Renesas M5M40R326 32Mbit DRAM Memory Structural Analysis

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1 August 13, 2004 Renesas M5M40R326 32Mbit DRAM Memory Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.

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3 Table of Contents Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Dielectrics 3.3 Metallization 3.4 Vias and Contacts 3.5 Peripheral Transistors and Poly 3.6 Access Transistor 3.7 DRAM Storage Cell 3.8 Isolation 3.9 Wells and Epi 4 DRAM Cell Analysis 4.1 DRAM Plan-View Analysis 4.2 Cross-Sectional Analysis (parallel to bitline) 4.3 Cross-Sectional Analysis (parallel to wordline) 5 Materials Analysis 5.1 SIMS Analysis of Dielectrics 5.2 TEM EDS Analysis of Dielectrics 5.3 TEM EDS Analysis of Metals 5.4 TEM EDS Analysis of Contacts and Gate Silicide 5.5 SRP Analysis of Wells and Substrate

4 Table of Contents Structural Analysis 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions Report Evaluation

5 Overview Overview 1.1 List of Figures 2 Device Overview Top and Bottom Package Photographs Plan-View Package X-Ray Side-View Package X-Ray Package Cross-Section Partially Decapsulated Package Lead Frame and Bond Wires Tilt View of Lead Frame, Bond Wires and Dice Wedge Bond to M5M40R326 DRAM Die M5M40R326 Die Die Marking Die Corner Die Corner Die Corner Die Corner Minimum Pitch Bond Pads Cross-Section Through Ball Bond Fuses 3 Process Analysis General View of M5M40R Die Edge Die Seal Passivation IMD IMD Pre-Metal Dielectric Nitride Sealing Layer Minimum Pitch Metal TEM Metal 3 Barrier Layer Minimum Pitch Metal TEM Metal 2 Barrier Layer Minimum Pitch Metal TEM Edge of Metal Minimum Pitch Via 2 s

6 Overview Minimum Pitch Via 1 s Via 1 and Poly 5 Cell Plate Minimum Pitch Contacts to Diffusion TEM Metal 1 Contact to Diffusion TEM CoSi 2 Grains Minimum Pitch Contacts to Polycide TEM Metal 1Contact to Polycide TEM Contact to WSi 2 Interface Minimum Gate Length Peripheral NMOS Transistor Minimum Gate Length Peripheral PMOS Transistor TEM Peripheral Transistors Minimum Pitch Poly TEM Access Transistors TEM Access Transistor and Contact TEM Bitline Contact TEM CoSi 2 Contact Layer TEM Gate Oxide SEM DRAM Capacitors TEM DRAM Capacitors High Resolution TEM of Capacitor Dielectric Capacitor Contact to Diffusion Poly 3 Via Polycide Over STI TEM STI Bevel SCM Peripheral N-Well and P-Well SCM Embedded P-Well 4 DRAM Cell Analysis Poly 5 Cell Plate Storage Capacitor Metal 1 Bitlines Poly 1 Wordlines Diffusion and STI DRAM Array Along Bitline Direction DRAM Capacitors Cell Plate and Capacitor Poly 3 Capacitor Contacts to Diffusion

7 Overview Metal 1 Bitline DRAM Array Along Wordline Direction DRAM Capacitors Poly 1 Wordline Capacitor Vias and Contacts Bitline Contacts 5 Materials Analysis SIMS Profile of Dielectrics TEM EDS of Silicon Nitride Passivation TEM EDS of PMD 2 Oxide Layer TEM EDS of PMD 1 BPSG Layer TEM EDS of Silicon Nitride Liner TEM EDS of Metal 2 TiN Cap Layer TEM EDS of Metal 2 TiN Barrier Layer TEM EDS of Metal 1 TiN Barrier Layer TEM EDS of Gate Silicide TEM EDS Metal 1 Contact to Substrate TEM EDS Spectrum Metal 1 Contact to Poly SRP of Shallow Peripheral N-Well SRP of Deep N-Well SRP of Peripheral P-Well SRP Embedded P-Well in DRAM Array 1.2 List of Tables Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor and Polycide Dimensions Access Transistor Dimensions