Low Temperature Dielectric Deposition for Via-Reveal Passivation.

Transcription

1 EMPC 2013, September 9-12, Grenoble; France Low Temperature Dielectric Deposition for Via-Reveal Passivation. Kath Crook, Mark Carruthers, Daniel Archard, Steve Burgess, Keith Buchanan SPTS Technologies, Ringland Way, Newport, NP18 2TA UK Abstract This paper reports on the development of low temperature (<190 C) plasma-enhanced chemical vapour deposition (PECVD) processes used to deposit silicon oxide / silicon nitride film stacks for use as passivation layers over exposed through-silicon vias in thinned (<60µm), 300mm silicon wafers, temporarily bonded to silicon or glass carriers. The deposition processes are optimized to provide excellent electrical isolation with the films having low leakage currents and high breakdown voltages. The deposited stacks are also used to compensate for wafer bow resulting from CMOS front-side wafer processes and so provide a method of preventing excessive bow when the thinned silicon wafer is de-bonded from its carrier. Crucially, electrical properties and stack stress are shown to be stable with no drift over time when exposed to atmosphere. Key words: 3D-IC, advanced packaging, TSV, dielectric, PECVD, via-reveal, passivation Introduction Emerging 3D-IC packaging technologies, incorporating through-silicon vias (TSV) offer system designers improved functionality combined with reduced package form factors. TSV s are typically manufactured using the via-middle approach where the vias are blindly etched, lined and filled during CMOS wafer front side processing. This approach requires that the TSV s be revealed on the back side of the wafer by grind and plasma etch steps. Layers of SiN and SiO deposited by PECVD serve to passivate and mechanically support the exposed TSV prior to bump/rdl formation and then chip-to-wafer or wafer-to-wafer bonding. A typical via-reveal process flow is shown in figure 1. Before the via-reveal process steps occur, CMOS device wafers are temporarily bonded to silicon or glass carriers and thinned to around 50µm. The temporary bonding adhesive imposes an (adhesivespecific) upper temperature limit of ~190 C for subsequent process steps and there is a risk of premature delamination of the device wafer if this limit is exceeded. The temperature constraint is especially challenging for the PECVD passivation processes as it is challenging to produce films of sufficient quality and stability at such low temperatures. The PECVD passivation layers also serve to maintain bow of the thinned silicon at manageable levels; ideally less than 10mm to allow the wafers to be handled through subsequent process steps. Full thickness (~770µm) CMOS wafers will typically Figure 1. Typical via-reveal process flow. (a) Device wafer temporarily is bonded face-down to carrier and silicon is thinned. (b) RIE Si etch to expose TSV with liner oxide intact ( soft reveal ) (c) deposit PECVD SiN-SiO passivation at <190 C to preserve adhesive integrity (d) CMP to expose via tips, stopping in the SiO layer.

2 have wafer bows within the range µm. When these incoming wafers are thinned to ~50µm to allow for chip stacking, bow will increase to several centimetres, making wafer handling impossible and can also likely causing cracking after debond. The stress of the back side passivation stack can be tailored to compensate for the incoming wafer bow and so produce wafers with manageable flatness after debond. To achieve this, low temperature PECVD films having both compressive and tensile stresses must be available. For example, CMOS devices with multiple layers of Cu-low k interconnect will typically have a front side tensile stress and so via-reveal passivation stacks with net tensile stress are required to compensate. Engineering of high quality, low temperature, TEOS-based SiO with tensile stress is extremely challenging as these films are susceptible to water re-absorption on exposure to atmosphere [1,2]. In this paper, we report on PECVD passivation stack engineering for via-reveal. Optimized SiN-SiO stacks deposited at <190 C provide excellent electrical isolation with leakage current densities <1E-9 A.cm -2 and breakdown voltages >10 MV.cm -1. Electrical leakage and stack stress are shown to be stable over several days when exposed to atmosphere. Compressively stressed SiN barrier films are combined with tensile SiO and SiN over-layers to produce stacks optimized for reliability and bow compensation. Bow is modeled using the Stoney equation and simple geometry and calculated values are in good agreement with measured bow. Experimental Dielectric films were deposited on to 300mm Si wafers using an SPTS Delta fxp, single-wafer cluster system designed for high volume manufacturing and configured with multi-wafer degas (MWD) and PECVD chambers as shown in Figure 2. Figure 2. PECVD cluster system with Multi-Wafer Degas chamber and 5 PECVD chambers The MWD chamber uses infra-red lamps to heat batches of 300mm wafers, allowing for degas times of up to 30 minutes with minimal reduction of system throughput. Such an approach is beneficial for bonded substrates, as long degas times ensure that the bonding adhesive is sufficiently outgassed prior to dielectric stack deposition, and can also prevent de-bonding due to thermal shock. Insufficient degas can lead to out-gassing from the adhesive during PECVD film deposition, with consequent disruption of plasma stability and degradation of film properties. Figure 3 shows outgassing characteristics of five typical silicon-onglass substrates. The outgassing rate was measured in a PECVD chamber at base pressure (<20mTorr) and peak wafer temperature was <150 C. The outgassing rate peaks after ~100 seconds with a further 300 seconds required for the pressure to recover fully. Wafer-to-wafer repeatability is small, compared to the difference in outgassing rate between different adhesive types. Figure 3. Typical out-gassing characteristics of bonded substrates. SiN and SiO films were deposited in a parallel plate PECVD reactor. The wafers sit on a platen configured with resistive heating and air-cooling, the latter to prevent energy from the plasma from overheating the wafer and platen assembly during deposition, and also during plasma cleaning of the PECVD chamber. Peak wafer temperature is verified as being <190 C using thermally sensitive adhesive dots applied to the front sides of the substrates prior to deposition. This approach, unlike thermocouplebased temperature measurement techniques, gives a truer indication of peak wafer temperature as it includes film deposition. The thermally sensitive dots have a sensitivity of ±3 C within the temperature range 180 C to 200 C. SiN and SiO films were deposited sequentially in the same PECVD chamber, this approach being preferred for best system productivity. SiN was deposited using a silane-based, ammonia-free process chemistry with MHz RF power applied to the showerhead. Film stress is tunable from -400 MPa to MPa where a negative stress denotes a compression. The ammonia-free chemistry was chosen because it produces SiN films of superior quality at low

3 temperatures. Figure 4 shows etch rates of ammoniabased and ammonia-free SiN films in 10: buffered hydrofluoric acid [BHF] with thermally grown silicon dioxide etch rate also shown for reference. The SiN films were deposited at <190 C. confirmation that the cracking threshold had been exceeded. Wafer bow modeling The modified Stoney equation was used to calculate wafer radius of curvature of the bowed wafer from measured stress: σ f = E 2 s. t s 6R. t f σ f = film stress E s = substrate biaxial Young s modulus = GPa T s = substrate thickness T f = film thickness R = radius of curvature Figure 4. 10:1 buffered HF wet etch rates of ammonia-based and ammonia-free SiN films, relative to thermal silicon dioxide. The ammonia-free SiN films have a much reduced etch rate, resulting from lower hydrogen content and higher density. This gives the ammoniafree films superior diffusion barrier properties. SiO films were deposited using a TEOS-based chemistry, this being preferred because of its superior step coverage. SiO stress is tunable from MPa to +200 MPa. For this work, the SiO deposition process is optimized so that deposited films do not absorb water on exposure to atmosphere. SiO films deposited using TEOS at low temperature can be hygroscopic and the water absorption causes instability with leakage current and stress drifting upwards over time [1]. Average thickness and uniformity of individual SiO and SiN films, and also film stacks was measured using a 49-point ellipsometry measurement with 3mm edge exclusion. Stress was calculated using a laser-based bow measurement system. The electrical leakage current density and breakdown voltage of the dielectric films were measured at room temperature using a metalinsulator-semiconductor (MIS) structure with low resistivity silicon as the lower electrode and evaporated aluminium dots with ~1.5mm diameter as the upper electrodes. Leakage current was measured at 2MV.cm -1 electric field strength and breakdown voltage was measured on 150nm SiO and SiN films with voltage swept from 0V to 200V in 5V increments. Film thickness cracking threshold was determined by using a diamond tip to score the film at the centre and edge of a 300mm wafer. An optical microscope is then used to check for crack propagation over a period of ~24 hours. Observation of spontaneous crack propagation was seen as Calculated values or radius of curvature are then used to calculate bow of 300mm wafers using simple trigonometry, with bow b estimated using the equation: b = d2 8R where d is wafer diameter and R is radius of curvature. The bow model accuracy was tested by comparing predicted and measured bows for a number of SiN- SiO film stacks typical of those used for via-reveal passivation. SiN Table 1. Predicted vs measured film stress SiN Stress (MPa) TEOS TEOS Stress (MPa) Stack Wafer Stack Measured Bow Modeled Bow Table 1 shows that there is less than 5% difference between measured and modeled bow. Dielectric stack engineering Requirements of the films and processes used for via-reveal passivation can be summarized as follows: 1. Peak wafer temperature during deposition compatible with the bonding adhesive used typically <190 C. 2. Processes must be compatible with silicon, silicon-on-silicon and siliconon-glass substrates. 3. Complete out-gassing of the bonding adhesive prior to film deposition. 4. Stability no changes to leakage current or stress after deposition. 5. Highly uniform films to minimize total thickness variation [TTV] of the substrate.

4 6. Good sidewall coverage of the revealed TSV with no corner voiding 7. Leakage current densities <1E-9 A.cm Breakdown electric field >8MV.cm -1 for reliability. 9. Good diffusion barrier performance prevention of impurity diffusion to the active silicon 10. Good interfacial adhesion of the passivation stack to silicon and also within the stack itself, where large stress gradients may exist. 11. Tunable film stress to allow for bow compensation on thinned silicon. 12. cracking threshold compatible with required overall stack thickness, typically 2.5µm - 3.0µm. 13. Hardness and elastic modulus compatible with subsequent Chemical Mechanical Planarization (CMP) process. Compressively stressed silicon nitride films are generally acknowledged to give best diffusion barrier properties, these being widely used in CMOS multi-level metal interconnect schemes [3]. For the via-reveal passivation stack, a PECVD SiN process with peak wafer temperature <190 C and film stress of -100 MPa was used. Figure 5 shows cross-sectional SEM images showing the crack-stopping capability of low temperature SiN films with both tensile and compressive stress. A crack deliberately propagated in a thick, overlying SiO film stops at the SiO-SiN interface and does not continue through the SiN. deposited with a tensile stress and the two films have both advantages and disadvantages for viareveal process integration. TEOS-based silicon oxide films with tensile stress show excellent sidewall coverage and deposition rate compared to silicon nitride, but maximum thickness is limited by the cracking threshold and leakage current increases as the tensile stress increases [4]. Figure 6. Maximum film thickness vs stress for low temperature TEOS SiO. Figure 6 plots the maximum thickness before spontaneous cracking occurs (cracking threshold) vs film stress for low temperature TEOS SiO films. The cracking threshold is less than 2µm for film stress > 150MPa. Tensile silicon nitride films were also investigated as a means of increasing the cracking threshold and providing improved electrical properties compared to TEOS SiO and so thereby offering greater tensile stress compensation capability. A <190 C SiN film was developed with tensile stress of +200 MPa and cracking threshold >7µm. The cracking threshold was demonstrated for films deposited on to bare Si and also on to a compressive SiN barrier film. Figure 5. SEM images of a) 2.0µm SiO over 0.3µm tensile SiN; b) 2.0µm SiO over 0.2µm compressive SiN For wafers with an incoming front side compressive stress, a SiN barrier with thicker (2-3µm) TEOS over-layer, both compressively stressed, can be used to provide both stress compensation and good sidewall coverage of the revealed TSV. When the incoming front side stress is tensile, then given the constraint of a compressively stressed SiN barrier layer, it is necessary to deposit thick over-layers with tensile stress to produce a passivation stack with net tensile stress. SiN and SiO films can both be Figure 7. Low temperature SiN stress vs time exposed to atmosphere at room temperature. Figure 7 shows stress stability of 1.4µm low temperature SiN films with nominal 200 MPa tensile stress. After 100 hours of exposure to atmosphere at room temperature, the stress has shifted by less than 5%.

5 tensile stress from 8.0µm multi-level interconnect of 70 MPa. The calculated resultant bow of the unthinned wafer is 0.35mm. The bow increases to more than 80mm when the wafer is thinned to 50µm and before back-side SiN is deposited. Figure 8. Leakage current density vs electric field strength for SiN films with stresses -400 MPa, -100 MPa and +200 MPa. Figure 8 shows electrical performance of low temperature SiN films with stress ranging from -400 MPa to +200 MPa. Leakage at 2MV.cm -1 is comparable for all films. The cracking threshold, stress stability and electrical performance suggest that low temperature SiN films are more suitable than TEOS SiO films for via-reveal passivation stacks where a net tensile stress is required. Figure 9. X-SEM images showing: a) low temperature PECVD SiN [compressive + tensile] passivation over Si step and b) high magnification image of corner. Figure 9a shows cross-sectional SEM images of a via-reveal passivation stack deposited over a silicon pillar, demonstrating minimum step coverage of 65%. Figure 9b shows the SiN film to be voidfree in the lower corner of the structure important for reliability. The stacks consists of 0.21µm compressive SiN (-100 MPa) with 2.25µm tensile SiN (+200 MPa), these stress values having been measured on full thickness silicon wafers. Adhesion of the compressive SiN film to silicon, and of the tensile SiN film to the compressive SiN film is excellent. Figure 10 shows the output of wafer bow modeling for a SiN stack on 300mm Si containing a 0.2µm, compressively stressed (-100MPa) barrier layer, and a second, thicker SiN layer with tensile stress to provide bow compensation. Figure 10 plots net wafer bow against the thickness and stress of the second SiN layer. Model inputs assume a Si thickness before thinning of 775µm and a front-side Figure 10. Net wafer bow vs SiN thickness and stress for 300mm silicon wafer thinned to 50µm. Figure 10 show that 2-3µm SiN films with stress in the range MPa will reduce the bow on the thinned silicon to <10mm, this being sufficient to enable further wafer processing. The model accuracy was confirmed by bow measurements on 50µm silicon after debond. Conclusions Low temperature (<190 C) PECVD SiN and SiO films are shown to be well suited for use in viareveal passivation stacks. Low temperature TEOS SiO films are more suitable to applications where a compressive stress is required, due to cracking threshold thickness limitations. Stable SiN films can, however, be produced with a tensile stress and cracking threshold of >7µm. These films, in combination with compressive SiN barrier layers, are effective in reducing net wafer bow to manageable levels on 300mm silicon wafers thinned to 50µm. References 1. K. Buchanan et al, Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing, in Proc. IEEE International Conference 3D Systems Integration (3DIC), San Francisco, CA, Sep 28 30, G. C. Schwartz, K. V. Srikrishnan [Eds], Handbook of Semiconductor Interconnection Technology, CRC Press, New York, 2006, pp R. A. Levy, Microelectronic Materials and Processes, Springer, 1989, p Crook et al, Dielectric Stack Engineering for Via-Reveal Passivation, in Proc. IEEE Electronic Components and Technology Conference, Las Vegas, NV, USA, May 2013