VLSI. Lecture 1. Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University. Based on slides of David Money Harris

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1 VLSI Lecture 1 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University Based on slides of David Money Harris

2 Goals of This Course Learn the principles of VLSI design Learn to design and implement state-of-the-art digital Very Large Scale Integrated (VLSI) chips using CMOS technology Complementary Metal Oxide Semiconductor (CMOS) Fast, cheap, robust, low power transistors Understand the complete design flow Be able to design state-of-the-art CMOS chips in industry Employ hierarchical design methods Use integrated circuit cells as building blocks Understand design issues at the layout, transistor, logic and register-transfer levels Use commercial design software in the lab VLSI 2

3 Course Information Instructor Jaeyong Chung ( 정재용, Office : 307, 3rd floor, Building 9 Tel : Office Hours : 1 hour after lecture class, or by appointment (send to schedule an appointment) Website: More on the course Prerequisites: logic design, basic computer organization Textbook: Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4 th Edition, 2010 Lectures and discussion in class will cover basics of course Homework, Laboratory exercises will help you gain a deep understanding of the subject EPC6071 Embedded System Design 3

4 licon Lattice Transistors are built on a silicon substrate licon is a Group IV material Forms crystal lattice with bonds to four neighbors VLSI 4

5 Dopants licon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) As B VLSI 5

6 p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode VLSI 6

7 nmos Transistor Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors O 2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is no longer made of metal* Source Gate Drain Polysilicon * Metal gates are returning today! O 2 n+ Body p n+ bulk VLSI 7

8 nmos Operation Body is usually tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Source Gate Drain Polysilicon O 2 n+ p n+ bulk S 0 D VLSI 8

9 nmos Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon O 2 n+ p n+ bulk S 1 D VLSI 9

10 pmos Transistor milar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Polysilicon Source Gate Drain O 2 p+ p+ n bulk VLSI 10

11 Power Supply Voltage GND = 0 V In 1980 s, V DD = 5V V DD has decreased in modern processes High V DD would damage modern tiny transistors Lower V DD saves power V DD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, VLSI 11

12 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g = 0 g = 1 nmos g d d OFF d ON s s s d d d pmos g ON OFF s s s VLSI 12

13 CMOS Inverter A Y V DD A 01 OFF ON Y ON OFF A Y GND VLSI 13

14 CMOS NAND Gate A B Y OFF ON OFF ON A 1 0 ON OFF Y B 10 ON OFF VLSI 14

15 CMOS NOR Gate A B Y A B Y VLSI 15

16 3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0 A Y B C VLSI 16

17 CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and crosssection of wafer in a simplified manufacturing process VLSI 17

18 Inverter Cross-section Typically use p-type substrate for nmos transistors Requires n-well for body of pmos transistors A GND Y V DD O 2 n+ diffusion n+ n+ p+ p+ p+ diffusion p substrate n well polysilicon metal1 nmos transistor pmos transistor VLSI 18

19 Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps A GND Y V DD p+ n+ n+ p+ p+ n+ p substrate n well substrate tap well tap VLSI 19

20 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line A Y GND V DD substrate tap nmos transistor pmos transistor well tap VLSI 20

21 Detailed Mask Views x masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal n well Polysilicon n+ Diffusion p+ Diffusion Contact Metal VLSI 21

22 Fabrication Chips are built in huge factories called fabs Contain clean rooms as large as football fields Courtesy of International Business Machines Corporation. Unauthorized use not permitted VLSI 22

23 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of O 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off O 2 p substrate VLSI 23

24 Oxidation Grow O 2 on top of wafer C with H 2 O or O 2 in oxidation furnace O 2 p substrate VLSI 24

25 Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Photoresist O 2 p substrate VLSI 25

26 Lithography Expose photoresist through n-well mask Strip off exposed photoresist Photoresist O 2 p substrate VLSI 26

27 Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Photoresist O 2 p substrate VLSI 27

28 Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn t melt in next step O 2 p substrate VLSI 28

29 n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Ion Implanatation Blast wafer with beam of As ions Ions blocked by O 2, only enter exposed O 2 n well VLSI 29

30 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps p substrate n well VLSI 30

31 Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with lane gas (H 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor Polysilicon Thin gate oxide p substrate n well VLSI 31

32 Polysilicon Patterning Use same lithography process to pattern polysilicon Polysilicon Polysilicon Thin gate oxide p substrate n well VLSI 32

33 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nmos source, drain, and n-well contact p substrate n well VLSI 33

34 N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn t melt during later processing n+ Diffusion p substrate n well VLSI 34

35 N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion n+ n+ n+ p substrate n well VLSI 35

36 N-diffusion cont. Strip off oxide to complete patterning step n+ n+ n+ p substrate n well VLSI 36

37 P-Diffusion milar set of steps form p+ diffusion regions for pmos source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ p substrate n well VLSI 37

38 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Contact p+ n+ n+ p+ p+ n+ Thick field oxide p substrate n well VLSI 38

39 Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires Metal p+ n+ n+ p+ p+ n+ Metal Thick field oxide p substrate n well VLSI 39

40 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of l = f/2 E.g. l = 0.3 mm in 0.6 mm process VLSI 40

41 mplified Design Rules Conservative rules to get you started VLSI 41

42 Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4l / 2l, sometimes called 1 unit In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long VLSI 42

43 Summary MOS transistors are stacks of gate, oxide, silicon Act as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip! VLSI 43

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