Wafer Process. For University Ver1.1. October, Renesas Technology Corp., All rights reserved.

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1 Wafer Process Overseas Design Support Center Shigeru Shimada October, 2007 For University Ver1.1

2 Contents of Wafer Process 1. What is semiconductor? 2. Why silicon is mot popular? 3. N type and P type Silicon 4. Why silicon wafer is round? 5. Crystal growth technology 6. What is MOS? 7. Basic steps of LSI wafer process 2

3 Contents of Wafer Process continued 8. Explanation of component process Oxidation, Plasma, CVD, Sputtering, Lithography (Stepper and Scanner), Device Isolation, Dry Etching, Plasma ashing, Ion Implantation, Annealing, Ohmic contact, Barrier metal, and CMP) 9. Modern CMOS Process 10. Reference 3

4 What is a Semiconductor? A semiconductor is a material that behaves in between a conductor and an insulator. At room temperature, it conducts electricity more Easily than an insulator, but less readily than a conductor. At very low temperatures, pure or intrinsic semiconductors behave like insulators. At higher temperatures though or under light, intrinsic semiconductors can become conductive. The addition of impurities to a pure semiconductor can also increase its conductivity. 4

5 What is a Semiconductor? glass germanium gold rubber silicon cupper ceramic aluminum Insulator Semiconductor Conductor Resistivity 8 10 ohm cm 4 10 ohm cm 5

6 Why Silicon is a most popular Semiconductor? Silicon exists everywhere. High quality Oxide can be made on Silicon. Raw material Raw material are silica stone and silica sand made from SiO2. It needs the electric power to make metal Silicon, so the countries where the electric power cost is low are the producing countries. They used to be China, Brazil, Russia, South Africa and Norway, and very recently, Australia,Malaysia and Viet Nam are coming up. Raw material Metal Silicon Poly Crystal silicon Single Crystal Silicon(Eleven Nine: %) 6 Crystal pulling method : Czochralski (CZ) method, Floating Zone method

7 Crystal structure of Silicon Silicon belongs to the cubic crystal system and has a diamond structure. This is characterized by having each atom symmetrically surrounded by four equally spaced neighbors. 7

8 Crystal planes (100) plane (110) plane (111) plane 8

9 Periodic Table Group III 5 B 13 Al 31 Ga IV 6 C 14 Si 32 Ge V 7 N 15 P 33 As + 9

10 N type and P type Silicon Silicon crystal is rarely used in the pure state. Usually, some impurity called a dopant is added in small controlled amount. If a boron atom is substituted for a silicon atom in the silicon lattice, the boron atom with only three of available electrons would be able to form bonds to only three of the four adjacent silicon atom and a hole would be formed. 10

11 N type and P type Silicon Continued + Si 14+ Si 14+ Si 14+ Si 14+ Si 14+ Si 14+ Si 14+ Si 14+ Si 14+ Si 14+ Si 14+ Si 14+ Si 14+ B 5+ Si 14+ Si 14+ Si 14+ Si

12 It is very easy for an electron from a nearby silicon to silicon bond to fall into this hole and effectively move the hole away from the boron atom. Since the boron atom will accept an electron, boron and the other elements of Group III(B, In, Ga) are refered to as acceptors. Silicon with acceptor is called as P type silicon, since Positive holes are generated and contribute a current flow. 12

13 If a Group V atom, such as phosphorus, is introduced into the silicon lattice, it will have an extra electron which may easily break away, becoming a conduction electron. The phosphorus is refered to a donor, since it donates an electron to the conduction band. Other donors are As and Sb. Silicon with donor is called as N type silicon, since Negative electrons are generated and contribute the current flow. Si 14+ Si 14+ Si 14+ Si 14+ P 15+ Si 14+ Si 14+ Si 14+ Si

14 Properties of Silicon and Silicon Oxide 14

15 Why Silicon wafer is round? Singlecrystal Silicon Silicon / wafer 15

16 Crystal Growth Technology FZ method Polycrystal rod FZ method Melting Singlecrystal silicon Heat Coil Seed crystal Seeding CZ method Seed crystal Heater Quartz Crucible Seeding Singlecrystal silicon CZ method Silicon melt 1420 Reference : Seibundo Shinkosha Inc. Guide with semiconductor pictures (1995) 16

17 What is MOS? M(Metal)O(Oxide)S(Semiconductor) Metal Oxide Semiconductor MOS Structure 17

18 Basic structure of MOS Transistor Electrode: Highly doped PolySilicon Source and Drain: Highly doped N+ Diffusion Gate Oxide: Silicon Oxide Gate Source Drain N + Electrode Gate Oxide N + ptype Substrate Circuit symbol 18 N channel MOS Transistor Substrate

19 Basic Steps of LSI wafer process A) Thin Film formation: Oxidation: Thermal Oxidation CVD(Chemical Vapor Deposition): Deposition of PolySilicon, Silicon Nitride, Silicon Oxide Evaporation, Sputtering: Aluminum, Metal, Silicide (Alloy of Silicon and other metal) Plating: Cu B) Patterning Photolithography: Forming photoresist patterns using UltraViolet beam Etching: Wet or Dry etching using Photoresist as a masking material 19

20 Basic Steps of LSI wafer process Continued C) Introduction of impurity Diffusion:Diffusion of Solid or vapor phase Ion Implantation:Ionized impurity bombardment using electric field D) Cleaning: Wafer cleaning using acid or ultra pure water These four steps are repeated during wafer process. 20

21 Principle of Oxidation 1. Dry Oxidation Oxidation in Dry Oxygen Used to form the thin oxide Si+O 2 (Gas) SiO 2 2. Wet Oxidation Oxidation in steam Used to form the thick oxide Si+2H 2 O(Gas) SiO 2 +2H 2 (Gas) Since the diffusion coefficient of H 2 O is larger than O 2, the wet oxidation can form thicker oxide in shorter time. 21

22 Plasma A plasma is typically an ionized gas,, and is usually considered to be a distinct phase of matter in contrast to solids, liquids, and gases because of its unique properties. Ionized" means that at least one electron has been dissociated from a proportion of the atoms or molecules. The free electron charges make the plasma electrically conductive so that it responds strongly to electromagnetic fields. 22

23 Typical PECVD (Plasma Enhanced CVD) equipment configuration RFpower input Electrode Plasma Gas Outlet Gas Inlet Ground Heater Silicon wafer 23

24 Principle of CVD The material gas is transferred to wafer surface where the reaction occurs and the reaction product deposits on wafer. Energy(heat, plasma, light, etc) Material gas Silicon wafer thin film and byproduct Thermal decomposition: SiH4 Si +2H2 Oxidation: SiH4 + 2O2 SiO2 + 2H2O Reaction: 3SiH4 + 4NH3 Si3N4 + 12H2 24

25 Sputtering Sputtering is a physical process whereby atoms in a solid target material are ejected into the gas phase due to bombardment of the material by energetic ions. It is commonly used for thinfilm deposition. 25

26 Sputtering Continued Matching Network RFpower input Electrode RF Generator Argon Plasma Target Vacuum Ground Sputtering Gas Inlet (Ar( Ar) Silicon wafer 26

27 What is Lithography Technology? This is a technology where semiconductor circuit patterns formed on photomask(mask) are repeatedly built on a wafer with high accuracy. Wafer process flow chart Film Forming Photomask CMP (Planarization) Si wafer Resist coating Film Expose Develop Etching or ion implantation Film forming process (Developing) Resist Coating Expose mask pattern Resist removal 27 Next process Resist pattern formation Etching Resist removal

28 Photoresist There are two types of photoresist, one is positive (posi) resist and the other is negative (nega) resist. When posi resist is exposed and developed, the resist of exposed portion is dissolved and when nega resist is exposed and developed, the exposed portion remains. We use posi resist for fine patterning. 28

29 Photoresist coating Photoresist is dropped on a wafer, then the wafer is spun to spread the resist. Photoresist is sensitive to a short wave length. So a light of longer wave length is used in the clean room. Spin Coater 29

30 Photolithography Machine Formation Masking blade Light source High eyes lens 1 st Zoom condenser Condenser lens Illumination system Reticule (mask) 1 st Zoom condenser 2 nd Input lens Relay optics Stopper Collimator lens Reticule Excimer laser Beam monitor Reduction projection lens 1 st input lens Projection lens Image shift Wafer Laser overdraw ND filter Wafer stage Manufacturers Nikon Cannon ASML For example refer to Cannon KrF sstepper FPA3000EX6 illumination system <Parameter related to exposure> Light source : Exposure wavelength Illumination : σ, Variable illumination Mask : Phase shift mask, magnification Reduction projection lens: NA, aberration Wafer stage: X,Y, Z position, Positioning accuracy 30

31 Types of Photolithography Machines Stepper and Scanner Stepper The target area for exposure (shot) is illuminated thoroughly and exposed entirely. Mask The area exposed to light Wafer Scanner The target area for exposure (shot) is illuminated partially in the form of a slit, and exposed by synchronously scanning the reticule and the wafer stage. 31

32 Schematic diagram of an RFpowered plasma etch system Matching Network RFpower input Electrode RF Generator Plasma Plasma sheaths Gas Inlet Ground Silicon wafer Gas Outlet 32

33 Dry Etching Figure 1 :Example of etching flow Film to be etched Photoresist Deposition Photolithography Etching Removal of photoresist Table 1 Main processed film Insulation film SiO2, Si3N4, Lowk material Wiring material AlCu, W, WSi2, CoSi, TiN, PolySi, Pt, Ru High dielectric material Ta2O5, BST Antireflection film Organic ARC, Inorganic ARC (psion, etc.) BST:(Ba,Sr)TiO 3 ARC:AntiReflection Reflection Coating 33

34 Dry Etching Continued Figure 2 Crosssection of etching P.R PolySi LResist LEtch P.R PolySi PolySi PolySi SiO2 Anisotropic etching SiO 2 Isotropic etching SiO2 CD shift: LResist LEtch 34

35 Reaction during Dry Etching Generation of etching seeds Plasma Absorption of etching seeds Dissociation of etching seeds Formation of reaction products Detachment of reaction products Detachment of adsorbent carbon 35

36 Plasma ashing In semiconductor manufacturing plasma ashing is the process of removing the photoresist from an etched wafer. Using a plasma source, a monatomic reactive species is generated. Oxygen or fluorine are the most common reactive species. The reactive species combines with the photoresist to form ash which is removed with a vacuum pump. Typically, monatomic (single atom) oxygen plasma is created by exposing oxygen gas (O2) to ionizing radiation. At the same time, many free radicals are formed which could damage the wafer. 36

37 Plasma ashing Continued Newer, smaller circuitry is increasingly susceptible to these particles. Originally, plasma was generated in the process chamber, but as the need to get rid of free radicals has increased, many machines now use a downstream Plasma configuration, where plasma is formed remotely and channeled to the wafer. This allows electrically charged particles time to recombine before they reach the wafer surface, and prevents damage to the wafer surface. 37

38 Ion Implantation Ion implantation is used to alter the surface properties of semiconductor materials. By doping the desired elements on the semiconductor substrate, or in the thin film on the substrate, PN junction is formed or surface properties are controlled by thermal treatment, recovery of dislocated crystal or implanted impurity atoms are substituted at the lattice point and activated electrically (referred to as Anneal). (Usage) Well formation Isolation between devices Source drain formation etc. (Requirement from device) Shallow junction formation 38

39 Features of Ion Implantation Can highly control the concentration and implantation depth. Photoresist can be used as a mask for a selective implantation. (Room temperature process) Can dope at low concentration. Conventional impurity doping technology such as thermal diffusion has replaced the thermal diffusion with ion implantation. 39

40 Implantation for Vth control If the acceptor ion is implanted to NMOS, then Vth of NMOS is increased. If the donor ion is implanted to NMOS, Vth of NMOS is lowered. Vice verse to PMOS. Delta Vth = Qimp/Cox Where Qimp=q*N, N=Dosage of implantation and Cox is Gate Capacitance. q= (C). Cox=ε 0 *ε r /Tox(ε 0 =8.85E12F/m, ε r =3.9) 40

41 Purpose of Annealing Annealing is done for the purpose of 1. Damage relaxation from the bombardment of impurity 2. Activation of doped impurity 3. Diffusion of doped impurity 41

42 Model of defect recovery and ion activation by annealing Process flow Before implantation Alignment model of Si atom Description Si atom Dopant ion Si atoms are aligned & bonded. However, only Si atoms may allow a small current to pass. After implantation Ion beam Due to ion Implantation, dopant and Si atoms collide, alignment is disturbed (defect occurred), and the covalent bonds break. In this case, implanted ions are not bonded to Si atoms, but is in between Si atoms. (Interstitial atom) In this condition, a current does not flow even though dopant ion exists. (Inactive condition) After annealing By annealing, the alignment of Si atoms is recovered, and ions also get bond to Si. Therefore a current can flow. (Ion activation) 42

43 Ohmic contact and barrier metal Ohmic Contact An ohmic contact refers to the contact between a metal and a semiconductor to allow carriers to flow in and out of the semiconductor. An ideal ohmic contact must have no effect on device performance, i.e., it must be capable of delivering the required current with no voltage drop between the semiconductor and the metal. In real life, therefore, an ohmic contact must have a contact resistance that is as small as possible, to make it negligible in comparison to the bulk or spreading resistance of the semiconductor. 43

44 Materials which form ohmic contact to Silicon Semiconductor Si Bandgap Energy Type Contact Material Technique(s) Alloy Temp n,p CoSi2 Direct Reaction* n,p TiSi2 Direct Reaction* n,p WSi2 Direct Reaction* n,p TaSi2 Direct Reaction* n,p PtSi Direct Reaction* n,p Al Evaporation 1.12 n (1% Sb) Evaporation 44

45 Barrier Metal A barrier metal is a material used in integrated circuits to chemically isolate semiconductors from soft metal interconnects, while maintaining an electrical connection between them. For instance, a layer of barrier metal must surround every copper interconnection in modern copperbased chips, to prevent diffusion of copper into surrounding materials. As the name implies, a barrier metal must have high electrical conductivity in order to maintain a good electronic contact, while maintaining a low enough copper diffusivity to chemically isolate the copper conductor from the silicon below. 45

46 CMP ChemicalMechanical Polishing Wafer carrier Slurry Polishing Table Wafer (facing down) Polishing Pad Silicon Polishing pad Oxide Slurry Closeup of wafer/pad interface 46

47 Modern CMOS Technology Followings are the typical CMOS wafer process. 47

48 Device Isolation Comparison of LOCOS and STI Comparison of below figures illustrates both similarities and the differences in LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation). Both process produce thick SiO2 regions laterally isolating adjacent device structure. However, STI produces more compact structures because there is very little lateral encroachment of the isolation structure into adjacent active regions. STI is used below 0.35um process. Thermally oxidized SiO2 LOCOS CVD deposited SiO2 STI 48

49 Active Region Formation Active Region means the region where active devices such as NMOS and PMOS transistors are formed. Following slides show the wafer process using LOCOS device isolation. STI process is explained as an option process. 49

50 Following initial cleaning, an SiO2 layer is thermally grown on the silicon substrate. A Si3N4 layer then deposited by LPCVD. Photoresist is spun on the wafer to prepare for the first masking operation. Photoresist SiO2 (40nm) Si3N4 (80nm) Si, (100), P Type, 5~50 ohmcm LPCVD: Low Pressure CVD 50

51 Mask 1 patterns the photoresist. Photomask(Reticule) Photoresist (Posi( type) SiO2 (40nm) Si3N4 (80nm) Si, (100), P Type, 5~50 ohmcm 51

52 The Si3N4 layer is removed where it is not protected by the photoresist by dry etching. 52

53 After photoresist stripping, the field oxide is grown in an oxidizing ambient (1000 C 90 min. in H2O). The thickness is about 0.5um. The oxidation extends under the nitride edge because the oxidant (H2O) can diffuses sideways. Field region: Isolation regions between Active regions. 53

54 Process option for Device Isolation Shallow Trench Isolation 54

55 After Mask 1 defines the photoresist, the Si3N4, SiO2 and Si trenches are successively plasma etched to create the shallow trenches for isolation. 55

56 A thin liner oxide is thermally grown in the trenches. The nitride prevents any additional oxidation on the top surface of the wafer. 56

57 SiO2 is deposited to completely fill the trenches. This would typically requires um of SiO2 to be deposited, depending on the trench depth and geometry. 57

58 The deposited SiO2 layer is polished back using CMP to produce a planar structure. 58

59 N and P WELL Formation 59

60 Photoresist is used to mask the regions where PMOS devices will be built using Mask 2. A boron implant provides the doping for the P wells for the NMOS devices. Boron P Type Implant 60

61 Photoresist is used to mask the regions where NMOS devices will be built using Mask 3. A phosphorus implant provides the doping for the N wells for the PMOS devices. Phosphorus N Type Implant P Type Implant 61

62 A high temperature drivein (1000~1100 C and 4 to 6 hours) completes the formation of the N and P wells. Well depth will be 2 to 3 um after the wafer process finishes. N Well P Well 62

63 Gate Formation Before forming Gate oxide, channel implant ( Vth controlled implant) is done. Vth is given by the following equation where QI Q is implant dose. This equation assumes that the entire implant dose is located in the near surface region, inside the MOS channel depletion region. 63

64 After spinning photoresist on the wafer, Mask 4 is used to define the NMOS transistors. A boron implant adjusts the Nchannel Vth. Boron N Well P P Well 64

65 After spinning photoresist on the wafer, Mask 5 is used to define the PMOS transistors. A arsenic implant adjusts the Pchannel Vth. Arsenic N N Well P P Well 65

66 After etching back the thin oxide to bare silicon, the gate oxide (~10nm) is grown for the MOS transistors. N N Well P P Well 66

67 A layer of polysilicon (0.3~0.5um) is deposited. Ion implantation of phosphorus follows the deposition to heavily dope the poly. This can produce lowsheetresistance poly layers. N N Well P P Well 67

68 Photoresist is applied and Mask 6 is used to define the regions where MOS gates are located. The polysilicon layer is then etched using plasma etching. N N Well P P Well 68

69 LDD (Lightly Doped Drain) Formation Decreasing the channel length in the device to 0.5um without reducing the supply voltage 5 1 increases the average field to about 10 Vcm. This high field is large enough to cause a problems in semiconductor devices. Such problems are often called hot electron problems. Carriers at high energies can cause impact ionization which creates additional hole electron pairs. LDD structure is applied to relax the field. 69

70 Mask 7 is used to cover the PMOS devices. A phosphorus implant is used to form the LDD (extension) region in the NMOS devices. Phosphorus N N Well P P Well N Implant 70

71 Mask 8 is used to cover the NMOS devices. A boron implant is used to form the LDD (extension) region in the PMOS devices. Boron N N Well P Implant P P Well N Implant 71

72 A conformal layer of SiO2 is deposited on the wafer in preparation for sidewall spacer formation. N N Well P Implant P P Well N Implant 72

73 Etchback process After oxide is deposited, and without any mask, oxide is etched using anisotropic dry etching. Oxide at the steps remains unetched. Oxide deposition Deposition is isotropic. Anisotropic dry etching 73

74 The deposited SiO2 layer is etched back anisotropically, leaving sidewall spacers along the edges of the polysilicon. N N Well P Implant P P Well N Implant 74

75 Source/Drain Formation 75

76 After growing a thin screen oxide, photoresist is applied and Mask 9 is used to protect the PMOS transistors. An arsenic implant then forms the NMOS source and drain regions. Arsenic N N Well P Implant P P Well N+ Implant 76

77 After applying photoresist, Mask 10 is used to protect the NMOS transistors. A boron implant then forms the PMOS source and drain regions. Boron N N Well P+ Implant P P Well N+ Implant 77

78 A final hightemperature drivein (900 C, 30 min. or c, 1min.) activates all the implanted dopants and diffuses junction to their final depth. P+ N N Well P P+ N+ P Well N+ 78

79 Contact and Local Interconnection Formation 79

80 Un masked oxide etch removes the SiO2 from the device source drain regions and from the top surface of the polysilicon. N P P+ N Well P+ N+ P Well N+ 80

81 Titanium is deposited on the wafer surface by sputtering. N P P+ N Well P+ N+ P Well N+ 81

82 The titanium is reacted in an N2 ambient, forming TiSi2 where it contacts silicon or polysilicon and TiN elsewhere. TSi2 TiN N P P+ N Well P+ N+ P Well N+ 82

83 Photoresist is applied and Mask 11 is used to define the regions where TiN local interconnects will be used. The TiN is then etched. N P P+ N Well P+ N+ P Well N+ 83

84 After stripping the photoresist, a conformal SiO2 layer is deposited by LPCVD. N P P+ N Well P+ N+ P Well N+ 84

85 CMP (ChemicalMechanical Polishing) is used to polish the deposited SiO2 layer. This planarizes the wafer surface. N P P+ N Well P+ N+ P Well N+ 85

86 Photoresist is spun onto the wafer. Mask 12 is used to define the contact holes. The deposited SiO2 layer is then etched to allow connections to the silicon, polysilicon and local interconnect regions. N P P+ N Well P+ N+ P Well N+ 86

87 A thin TiN barrier/adhesion layer is deposited on the wafer by sputtering, followed by deposition of a W layer by CVD. W TiN barrier/adhesion layer N P P+ N Well P+ N+ P Well N+ 87

88 CMP is used to polish back the W and TiN layers, leaving a planar surface on which the first level of metal can be deposited. N P P+ N Well P+ N+ P Well N+ 88

89 Aluminum is deposited on the wafer by sputtering. Photoresist is spun on the wafer and Mask 13 is used to define the first level of metal. The Al is then plasma etched. Aluminum N P P+ N Well P+ N+ P Well N+ 89

90 The steps to form the second level of Al interconnect follow those in previous slides from P Mask14 is used to define via holes between metal1 and metal2. Mask15 is used to define metal2. N P P+ N Well P+ N+ P Well N+ 90

91 The last step in the process is deposition of a final passivation layer, usually Si3N4 deposited by PECVD. The last Mask16 is used to open holes in this layer over the bonding pads (not shown). N P P+ N Well P+ N+ P Well N+ 91

92 The advantage of Cu wiring The advantages of Cu wiring over Aluminum are as follows. 1.Lower resistivity than Aluminum. (Al:2.8u ohm cm, Cu:1.7u ohm cm) Can be thinner than Al with the same resistance, which reduces capacitance. 2.Higher melting point and less electromigration. 3.Less stressmigration. 92

93 The advantage of Cu wiring Continued The disadvantages 1.Cu is one of the harmful elements to Si and SiO2. 2.Cannot be deposited by CVD. 3.Cannot be dryetched. 4.Weak cohesion to SiO2 5. TDDB lifetime is shorter than Al and W. (TDDB:Time Dependence on Dielectric Breakdown ) Damascene process is the best one for Cu. 93

94 Metal1 formation Damascene process Interlayer dielectric (IDL), insulator between metal is deposited. IDL is polished. Metal1 1 Photo is done and IDL is etched. Barrier metal (not shown) are deposited. N P P+ N Well P+ N+ P Well N+ 94

95 Cu seed is sputtered, then plated to fill the recess. Cu is polished back using CMP. Metal 1 N P P+ N Well P+ N+ P Well N+ 95

96 Metal2 formation Dual Damascene process Insulator, Etching stopper and insulator between Metal1 and Metal2 are deposited. Via1 is opened. N P P+ N Well P+ N+ P Well N+ 96

97 Metal2 photo is done and insulator is etched. N P P+ N Well P+ N+ P Well N+ 97

98 Barrier metal is deposited (not drawn). Cu (seed) is sputtered and plated to fill the recess. Cu is polished back by using CMP. Via and Metal recess formation is called Dual damascene process. N P P+ N Well P+ N+ P Well N+ 98

99 Comparison of wiring structure P+ N N Well P+ N+ P P Well N+ P+ N P N Well P+ N+ P Well N+ 99

100 Complete Cross Section 100

101 Gate Gate Drain Source Drain Source S Sub (N WELL) G D S Sub (P WELL) G D N P P+ N Well P+ N+ P Well N+ PMOS NMOS 101

102 Reference SILICON VLSI TECHNOLOGY Fundamentals, Practice and Modeling By J.D. Plummer, M.D. Deal and P.B. Griffin Prentice Hall,

103 2006. Renesas Technology Corp., All rights reserved.