Because of equipment availability, cost, and time, we will use aluminum as the top side conductor

Size: px
Start display at page:

Download "Because of equipment availability, cost, and time, we will use aluminum as the top side conductor"

Transcription

1

2

3 Because of equipment availability, cost, and time, we will use aluminum as the top side conductor

4 Top Side Conductor vacuum deposition Aluminum sputter deposit in Argon plasma CVC 601-sputter deposition tool

5 A conductor metal is vacuum deposited on to the wafer Aluminum will be used instead of silver Sputtered aluminum

6 Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask or stencil to stop the light. Photolithography is used extensively in the progression of microelectronics. Today, because of the sizes involved in current computer microprocessor devices, other methods like direct patterning using electron beams are used. Photolithography is still used for dimensions down to about 0.5um. The wavelength of UV light is um.

7 Top side conductor grid is created using a transparency mask The top side conductor grid is created on a transparency sheet to keep cost low Once top side conductor grid design is finalized, a chrome on glass professional mask can be made to go into mass production

8 Top side conductor Because of Cameron tester limitations (1.0A) cell size is limited to about 65mm x 65mm max

9 UV light sensitive material called photoresist is spin coated on to the aluminum conductor on the top side of the wafer (polished side) Positive photoresist Aluminum Silicon wafer

10 Wafers are spin coated with Shipley 1813 UV sensitive photoresist spin coating produces a uniform coating Run a test spin without the photoresist to verify operation Spin speed is set here. Spin speed is 4K rpm Close lid and apply photoresist through the lid opening A vacuum chuck holds the wafer Light sensitive material is stored in amber dropper bottles Use 1813

11 Transparency is used as a photomask. Cells can be designed to various sizes Cells can be of various sizes but must line up for saw cutting

12 The transparency is called a photo mask. Production photo masks would be made on glass plates with high precision patterns. Transparency mask A glass plate is placed on top of transparency mask to keep it flat and prevent light to leak under the transparency Glass plate Positive photoresist Aluminum Silicon wafer

13 HTG mask aligner is used to provide the UV Clear glass plates are used to make sure the transparency lays flat to the wafer light source The UV light source is a mercury vapor lamp at 436nm wavelength UV light with filter surrounding it Exposure time set on timer Wafer is held by vacuum, mask is placed on top and brought into contact with wafer

14 Ultraviolet light is projected down on to the photoresist coated wafer UV light Glass plate Aluminum Silicon wafer Exposed photoresist

15 The wafer is developed, leaving photoresist where no UV light has penetrated the mask Aluminum Silicon wafer Unexposed photoresist

16 Solitec automatic developer vacuum chuck holds wafer, tool develops, rinses, and dries the wafer Minimum vacuum level is 15 on vacuum gauge Vacuum switch Start switch hold down until tool starts

17 The wafer is immersed in the aluminum etch and the top side aluminum conductor is dissolved (etched away) Because it is a liquid etch and can undercut the photoresist it is important to remove the wafer from the etchant as soon as the pattern clears Liquid aluminum etchant PR Al PR PR PR Al Al Al Silicon wafer

18 Unwanted aluminum is etched away using the aluminum etchant at about 80 0 C Aluminum 80 o C Aluminum etch contains strong acids and all safety precautions are needed

19 After etching, the top conductor grid pattern will be left on the wafer. The photoresist is removed leaving the top side aluminum grid Completed topside conductor Al Al Al Al N- region P type silicon wafer

20 Once the top side conductor grid is complete, the back side conductor can be deposited, again aluminum sputtered with the CVC 601 will be used Al Al Al Al N- region P type silicon wafer Backside aluminum

21 Assignment Complete the photolithography worksheet

micro resist technology

micro resist technology Characteristics Processing guidelines Negative Tone Photoresist Series ma-n 1400 ma-n 1400 is a negative tone photoresist series designed for the use in microelectronics and microsystems. The resists are

More information

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther EECS 40 Spring 2003 Lecture 19 Microfabrication 4/1/03 Prof. ndy Neureuther How are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other films Pattern transfer by lithography

More information

Microelectronic Device Instructional Laboratory. Table of Contents

Microelectronic Device Instructional Laboratory. Table of Contents Introduction Process Overview Microelectronic Device Instructional Laboratory Introduction Description Flowchart MOSFET Development Process Description Process Steps Cleaning Solvent Cleaning Photo Lithography

More information

Low-temperature, Simple and Fast Integration Technique of Microfluidic Chips by using a UV-curable Adhesive

Low-temperature, Simple and Fast Integration Technique of Microfluidic Chips by using a UV-curable Adhesive Low-temperature, Simple and Fast Integration Technique of Microfluidic Chips by using a UV-curable Adhesive Supplementary Information Channel fabrication Glass microchannels. A borosilicate glass wafer

More information

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing CS/ECE 5710/6710 CMOS Processing Addison-Wesley N-type Transistor D G +Vgs + Vds S N-type from the top i electrons - Diffusion Mask Mask for just the diffused regions Top view shows patterns that make

More information

Complexity of IC Metallization. Early 21 st Century IC Technology

Complexity of IC Metallization. Early 21 st Century IC Technology EECS 42 Introduction to Digital Electronics Lecture # 25 Microfabrication Handout of This Lecture. Today: how are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other

More information

Fabrication Technology

Fabrication Technology Fabrication Technology By B.G.Balagangadhar Department of Electronics and Communication Ghousia College of Engineering, Ramanagaram 1 OUTLINE Introduction Why Silicon The purity of Silicon Czochralski

More information

Photolithography I ( Part 2 )

Photolithography I ( Part 2 ) 1 Photolithography I ( Part 2 ) Chapter 13 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Bjørn-Ove Fimland, Department of Electronics and Telecommunication, Norwegian University of Science

More information

micro resist technology

micro resist technology Characteristics Processing guidelines Negative Tone Photoresist Series ma-n 2400 ma-n 2400 is a negative tone photoresist series designed for the use in micro- and nanoelectronics. The resists are available

More information

Microfabrication of Integrated Circuits

Microfabrication of Integrated Circuits Microfabrication of Integrated Circuits OUTLINE History Basic Processes Implant; Oxidation; Photolithography; Masks Layout and Process Flow Device Cross Section Evolution Lecture 38, 12/05/05 Reading This

More information

Chapter 3 Silicon Device Fabrication Technology

Chapter 3 Silicon Device Fabrication Technology Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale

More information

Processing guidelines. Negative Tone Photoresist Series ma-n 2400

Processing guidelines. Negative Tone Photoresist Series ma-n 2400 Characteristics Processing guidelines Negative Tone Photoresist Series ma-n 2400 ma-n 2400 is a negative tone photoresist series designed for the use in micro- and nanoelectronics. The resists are available

More information

Mostafa Soliman, Ph.D. May 5 th 2014

Mostafa Soliman, Ph.D. May 5 th 2014 Mostafa Soliman, Ph.D. May 5 th 2014 Mostafa Soliman, Ph.D. 1 Basic MEMS Processes Front-End Processes Back-End Processes 2 Mostafa Soliman, Ph.D. Wafers Deposition Lithography Etch Chips 1- Si Substrate

More information

Introduction to Nanoscience and Nanotechnology

Introduction to Nanoscience and Nanotechnology Introduction to Nanoscience and Nanotechnology ENS 463 2. Principles of Nano-Lithography by Alexander M. Zaitsev alexander.zaitsev@csi.cuny.edu Tel: 718 982 2812 Office 4N101b 1 Lithographic patterning

More information

Schematic creation of MOS field effect transistor.

Schematic creation of MOS field effect transistor. Schematic creation of MOS field effect transistor. Gate electrode Drain electrode Source electrode Gate oxide Gate length Page 1 Step 0 The positively doped silicon wafer is first coated with an insulating

More information

Making of a Chip Illustrations

Making of a Chip Illustrations Making of a Chip Illustrations 22nm 3D/Trigate Transistors Version April 2015 1 The illustrations on the following foils are low resolution images that visually support the explanations of the individual

More information

Photolithography Process Technology

Photolithography Process Technology Contents Photolithography Process - Wafer Preparation - Photoresist Coating - Align & Expose - Photoresist Development Process Control CD Measurement Equipment Expose System & Wafer Track Consumables Chemicals

More information

Fabrication and Layout

Fabrication and Layout ECEN454 Digital Integrated Circuit Design Fabrication and Layout ECEN 454 3.1 A Glimpse at MOS Device Polysilicon Aluminum ECEN 475 4.2 1 Material Classification Insulators Glass, diamond, silicon oxide

More information

!"#$#%&#'(() ) **+,-./01)2-,-.3)456,1) /0! **)

!#$#%&#'(() ) **+,-./01)2-,-.3)456,1) /0! **) !"#$#%&#'(() ) **+,-./01)2-,-.3)456,1) /0!7.5853-09**) Etching Removal of unwanted or non-circuit copper from board Etch resists organic and metallic resists photoresist tin, gold, nickel, silver and alloys

More information

4. Thermal Oxidation. a) Equipment Atmospheric Furnace

4. Thermal Oxidation. a) Equipment Atmospheric Furnace 4. Thermal Oxidation a) Equipment Atmospheric Furnace Oxidation requires precise control of: temperature, T ambient gas, G time spent at any given T & G, t Vito Logiudice 34 4. Thermal Oxidation b) Mechanism

More information

Surface micromachining and Process flow part 1

Surface micromachining and Process flow part 1 Surface micromachining and Process flow part 1 Identify the basic steps of a generic surface micromachining process Identify the critical requirements needed to create a MEMS using surface micromachining

More information

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller Webpage: http://www.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604

More information

Major Fabrication Steps in MOS Process Flow

Major Fabrication Steps in MOS Process Flow Major Fabrication Steps in MOS Process Flow UV light Mask oxygen Silicon dioxide photoresist exposed photoresist oxide Silicon substrate Oxidation (Field oxide) Photoresist Coating Mask-Wafer Alignment

More information

Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester,

More information

Wafer (1A) Young Won Lim 4/30/13

Wafer (1A) Young Won Lim 4/30/13 Copyright (c) 2011-2013 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published

More information

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB Fabrication Process Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation 1 Fabrication- CMOS Process Starting Material Preparation 1. Produce Metallurgical Grade Silicon

More information

Dr. Priyabrat Dash Office: BM-406, Mob: Webpage: MB: 205

Dr. Priyabrat Dash   Office: BM-406, Mob: Webpage:  MB: 205 Email: dashp@nitrkl.ac.in Office: BM-406, Mob: 8895121141 Webpage: http://homepage.usask.ca/~prd822/ MB: 205 Nonmanufacturing In continuation from last class... 2 Top-Down methods Mechanical-energy methods

More information

Czochralski Crystal Growth

Czochralski Crystal Growth Czochralski Crystal Growth Crystal Pulling Crystal Ingots Shaping and Polishing 300 mm wafer 1 2 Advantage of larger diameter wafers Wafer area larger Chip area larger 3 4 Large-Diameter Wafer Handling

More information

EE 330 Lecture 9. IC Fabrication Technology Part 2

EE 330 Lecture 9. IC Fabrication Technology Part 2 EE 330 Lecture 9 IC Fabrication Technology Part 2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this

More information

Semiconductor device fabrication

Semiconductor device fabrication REVIEW Semiconductor device fabrication is the process used to create the integrated circuits (silicon chips) that are present in everyday electrical and electronic devices. It is a multiplestep sequence

More information

conductor - gate insulator source gate n substrate conductor - gate insulator gate substrate n open switch closed switch however: closed however:

conductor - gate insulator source gate n substrate conductor - gate insulator gate substrate n open switch closed switch however: closed however: MOS Transistors Readings: Chapter 1 N-type drain conductor - gate insulator source gate drain source n p n substrate P-type drain conductor - gate insulator source drain gate source p p substrate n 42

More information

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing ELEC 3908, Physical Electronics, Lecture 4 Basic Integrated Circuit Processing Lecture Outline Details of the physical structure of devices will be very important in developing models for electrical behavior

More information

Temperature Scales. Questions. Temperature Conversions 7/21/2010. EE580 Solar Cells Todd J. Kaiser. Thermally Activated Processes

Temperature Scales. Questions. Temperature Conversions 7/21/2010. EE580 Solar Cells Todd J. Kaiser. Thermally Activated Processes 7/1/010 EE80 Solar Cells Todd J. Kaiser Flow of Wafer in Fabrication Lecture 0 Microfabrication A combination of Applied Chemistry, Physics and ptics Thermal Processes Diffusion & xidation Photolithograpy

More information

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to Supporting Information: Substrate preparation and SLG growth: All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to aid in visual inspection of the graphene samples. Prior

More information

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009 Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology

More information

Supporting Information: Model Based Design of a Microfluidic. Mixer Driven by Induced Charge Electroosmosis

Supporting Information: Model Based Design of a Microfluidic. Mixer Driven by Induced Charge Electroosmosis Supporting Information: Model Based Design of a Microfluidic Mixer Driven by Induced Charge Electroosmosis Cindy K. Harnett, Yehya M. Senousy, Katherine A. Dunphy-Guzman #, Jeremy Templeton * and Michael

More information

Dow Corning WL-5150 Photodefinable Spin-On Silicone

Dow Corning WL-5150 Photodefinable Spin-On Silicone Dow Corning WL-515 Photodefinable Spin-On Silicone Properties and Processing Procedures Introduction Dow Corning WL-515 is a silicone formulation which can be photopatterned and cured using standard microelectronics

More information

Most semiconductor devices contain at least one junction between p-type and n-type material. These p-n junctions are fundamental to the performance

Most semiconductor devices contain at least one junction between p-type and n-type material. These p-n junctions are fundamental to the performance Ch. 5: p-n Junction Most semiconductor devices contain at least one junction between p-type and n-type material. These p-n junctions are fundamental to the performance of functions such as rectification,

More information

Lecture #18 Fabrication OUTLINE

Lecture #18 Fabrication OUTLINE Transistors on a Chip Lecture #18 Fabrication OUTLINE IC Fabrication Technology Introduction the task at hand Doping Oxidation Thin-film deposition Lithography Etch Lithography trends Plasma processing

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)

More information

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing 3. Conventional licon Processing Micromachining, Microfabrication. EE 5344 Introduction to MEMS CHAPTER 3 Conventional Processing Why silicon? Abundant, cheap, easy to process. licon planar Integrated

More information

Electronic Supplementary Information

Electronic Supplementary Information Electronic Supplementary Material (ESI) for Journal of Materials Chemistry C. This journal is The Royal Society of Chemistry 2015 Electronic Supplementary Information Water stability and orthogonal patterning

More information

Chapter 2 MOS Fabrication Technology

Chapter 2 MOS Fabrication Technology Chapter 2 MOS Fabrication Technology Abstract This chapter is concerned with the fabrication of metal oxide semiconductor (MOS) technology. Various processes such as wafer fabrication, oxidation, mask

More information

Fabrication of Nanoscale Silicon Membranes on SOI Wafers Using Photolithography and Selective Etching Techniques:

Fabrication of Nanoscale Silicon Membranes on SOI Wafers Using Photolithography and Selective Etching Techniques: Fabrication of Nanoscale Silicon Membranes on SOI Wafers Using Photolithography and Selective Etching Techniques: Participant Names: Moriah Faint, Marcos Rodriguez Mentor: Frank Tsang Date: 1 Introduction

More information

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers Aaron Pederson EE 432 Lab Dr. Meng Lu netid: abp250 Lab instructor: Yunfei Zhao Report 1 A. Overview The goal of this lab is to go through the semiconductor fabrication process from start to finish. This

More information

IC/MEMS Fabrication - Outline. Fabrication

IC/MEMS Fabrication - Outline. Fabrication IC/MEMS Fabrication - Outline Fabrication overview Materials Wafer fabrication The Cycle: Deposition Lithography Etching Fabrication IC Fabrication Deposition Spin Casting PVD physical vapor deposition

More information

UV15: For Fabrication of Polymer Optical Waveguides

UV15: For Fabrication of Polymer Optical Waveguides CASE STUDY UV15: For Fabrication of Polymer Optical Waveguides Master Bond Inc. 154 Hobart Street, Hackensack, NJ 07601 USA Phone +1.201.343.8983 Fax +1.201.343.2132 main@masterbond.com CASE STUDY UV15:

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 3D Perspective 2 3 Fabrication

More information

Technology process. It s very small world. Electronics and Microelectronics AE4B34EM. Why is the integration so beneficial?

Technology process. It s very small world. Electronics and Microelectronics AE4B34EM. Why is the integration so beneficial? It s very small world Electronics and Microelectronics AE4B34EM 9. lecture IC processing technology Wafer fabrication Lithography How to get 1 000 000 000 Components to 1 cm 2 Human hair on the surface

More information

MCC. PMGI Resists NANO PMGI RESISTS OFFER RANGE OF PRODUCTS

MCC. PMGI Resists NANO PMGI RESISTS OFFER RANGE OF PRODUCTS MCC PMGI RESISTS OFFER Sub.25µm lift-off processing Film thicknesses from 5µm Choice of resin blends for optimal undercut control High thermal stability Superior adhesion to Si, NiFe, GaAs, InP

More information

Lab #2 Wafer Cleaning (RCA cleaning)

Lab #2 Wafer Cleaning (RCA cleaning) Lab #2 Wafer Cleaning (RCA cleaning) RCA Cleaning System Used: Wet Bench 1, Bay1, Nanofabrication Center Chemicals Used: H 2 O : NH 4 OH : H 2 O 2 (5 : 1 : 1) H 2 O : HF (10 : 1) H 2 O : HCl : H 2 O 2

More information

EELE408 Photovoltaics Lecture 02: Silicon Processing

EELE408 Photovoltaics Lecture 02: Silicon Processing EELE408 Photovoltaics Lecture 0: licon Processing Dr. Todd J. Kaiser tjkaiser@ece.montana.edu Department of Electrical and Computer Engineering Montana State University - Bozeman The Fabrication Process

More information

Review of CMOS Processing Technology

Review of CMOS Processing Technology - Scaling and Integration Moore s Law Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from

More information

Fabrication Technology, Part I

Fabrication Technology, Part I EEL5225: Principles of MEMS Transducers (Fall 2003) Fabrication Technology, Part I Agenda: Oxidation, layer deposition (last lecture) Lithography Pattern Transfer (etching) Impurity Doping Reading: Senturia,

More information

Micro & nanofabrica,on

Micro & nanofabrica,on Micro & nanofabrica,on Photolitography : - contact - projec,on Electron Beam lithography (EBL) Nano imprint lithography Etching Contact Photolithography Substrate (e.g. Silicon wafer) Photoresist spinning

More information

Physical Vapor Deposition (PVD) Zheng Yang

Physical Vapor Deposition (PVD) Zheng Yang Physical Vapor Deposition (PVD) Zheng Yang ERF 3017, email: yangzhen@uic.edu Page 1 Major Fabrication Steps in MOS Process Flow UV light Mask oxygen Silicon dioxide photoresist exposed photoresist oxide

More information

Solid State Sensors. Microfabrication 8/22/08 and 8/25/08

Solid State Sensors. Microfabrication 8/22/08 and 8/25/08 Solid State Sensors Microfabrication 8/22/08 and 8/25/08 Purpose of This Material To introduce the student to microfabrication techniques as used to fabricate MEMS Sensors Understand concepts not specifics

More information

Basic&Laboratory& Materials&Science&and&Engineering& Micro&Electromechanical&Systems&& (MEMS)&

Basic&Laboratory& Materials&Science&and&Engineering& Micro&Electromechanical&Systems&& (MEMS)& Basic&Laboratory& Materials&Science&and&Engineering& Micro&Electromechanical&Systems&& (MEMS)& M105& As of: 27.10.2011 1 Introduction... 2 2 Materials used in MEMS fabrication... 2 3 MEMS fabrication processes...

More information

Introduction to Nanofabrication: Top Down to Bottom Up

Introduction to Nanofabrication: Top Down to Bottom Up Welcome to NACK s Webinar Introduction to Nanofabrication: Top Down to Bottom Up NACK is an NSF-funded ATE Resource Center supporting faculty in Nanotechnology Education Hosted by MATEC Networks www.matecnetworks.org

More information

Metallization deposition and etching. Material mainly taken from Campbell, UCCS

Metallization deposition and etching. Material mainly taken from Campbell, UCCS Metallization deposition and etching Material mainly taken from Campbell, UCCS Application Metallization is back-end processing Metals used are aluminum and copper Mainly involves deposition and etching,

More information

Technology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS

Technology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS INTRODUCTION TO Semiconductor Manufacturing Technology SECOND EDITION Hong Xiao TECHNISCHE INFORMATIONSBiBUOTHEK UNIVERSITATSBIBLIOTHEK HANNOVER SPIE PRESS Bellingham,Washington USA Contents Preface to

More information

Lecture 5: Micromachining

Lecture 5: Micromachining MEMS: Fabrication Lecture 5: Micromachining Prasanna S. Gandhi Assistant Professor, Department of Mechanical Engineering, Indian Institute of Technology, Bombay, Recap: Last Class E-beam lithography X-ray

More information

Chapter 3 CMOS processing technology

Chapter 3 CMOS processing technology Chapter 3 CMOS processing technology (How to make a CMOS?) Si + impurity acceptors(p-type) donors (n-type) p-type + n-type => pn junction (I-V) 3.1.1 (Wafer) Wafer = A disk of silicon (0.25 mm - 1 mm thick),

More information

Semiconductor Manufacturing Technology. IC Fabrication Process Overview

Semiconductor Manufacturing Technology. IC Fabrication Process Overview Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4 Objectives After studying the material in this chapter, you

More information

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS Contents: VI Sem ECE 06EC63: Analog and Mixed Mode VLSI Design PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS 1. Introduction 2. CMOS Fabrication 3. Simplified View of Fabrication Process 3.1 Alternative

More information

Processing guidelines. Negative Tone Photoresists mr-ebl 6000

Processing guidelines. Negative Tone Photoresists mr-ebl 6000 Characteristics Processing guidelines Negative Tone Photoresists mr-ebl 6000 mr-ebl 6000 is a chemically amplified negative tone photoresist for the use in micro- and nanoelectronics. - Electron beam sensitive

More information

Fabrication and Layout

Fabrication and Layout Fabrication and Layout Kenneth Yun UC San Diego Adapted from EE271 notes, Stanford University Overview Semiconductor properties How chips are made Design rules for layout Reading Fabrication: W&E 3.1,

More information

Photolithography. Dong-Il Dan Cho. Seoul National University Nano/Micro Systems & Controls Laboratory

Photolithography. Dong-Il Dan Cho. Seoul National University Nano/Micro Systems & Controls Laboratory Lecture 9: Photolithography School of Electrical l Engineering i and Computer Science, Seoul National University Nano/Micro Systems & Controls Laboratory Email: dicho@snu.ac.kr URL: http://nml.snu.ac.kr

More information

Lect. 2: Basics of Si Technology

Lect. 2: Basics of Si Technology Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from fractions of nanometer to several micro-meters

More information

Eco-Friendly Photolithography Using Water- Developable Pure Silk Fibroin

Eco-Friendly Photolithography Using Water- Developable Pure Silk Fibroin Electronic Supplementary Material (ESI) for RSC Advances. This journal is The Royal Society of Chemistry 2016 SUPPLEMENTARY INFORMATION Eco-Friendly Photolithography Using Water- Developable Pure Silk

More information

EE 527 MICROFABRICATION. Lecture 15 Tai-Chang Chen University of Washington EE-527 M4 MASK SET: NPN BJT. C (sub) A E = 40 µm x 40 µm

EE 527 MICROFABRICATION. Lecture 15 Tai-Chang Chen University of Washington EE-527 M4 MASK SET: NPN BJT. C (sub) A E = 40 µm x 40 µm EE 527 MICROFABRICATION Lecture 15 Tai-Chang Chen University of Washington EE-527 M4 MASK SET: NPN BJT C (sub) E B A E = 40 µm x 40 µm 1 EE-527 M4 MASK SET: MOS C-V TEST CAPACITORS W = 10 µm L = 10 µm

More information

4/10/2012. Introduction to Microfabrication. Fabrication

4/10/2012. Introduction to Microfabrication. Fabrication Introduction to Microfabrication Fabrication 1 MEMS Fabrication Flow Basic Process Flow in Micromachining Nadim Maluf, An introduction to Microelectromechanical Systems Engineering 2 Thin Film Deposition

More information

9-11 April 2008 Micro-electroforming Metallic Bipolar Electrodes for Mini-DMFC Stacks

9-11 April 2008 Micro-electroforming Metallic Bipolar Electrodes for Mini-DMFC Stacks 9-11 April 8 Micro-electroforming Metallic Bipolar Electrodes for Mini-DMFC Stacks R. F. Shyu 1, H. Yang, J.-H. Lee 1 Department of Mechanical Manufacturing Engineering, National Formosa University, Yunlin,

More information

Lecture 10: MultiUser MEMS Process (MUMPS)

Lecture 10: MultiUser MEMS Process (MUMPS) MEMS: Fabrication Lecture 10: MultiUser MEMS Process (MUMPS) Prasanna S. Gandhi Assistant Professor, Department of Mechanical Engineering, Indian Institute of Technology, Bombay, 1 Recap Various VLSI based

More information

Introduction to Micro/Nano Fabrication Techniques. Date: 2015/05/22 Dr. Yi-Chung Tung. Fabrication of Nanomaterials

Introduction to Micro/Nano Fabrication Techniques. Date: 2015/05/22 Dr. Yi-Chung Tung. Fabrication of Nanomaterials Introduction to Micro/Nano Fabrication Techniques Date: 2015/05/22 Dr. Yi-Chung Tung Fabrication of Nanomaterials Top-Down Approach Begin with bulk materials that are reduced into nanoscale materials Ex:

More information

Lecture 1A: Manufacturing& Layout

Lecture 1A: Manufacturing& Layout Introduction to CMOS VLSI Design Lecture 1A: Manufacturing& Layout David Harris Harvey Mudd College Spring 2004 Steven Levitan Fall 2008 1 The Manufacturing Process For a great tour through the IC manufacturing

More information

DuPont MX5000 Series

DuPont MX5000 Series DuPont MX5000 Series DATA SHEET & PROCESSING INFORMATION High Performance Multi-Purpose Polymer Film for MEMS Applications PRODUCT FEATURES/ APPLICATIONS Negative working, aqueous processable dry film

More information

Cu Wiring Process for TFTs - Improved Hydrogen Plasma Resistance with a New Cu Alloy -

Cu Wiring Process for TFTs - Improved Hydrogen Plasma Resistance with a New Cu Alloy - Cu Wiring Process for TFTs - Improved Hydrogen Plasma Resistance with a New Cu Alloy - Masanori Shirai*, Satoru Takazawa*, Satoru Ishibashi*, Tadashi Masuda* As flat-screen TVs become larger and their

More information

Welcome MNT Conference 1 Albuquerque, NM - May 2010

Welcome MNT Conference 1 Albuquerque, NM - May 2010 Welcome MNT Conference 1 Albuquerque, NM - May 2010 Introduction to Design Outline What is MEMs Design General Considerations Application Packaging Process Flow What s available Sandia SUMMiT Overview

More information

EE 432/532 CyMOS process PWELL Lithography & Diffusion Feb 24, 2016

EE 432/532 CyMOS process PWELL Lithography & Diffusion Feb 24, 2016 EE 432/532 CyMOS process PWELL Lithography & Diffusion Feb 24, 2016 Friday Afternoon Group Brady Koht Sebastian Roe Peter Bonnie Joseph Wickner Lab Instructor Yunfei Zhao 1. Overview Now that a Field Oxide

More information

The Hummer VI. Brian Thomas Lithography. October 29, Hummer VI THE UNIVERSITY OF TEXAS AT DALLAS ERIK JOHNSON SCHOOL OF ENGINEERING

The Hummer VI. Brian Thomas Lithography. October 29, Hummer VI THE UNIVERSITY OF TEXAS AT DALLAS ERIK JOHNSON SCHOOL OF ENGINEERING The Hummer VI Brian Thomas Lithography October 29, 2003 Hummer VI THE UNIVERSITY OF TEXAS AT DALLAS ERIK JOHNSON SCHOOL OF ENGINEERING DOCUMENT NUMBER: FA2003-LI-006 EDITION: 1.0 PAGE: 1 of 6 The Hummer

More information

PHYSICAL ELECTRONICS(ECE3540) Brook Abegaz, Tennessee Technological University, Fall 2013

PHYSICAL ELECTRONICS(ECE3540) Brook Abegaz, Tennessee Technological University, Fall 2013 PHYSICAL ELECTRONICS(ECE3540) Brook Abegaz, Tennessee Technological University, Fall 2013 1 Chapter 1 The Crystal Structure of Solids Physical Electronics: Includes aspects of the physics of electron movement

More information

Process Flow in Cross Sections

Process Flow in Cross Sections Process Flow in Cross Sections Process (simplified) 0. Clean wafer in nasty acids (HF, HNO 3, H 2 SO 4,...) --> wear gloves! 1. Grow 500 nm of SiO 2 (by putting the wafer in a furnace with O 2 2. Coat

More information

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY CHAPTER - 4 CMOS PROCESSING TECHNOLOGY Samir kamal Spring 2018 4.1 CHAPTER OBJECTIVES 1. Introduce the CMOS designer to the technology that is responsible for the semiconductor devices that might be designed

More information

CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI

CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI CMOS Technology Flow varies with process types & company N-Well CMOS Twin-Well CMOS STI Start with substrate selection Type: n or p Doping level, resistivity Orientation, 100, or 101, etc Other parameters

More information

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Development of Sidewalls Passivating Films Sidewalls get inert species deposited on them with plasma etch Creates

More information

Be careful what you wish for

Be careful what you wish for Be careful what you wish for Four Point Probe Key measurement tool in microelectronics fabrication What is Four Point Probing Four Point Probing is a method for measuring the resistivity of a substance.

More information

Via Fill in Small Trenches using Hot Aluminum Process. By Alice Wong

Via Fill in Small Trenches using Hot Aluminum Process. By Alice Wong Via Fill in Small Trenches using Hot Aluminum Process By Alice Wong Goals for Project Good Via Fill in Small contact holes using hot aluminum process Be able to get good images of the contact holes using

More information

FABRICATION of MOSFETs

FABRICATION of MOSFETs FABRICATION of MOSFETs CMOS fabrication sequence -p-type silicon substrate wafer -creation of n-well regions for pmos transistors, -impurity implantation into the substrate. -thick oxide is grown in the

More information

Nanoelectronics Fabrication Facility

Nanoelectronics Fabrication Facility Nanoelectronics Fabrication Facility Contents Introduction 2 Mask Making Module 4 Photolithography Module 6 Wet Etching and CMP Module 8 Dry Etching and Sputtering Module 10 Thermal Process and Implantation

More information

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Development of Sidewalls Passivating Films Sidewalls get inert species deposited on them with plasma etch Creates

More information

Screen Printing of Highly Loaded Silver Inks on. Plastic Substrates Using Silicon Stencils

Screen Printing of Highly Loaded Silver Inks on. Plastic Substrates Using Silicon Stencils Supporting Information Screen Printing of Highly Loaded Silver Inks on Plastic Substrates Using Silicon Stencils Woo Jin Hyun, Sooman Lim, Bok Yeop Ahn, Jennifer A. Lewis, C. Daniel Frisbie*, and Lorraine

More information

Thomas M. Adams Richard A. Layton. Introductory MEMS. Fabrication and Applications. Springer

Thomas M. Adams Richard A. Layton. Introductory MEMS. Fabrication and Applications. Springer Thomas M. Adams Richard A. Layton Introductory MEMS Fabrication and Applications Springer Contents Preface xiü Part I Fabrication Chapter 1: Introduction 3 1.1 What are MEMS? 3 1.2 Why MEMS? 4 1.2.1. Low

More information

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in Chapter 5 PROCESSING OF DEVICES A discussion of crystal growth, lithography, etching, doping, and device structures is presented in the following overview gures. SEMICONDUCTOR DEVICE PROCESSING: AN OVERVIEW

More information

Dr. Lynn Fuller, Motorola Professor Steven Sudirgo, Graduate Student

Dr. Lynn Fuller, Motorola Professor Steven Sudirgo, Graduate Student ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Bulk Micromachined Pressure Sensor Dr. Lynn Fuller, Motorola Professor Steven Sudirgo, Graduate Student 82 Lomb Memorial Drive Rochester, NY

More information

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate Development of Sidewalls Passivating Films Sidewalls get inert species deposited on them with plasma etch Creates

More information

Thermal Nanoimprinting Basics

Thermal Nanoimprinting Basics Thermal Nanoimprinting Basics Nanoimprinting is a way to replicate nanoscale features on one surface into another, like stamping copies are made by traditional fabrication techniques (optical/ebeam lith)

More information

SUPPORTING INFORMATION: Collateral Advantages of a Gel Electrolyte for. Higher Voltage; Reduced Volume

SUPPORTING INFORMATION: Collateral Advantages of a Gel Electrolyte for. Higher Voltage; Reduced Volume SUPPORTING INFORMATION: Collateral Advantages of a Gel Electrolyte for MnO 2 Nanowire Capacitors: Higher Voltage; Reduced Volume Mya Le Thai, Shaopeng Qiao, Rajen K. Dutta, Gaurav Jha, Alana Ogata, Girija

More information