Integrated Circuits & Systems

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1 Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 6 CMOS Fabrication Process & Design Rules

2 Layout for CMOS Inverter (typical 0.35 µm tech.) N-channel (or NMOS) transistor Polysilicon (poly) Active areas P-channel (or PMOS) transistor N implant (drain & source) P implant (drain & source) Slide 6.2

3 Layout for CMOS Inverter Polysilicon (poly) NMOS transistor Active areas PMOS transistor Active area & P implant (substrate contact) N implant (drain & source) P implant (drain & source) Active area & P implant (well contact) Slide 6.3

4 Layout for CMOS Inverter NMOS transistor PMOS transistor Via 1 Contact holes Polysilicon Gnd Metal 2 Vdd Gnd Metal 1 Vdd Slide 6.4

5 Layout for CMOS Inverter To study the CMOS process steps, we will disregard substrate and well contacts NMOS transistor Poly PMOS transistor N implant (drain & source) P implant (drain & source) Gnd Vdd Slide 6.5

6 Layout vs. AA Cross on Fabricated Structure NMOS transistor PMOS transistor A A Transistor gate (poly) Metal 1 Metal 2 Transistor gate (poly) Isolation oxide Field oxide N implant Gate (thin) oxide Field oxide P implant Gate (thin) oxide Field oxide N.B.: oxide = SiO 2 Slide 6.6

7 N Well Creation A thin layer ( film ) of oxide (SiO 2 ), typically with 10nm, is deposited through dry oxidation (which is slow, but allows for a good thickness control) Silicon oxide (SiO 2 ) Thickness of substrate is between 0.5 and 1.0 mm Slide 6.7

8 N Well Creation A thicker layer ( film ) of sacrificial silicon nitride (Si 3 N 4 ) is deposited through Plasma CVD (Chemical Vapor Deposition) Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.8

9 N Well Creation layer (pattern) A A UV light Photolithography using N well mask: 1. Spin deposition of photoresist (~1µm) 2. Wafer is put in oven to dry photoresist 3. Wafer surface is exposed to UV light through optical mask Optical mask with pattern (Negative) photoresist Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.9

10 N Well Creation Photolithography using N well mask: 4. Unexposed photoresist is removed by using organic solvent 5. Wafer is soft baked at low temperature to hard remaining photoresist Remaining photoresist Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.10

11 N Well Creation Nitride is selectively removed by plasma etching (photoresist serves as coat) Remaining photoresist Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.11

12 N Well Creation Nitride is selectively removed by plasma etching (photoresist serves as coat) Remaining photoresist Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.12

13 N Well Creation Remaining photoresist is removed with a mixture of acids Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.13

14 N Well Creation Ion implantation (N-type dopant) is formed by ion implantation: Nitride is used as protecting coat Ions traverse oxide film Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.14

15 N Well Creation Ion implantation (N-type dopant) is formed by ion implantation: Nitride is used as protecting coat Ions traverse oxide film Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.15

16 N Well Creation Nitride is selectively removed by plasma etching Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.16

17 N Well Creation Oxide is removed by using Hydrofluoric acid (HF) The wafer is cleaned (SDR - spin, rinse and dry with nitrogen) Slide 6.17

18 Field Oxide Growth There are two types of regions ion wafer surface: Active area (where transistors are) Field area (must isolate transistors) Slide 6.18

19 Field Oxide Growth Active area layer (pattern) A A UV light After oxide and nitride deposition (similar to N well creation step), photolithography is performed with an optical mask containing the negative of active area pattern. optical mask with negative pattern of active area Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.19

20 Field Oxide Growth Wet oxidation is used to grow a thick layer of oxide, that will serve as isolation between transistors Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.20

21 Field Oxide Growth Wet oxidation is used to grow a thick layer of oxide (with a few hundreds of nanometers), that will serve as isolation between transistors Silicon nitride (Si 3 N 4 ) Silicon oxide (SiO 2 ) Slide 6.21

22 Field Oxide Growth Field oxide Nitride is selectively removed by plasma etching Oxide is removed by using Hydrofluoric acid (HF) The wafer is cleaned (SDR - spin, rinse and dry with nitrogen) Slide 6.22

23 Field Oxide Growth Nitride is selectively removed by plasma etching Oxide is removed by using Hydrofluoric acid (HF) The wafer is cleaned (SDR - spin, rinse and dry with nitrogen) Slide 6.23

24 Gate Oxide Formation Gate oxide Wafer surface is submitted to dry oxidation to grow a thin film of oxide (~100 Angstrom), referred to as gate oxide Slide 6.24

25 Polysilicon Deposition Poly is deposited by CVD process using silane gas Slide 6.25

26 Polysilicon Deposition Poly layer (pattern) A A UV light Transistor gate pattern pattern is printed on wafer surface by using photolithography. optical mask with negative pattern of poly Slide 6.26

27 Polysilicon Deposition Poly layer (pattern) A A UV light Transistor gate pattern pattern is printed on wafer surface by using photolithography. Slide 6.27

28 Polysilicon Deposition Non-exposed poly is selectively removed by etching. The photoresist serves as coating. Slide 6.28

29 Polysilicon Deposition Non-exposed poly is selectively removed by etching Slide 6.29

30 Polysilicon Deposition Non-exposed thin oxide is selectively removed by etching Slide 6.30

31 Polysilicon Deposition Non-exposed thin oxide is selectively removed by etching Slide 6.31

32 PMOS Transistor Drain and Source Creation UV light P implant layer (pattern) A A P implant pattern is printed on wafer surface by using photolithography. Optical mask with P implant pattern Slide 6.32

33 PMOS Transistor Drain and Source Creation UV light P implant layer (pattern) A A P implant pattern is printed on wafer surface by using photolithography. Optical mask with P implant pattern Slide 6.33

34 PMOS Transistor Drain and Source Creation Ion implantation (P-type dopant) P-type dopants are implanted through ion implantation. Photoresist serves as coating Slide 6.34

35 PMOS Transistor Drain and Source Creation Ion implantation (P-type dopant) P-type dopants are implanted through ion implantation. Photoresist serves as coating Slide 6.35

36 PMOS Transistor Drain and Source Creation Remaining photoresist is removed with a mixture of acids Slide 6.36

37 PMOS Transistor Drain and Source Creation Remaining photoresist is removed with a mixture of acids Slide 6.37

38 NMOS Transistor Drain and Source Creation N implant layer (pattern) A A UV light N implant pattern is printed on wafer surface by using photolithography. Optical mask with N implant pattern Slide 6.38

39 NMOS Transistor Drain and Source Creation N implant layer (pattern) A A UV light N implant pattern is printed on wafer surface by using photolithography. Optical mask with N implant pattern Slide 6.39

40 NMOS Transistor Drain and Source Creation Ion implantation (N-type dopant) N-type dopants are implanted through ion implantation Photoresist serves as coating Slide 6.40

41 NMOS Transistor Drain and Source Creation Ion implantation (N-type dopant) N-type dopants are implanted through ion implantation Photoresist serves as coating Slide 6.41

42 NMOS Transistor Drain and Source Creation Remaining photoresist is removed with a mixture of acids Slide 6.42

43 NMOS Transistor Drain and Source Creation Remaining photoresist is removed with a mixture of acids Slide 6.43

44 Isolation Oxide Deposition A thick film of oxide is deposited through CVD Slide 6.44

45 Contact Wholes Opening Contact layer (pattern) A A UV light Contact holes are printed on wafer surface by using photolithography. Optical mask with contacts pattern Slide 6.45

46 Contact Wholes Opening Contact layer (pattern) A A UV light Contact holes are printed on wafer surface by using photolithography. Optical mask with contacts pattern Slide 6.46

47 Contact Wholes Opening Contact holes are dug on isolation oxide through etching Slide 6.47

48 Contact Wholes Opening Contact holes are dug on isolation oxide through etching Slide 6.48

49 Contact Wholes Opening Remaining photoresist is removed Slide 6.49

50 Contact Wholes Opening Slide 6.50

51 Metal 1 Deposition Metal 1 is deposited through sputtering Slide 6.51

52 Metal 1 Deposition Metal 1 layer (pattern) Undesired metal 1 is removed, leaving only desired connections UV light A A Optical mask with metal 1 pattern Slide 6.52

53 Metal 1 Deposition Metal 1 layer (pattern) Undesired metal 1 is removed, leaving only desired connections A UV light A Optical mask with metal 1 pattern Slide 6.53

54 Metal 1 Deposition Undesired metal 1 is removed through etching Slide 6.54

55 Metal 1 Deposition Undesired metal 1 is removed through etching Slide 6.55

56 Metal 1 Deposition Photoresist is removed Slide 6.56

57 Isolation Oxide Deposition Another thick film of oxide is deposited through CVD to isolate metal 1 from metal 2 Slide 6.57

58 Metal 2 Deposition Similarly to metal 1 deposition Slide 6.58

59 Layout vs. AA Cross on Fabricated Structure NMOS transistor PMOS transistor A A Slide 6.59

60 Metal Layers in a Contemporary Technology Conexões em cobre 0,11µm IBM Fonte: Rabaey; Chandrakasan; Nikolic, 2003 Slide 6.60

61 Dual-Well Trench-Isolated CMOS Process (Current) Source: Rabaey; Chandrakasan; Nikolic, 2003 Epitaxial layer: Single-crystal film grown on silicon surface with controlled impurities, that can have fewer defects than native wafer surface. Slide 6.61

62 Final Result Slide 6.62

63 CMOS Process Layers Layer Color N Well Gray Active Area Green N+ implant (N+ select) Yellow P+ implant (P+ select) Orange Polysilicon Red Metal 1 Medium blue Metal 2 Light blue Contact to drain/source Black Contract to polysilicon Black Via Light Gray Colors may vary according to Foundry/technology/layout editor Slide 6.63

64 L 1: mínima extensão da porta (poli) fora da área ativa 2: mínima extensão do implante fora da área ativa L 2 1 W 4 3 W 3: mínima distância entre implante N e implante P 4: mínima distância entre implante N (área ativa) e poço N Slide Fonte: Fernanda Kastensmidt, EMicro2005

65 : mínima largura de metal 1 2: mínima distância entre metal 1 3: mínima largura de metal 2 4: mínima distância entre metal 2 5: mínima largura do contado 6: mínima extensão de metal 1 para fora do contato 7: mínima distância entre contatos 8: mínima largura de via 9: mínima extensão de metal 2 para fora da via 10: mínima extensão de metal 1 para fora da via 7 Fonte: Fernanda Kastensmidt, EMicro2005 Slide 6.65

66 Conectando Transistores em Série A B A B Slide 6.66

67 Conectando Transistores em Série A B A B Slide 6.67

68 Conectando Transistores em Série X A B Y A B X Y X=Y se A=1 E B=1 Slide 6.68

69 Conectando Transistores em Paralelo X A B A B Y Slide 6.69

70 Conectando Transistores em Paralelo X Problema: capacitância da difusão é muito grande! X A B Y A B Y Slide 6.70

71 Conectando Transistores em Paralelo Solução: usar metal para conexões, sempre que possível! X X A B Y A B X=Y se A=1 OU B=1 Y Slide 6.71

72 Dois Transistores em Série em Tecnol. 350nm Two transistors in series with wider chanels (asuming typical 0.35 µm CMOS Design Rules) L min = 0.35µm L min = 0.35µm 0,4µm b 0,4µm 0,4µm b 0,4µm 0,4µm b 0,4µm 0,45µm a 0,4µm 0,45µm a 0,4µm b a=0,3µm (minimum diffusion contact to gate spacing) b=0,15µm (minimum diffusion enclosure to contact) minimum contact spacing =0,4µm Slide 6.72

73 A Typical 350nm CMOS Inverter Vdd 0,4µm in out PMOS: W=W min =0.35µm L=1.5 µm b 0,4µm 0,4µm 0,4µm b in out a=0,3µm (minimum diffusion contact to gate spacing) NMOS: W=W min =0.35µm L=0.7 µm 0,4µm b b b=0,15µm (minimum diffusion enclosure to contact) Slide 6.73 Gnd

74 Another Inverter Layout Polysilicon to connect PMOS to NMOS gate V DD in out in out Metal 1 to connect PMOS and NMOS drains A given layout for a logic gate is referred to as cell GND Slide 6.74

75 2-Input NAND Cell Vdd V DD A B A B S A B S GND Slide 6.75

76 2-Input NOR Cell Vdd V DD B S A S A B A B GND Slide 6.76

77 Standard Cells Circuit layout is assembled by using pre-designed cell layouts made available in a library ( cell library ) inversor nor2 nand2... V DD V DD V DD S in A B A B Out S GND GND GND Slide 6.77

78 Standard Cell-Based Circuit Structure Cells laid out in strips cells GND roteamento sobre os transistores, em M2, M3,... VCC Slide 6.78

79 Standard Cell-Based Circuit Structure Slide 6.79

80 CMOS Fabrication References Process & Design Rules 1. RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2 nd Edition. Prentice Hall, ISBN: JAEGER, Richard C. Introduction to Microelectronic Fabrication 2 nd Edition. (Modular Series on Solid State Devices, Vol V), Prentice Hall, REIS, Ricardo.(Organizador.) Concepção de Circuitos Integrados. Porto Alegre: Sagra- Luzzatto/UFRGS, a edição. Cap. 3. ISBN Slide 6.80

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