Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages

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1 Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages by Ming-Che Hsieh STATS ChipPAC Taiwan Co. Ltd. Copyright Reprinted from 2013 International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) Proceedings. The material is posted here by permission of the IMPACT. Such permission of the IMPACT does not in any way imply IMPACT endorsement of any STATS ChipPAC Ltd s products or services. Internal or personal use of this material is permitted, however, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution must be obtained from IMPACT. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

2 Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages Ming Che Hsieh STATS ChipPAC Taiwan Co. Ltd. No , 6 Ling, Hualung Chun, Chiung Lin, Hsinchu 307, Taiwan mc.hsieh@statschippac.com ABSTRACT The three dimensional finite element analysis (FEA) was adopted to study the stress responses for the general design of a wafer level chip scale package (WLCSP) with one under bump metallurgy (UBM) layer, one redistribution layer (RDL) and two polymer layers (called 2P2M WLCSP which includes two polymer layers and two metal layers on a passivated wafer), the low cost designs of 2P1M WLCSP (with one RDL and two polymer layers) and 1P1M WLCSP (with one RDL and one polymer layer) in this study. To validate the FEA result, the board level thermal cycling reliability test of 2P2M WLCSP that followed the JEDEC standard was evaluated and both results were well aligned. Through validation and characterization, the finite element model can be further utilized to achieve precise simulations in systematic simulation studies. For the sake of capturing the top significant factors and their corresponding impact levels to the low k layer, UBM, RDL pad, top and bottom IMC stresses in 2P2M WLCSP designs, the parameters of die, low k, polymer, RDL, solder ball and PCB were discussed. By observing the presented results, not only can the significant factors that impact the stress responses be investigated but also the suitable parameters that have the best stress reduction designs in 2P2M WLCSP can be determined. This study can effectively serve as design guidelines and provide a good point of reference for significant factor selection analyses and high reliability designs of 2P2M INTRODUCTION For the highly insatiable demands of smaller form factor, multifunctional and lower cost requirements for handheld and portable electronic devices in the semiconductor industry, WLCSP technology has been widely utilized and become a mainstream product. Although WLCSP technology can provide a strong solution for miniaturization and performance, the insatiable market demands have been pushing WLCSP designs aggressively towards large die sizes (larger than 6x6mm 2 ), smaller pitches (less than 300µm) and lower prices. Based on these requirements, the challenges of finer pitches, higher input/output (I/O) pin counts, solder joint reliability and material costs have become important reasons to pursue high performance, low cost WLCSP solutions [1 5]. The typical WLCSP structure in the semiconductor industry today utilizes four mask processes on the passivated wafer (2P2M WLCSP). The 2P2M WLCSP design includes one UBM layer, one RDL and two polymer layers. The first polymer layer (PBO1) is coated on the passivated wafer and then an opening is etched for electroplating RDL on the top surface of the PBO1 layer and connected to the Aluminum (Al) pad. The second polymer layer (PBO2) is coated and covered the RDL on the top surface of PBO1 layer after the RDL plating. Then, an opening was etched in the PBO2 layer followed by UBM electroplating on the RDL pad to form the interconnections. The difference with the 2P2M WLCSP is the low cost design of 2P1M WLCSP uses three mask processes (eliminating the process of UBM electroplating) while 1P1M WLCSP only uses two mask processes (eliminating UBM formation and one polymer layer coating). Although the use of UBM on the solder balls can enhance the package reliability [6 7], the failure mode of intermetallic compound (IMC) crack on UBM and/or printed circuit board (PCB) copper (Cu) pad was observed in the 2P2M WLCSP structure during the board level reliability test [1, 3, 8], which indicated that the solder crack problem is still a concern even though the UBM structure was adopted. In addition, since the low cost designs of 2P1M and 1P1M WLCSP do not include the UBM structure, higher risks in reliability are the result as compared to 2P2M WLCSP which is necessary to solve [9]. For the purpose of studying mechanical behaviors of these WLCSPs, the three dimensional FEA was employed to study the stress comparison for 2P2M, 2P1M and 1P1M WLCSP designs. Moreover, the board level thermal cycling reliability test (TCT) for 2P2M WLCSP that followed JEDEC standard JESD22 A104C condition G with a temperature range of 40 C to 125 C was utilized to validate the simulation results. When comparing both results, it was found that the estimated crack propagation directions obtained by FEA are almost similar to those in the TCT result. Through the comparison and validation, the presented finite element model was found to be reliable when parametric simulations on packaging geometry and materials were studied. To obtain the top significant factors and the impact levels to the low k layer, RDL pad, top IMC and bottom IMC stresses in the 2P2M WLCSP design, a number of the parameters including die, low k, polymer, RDL, solder ball and PCB were selected in the systematic simulation study. (The systematic studies for low cost 2P1M and 1P1M WLCSP designs are illustrated in [9]). It is believed that this result can provide the useful optimization of designs for thermo mechanical stress solutions and high reliability requirements in WLCSPs. SIMULATIONS AND EXPERIMENTAL VALIDATIONS The WLCSP with 5.3x5.8mm 2 die on a JEDEC standard PCB was evaluated as the test vehicle for this paper. The die was 330 m and the PCB was 1.6mm. A 5 m low k layer and 0.5 m passivation layer was utilized on the die side. Non solder mask defined (NSMD) interconnects that have a larger contact area with the Cu pad on PCB were used. The solder resist opening (SRO) of 300 m and of 30 m was used on the top surface of the PCB. The diameter of the Cu pad on PCB was 220 m and was 25 m. The SAC405 lead free solder ball with 250 m ball diameter and 400 m ball pitch was utilized to form the interconnects between die and PCB. For 2P2M WLCSP, both 443

3 7.5 m thick polymer layers (PBO1 and PBO2) and a corresponding PBO2 opening size of 200 m was designed. The of RDL was 4 m and the RDL pad diameter was 250 m. The UBM size was designed to be with a diameter of 240 m and a of 8.6 m. For cost reduced 2P1M and 1P1M WLCSP, both structures are with a PBO2 layer of 10 m and with a corresponding PBO2 opening size of 240 m. The RDL was 8. m and RDL pad diameter was 257 m. A 7.5 m thick PBO1 layer was employed in 2P1M WLCSP but not used in the 1P1M The schematics and cross sectional photos of these WLCSP structures are shown in Figure 1. In order to realize the stress responses of WLCSP, the three dimensional FEA was adopted. A quarter model with pure hexahedral element meshes has been constructed in FEA due to the symmetry feature. Dense meshes were used to have precise stress solution in the outermost solder balls since the maximum stress is typically located on this critical place (IMC layer) which drives solder crack in The finite element models and the applied boundary conditions for a 2P2M, 2P1M and 1P1M WLCSP are shown in Figure 2 (with PCB size of 10x10mm 2 ). A thermal cycle loading condition from 40 C to 125 C was applied in FEA. The material properties of WLCSP are listed in Table 1. In Table 1,,ν, CTE and Tg are, respectively, Young s modulus, Poisson s ratio, coefficient of thermal expansion and glass transition temperature. 125 C 125 C RDL (Cu) PCB (FR 4) IMC (Cu 3Sn) Passivation (SiN/USG) UBM (Cu) Figure 3 illustrates the stress contour and vector plot in 2P2M WLCSP, which indicates that a larger principal stress was concentrated on the corner of UBM and RDL pad interface as well as at the edge of the top IMC layer that was adjacent to UBM layer. Thus, the failure may initiate at the interface of UBM and RDL pad to cause delamination or at the edge of the top IMC layer to induce solder crack in the 2P2M WLCSP structure. Compared with the reliability result (followed by JESD22 A104C condition G) that is shown in Figure 4, it was observed that the solder crack initially occurred mostly near the corner of the UBM and solder ball, and some cracks existed at the solder ball that was adjacent to PCB Cu pad. These cracks may propagate along the IMC layer to cause failures. In addition, the delamination between RDL pad and UBM was also observed in 2P2M WLCSP, which illustrates the well alignment with the simulation results. Hence, by utilizing present models, the stress comparison of low k, RDL pad, top and bottom IMC layer in three different WLCSPs is illustrated in Figure 5.A much higher low k stress was observed in the 1P1M WLCSP as compared to 2P1M and 2P2M WLCSP (the stress responses in 2P1M WLCSP are normalized as 1), which may come from the fact that the RDL pad in 1P1M WLCSP is electroplated directly on the passivation layer without any polymer layer to release the excess stress. Hence, a larger stress in the passivation and low k layer may result as well. Furthermore, it was also found that the stress in the top IMC layer in 1P1M WLCSP was larger than that in 2P1M and 2P2M WLCSP and indicates that there was about a 15% increase of top IMC stress in 1P1M WLCSP and a 35% reduction of top IMC stress in 2P2M WLCSP as compared to 2P1M WLCSP [9]. Figure 1. The schematics and cross sectional images of solder ball structures in (a) 1P1M WLCSP; (b) 2P1M WLCSP; (c) 2P2M (a) Figure 2. Finite element models and applied boundary conditions of various WLCSPs. Table 1. Material properties in Material E (GPa) ν CTE (ppm/ C) Die Low k PBO1/PBO Cu pad Solder resist (SR) /153 (Tg=105 C) Solder (SAC405) [10] 65 C 25 C C 75 C C 25 C C 75 C (b) Figure 3. Stress contour and vector plot for 2P2M WLCSP (a) delamination between RDL pad and UBM; (b) crack propagation along the IMC layer. SYSTEMATIC SIMULATIONS FOR 2P2M WLCSP The systematic simulations for typical a 2P2M WLCSP were examined to study the significant effects of geometry and material properties that comprehend the stress responses in the low k layer, UBM, RDL pad, top IMC and bottom IMC layer through FEA (systematic simulation results for low cost 2P1M and 1P1M WLCSP are illustrated in [9]). The utilized material properties are shown in 444

4 Table 1 and the selected parameters and ranges are listed in Table 2. The loading condition was set to be from 125 C to 40 C. Figure 6 shows the impact levels of significant factors to top IMC stress in 2P2M WLCSP (the list only includes major factors that are larger than 10%). It was observed that the UBM size and PBO2 are the critical factors to top IMC stress. The enlargement of UBM size or incremental PBO2 can efficiently reduce the top IMC stress. There is more than 20% stress reduction in the top IMC layer when the UBM size increases by 20 m (from 220 m to 260 m) or PBO2 increases by 2.5 m (from 5 m to 10 m). In addition, decreasing PCB, RDL pad size or solder ball diameter is also helpful to reduce the top IMC stress. For smaller bottom IMC stress control, a more than 15% stress reduction occurred in the bottom IMC layer when the PCB decreased by 400 m (from 1600 m to 800 m). Furthermore, there is a 5% 10% stress reduction in the bottom IMC layer if there is an increase in the bottom IMC, solder ball diameter or a decrease in solder ball pitch, which is illustrated in Figure 7. Figure 6. Impact levels of significant factors to top IMC stress in 2P2M Figure 4. Board level thermal cycling reliability test result of 2P2M Stress responses in 2P1M WLCSP are normalized as 1. Figure 5. Stress comparison of various WLCSPs. Table 2. Selected parameters list in parametric simulations. Size 4x4 8x8 (mm 2 RDL pad ) 4 6 ( m) Thickness ( m) PBO2 opening ( m) UBM size ( m) PBO ( m) UBM 4 12 ( m) PBO ( m) RDL pad size ( m) Passivation ( m) Modulus 5 20 (GPa) Thickness 3 7 ( m) CTE 5 25 (ppm/ C) Height ( m) Top IMC 1 5 ( m) Bottom IMC Diameter ( m) 1 5 ( m) Pitch ( m) Thickness ( m) SRO size ( m) Cu pad diameter ( m) SR ( m) Cu pad ( m) Figure 7. Impact levels of significant factors to bottom IMC stress in 2P2M Figure 8 illustrates the impact levels of significant factors to RDL pad stress, which indicates that the UBM size, RDL pad size and has obvious contributions. More than a 20% stress reduction occurs when UBM size increases by 20 m and more than a 15% stress reduction results when the RDL pad size increases by 30 m or the RDL increases by 1 m. The impact levels of significant factors to UBM stress are similar as compared to RDL pad stress except for the UBM which is significant to UBM stress. There is a 15% stress reduction if UBM increases from 4 m to 12 m by 4 m (only 3% stress reduction in RDL pad underneath the same condition). Figure 9 shows the impact levels of significant factors to low k stress. It is observed that the effect of PCB and PBO1 is critical to the low k stress and almost 10% 20% of low k stress decreases when the PCB decreases by 400 m or PBO1 increases by 2.5 m. Hence, to efficiently reduce the stress in the low k layer and avoid the risk of low k damage, the utilization of a thinner PCB or higher PBO1 layer may be helpful. Moreover, enlarging the RDL pad size or reducing the solder pitch and die is useful in reducing low k stress. There is about a 10% stress reduction in low k layer when the UBM size increases by 20 m (from 220 m to 260 m) or the solder pitch decreases by 50 m (from 400 m to 300 m) or the die decreases from 300 m to 150 m. Through the systematic simulations, several special cases are addressed. From Figure 6 9, it is clear that the die size is the significant factor to influence the stress responses. If the die size equals to 5.3x5.8mm 2 (PCB size is 10x10mm 2 ), larger stresses occur in the low k layer, UBM, RDL pad, top and bottom IMC layer than 445

5 other die sizes discussed (a similar trend in low cost 2P1M and 1P1M WLCSP was shown in [9]). The stresses in the low k layer, UBM, RDL pad, top and bottom IMC layer decreases as the die size expands up to 10x10mm 2 or shrinks down to 2x2mm 2. There is a more than 30% stress reduction when the die size is 10x10mm 2 or 2x2mm 2, while almost a 10% stress reduction when the die size is 4x4mm 2 or 8x8mm 2 as compared to the die size of 5.3x5.8mm 2 [9]. Another special case is the utilization of the same of RDL pad and PBO2 layer. A much higher stress was observed in the top IMC and UBM layer when the RDL pad equals the PBO2 (see Figure 10). The reason may come from the fact that there is no buffer layer around the UBM layer to release the corresponding stress and hence causes a larger stress in the top IMC layer. The stress in the low k layer is also enhanced, but the effect is insignificant. The effect of the PBO2 opening is illustrated in Figure 11. As the PBO2 opening increases, the stress in the low k layer increases but stress in the UBM, RDL pad and top IMC layer decreases, except when the PBO2 opening size is over 220 m. A rapid increment for the stress in UBM, RDL pad and top IMC layer is observed when the PBO2 opening size is 230 m (UBM size is 240 m), which indicates that the overlap of UBM and PBO2 opening size is recommended to be more than 20 m to avoid the risk of UBM delamination and solder crack. characterize the corresponding simulation results. With the alignment of TCT and simulation results, the reliable finite element model was utilized to obtain the most critical factors and correspondingly impact levels to low k, UBM, RDL pad, top and bottom IMC stress responses in this systematic simulation study. Moreover, the stress comparison of 2P2M WLCSP and low cost 2P1M and 1P1M WLCSP was also illustrated. The presented results would be useful if stress reduction in designs and package reliability enhancements in WLCSP are demanded. Figure 10. Stress comparison for the effect of RDL pad and PBO2. Stress responses in PBO2 opening size of 200 m are normalized as 1. Figure 11. Stress comparison for the effect of PBO2 opening size. ACKNOWLEDGEMENTS Figure 8. Impact levels of significant factors to RDL pad stress in 2P2M Figure 9. Impact levels of significant factors to low k stress in 2P2M CONCLUSIONS A comprehensive study for stress analysis of WLCSP by FEA modeling has been presented in this paper. The board level reliability TCT result for typical 2P2M WLCSP was evaluated to validate and The author would like to thank Chi Yuan Chen, Yun Yu Hsu and Su Lan Tzeng at STATS ChipPAC Taiwan for the support of test vehicles' TCT arrangement and SEM cross section. The suggestions from Lisa Lavin at STATS ChipPAC are also appreciated. REFERENCES [1] R. Chilukuri, "Technology solutions for a dynamic and diverse WLCSP market," International Wafer Level Packaging Conference, [2] Y. L. Tzeng, et al.," WLCSP Parameter Study for Ball Reliability Analysis," VLSI Packaging Workshop of Japan, pp , [3] R. Anderson, et al., "Integrated testing, modeling and failure analysis of CSP nl for enhanced board level reliability," International Wafer Level Packaging Conference, pp , [4] M. S. K. Rahim, et al., "Board Level Temperature Cycling Study of Large Array Wafer Level Package," Electronic Components and Technology Conference, pp , [5] Y. Liu, et al., "Modeling for critical design and performance of wafer level chip scale package," Electronic Components and Technology Conference, pp , [6] M. C. Hsieh, C. C. Lee and L. C. Hung, "Comprehensive thermo mechanical stress analyses and validation for various Cu column bumps in fcfbga,", Vol. 3, no. 1, pp , [7] M. C. Hsieh, C. C. Lee and L. C. Hung, "Comprehensive thermo mechanical stress analyses and underfill selection of large die fcbga,", Vol. 3, no. 7, pp , [8] J. H. Lau and S. W. R. Lee, "Effects of build up printed circuit board on the solder joint reliability of a wafer level chip scale package (WLCSP),", Vol. 25, no. 1 pp. 3 14, [9] M. C. Hsieh, "Finite element analyses for critical designs of low cost wafer level chip scale packages," submitted for publication, 2013 [10] S. Wiese, S. Rzepka and E. Meusel, "Time dependent plastic behavior of solders and its effect on FEM simulations for electronic packages," pp ,

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