EE432/532 CYMOS PROCESS PWELL LITHOGRAPHY AND DIFFUSION

Size: px
Start display at page:

Download "EE432/532 CYMOS PROCESS PWELL LITHOGRAPHY AND DIFFUSION"

Transcription

1 EE432/532 CYMOS PROCESS PWELL LITHOGRAPHY AND DIFFUSION [Document subtitle] GROUP 4 GROUP 4 (TUESDAY AFTERNOON) GROUP LEADER: ANDREW MCNEIL GROUP MEMBERS: WENG HOONG LOO MARIO PEREZ ZHIHAO LIAO LAB INSTRUCTOR MATTHEW WEINSTEIN JANUARY

2 1 Overview From the last lab of oxidation as shown in Figure 1, we carried on the process to build our CyMOS. In this week s lab, we were introduced to the lithography as shown in Figure 2 and Boron Deposition Process as shown in Figure 3 for the PWELL process. These are two important procedures that were required for a successful development of devices on a silicon wafer. Throughout these two processes we followed the CyMOS process traveler closely. After our procedures, Dr. Tuttle helped us with the LTO (Low Temperature Oxidation), PWELL boron drive and re-oxidation that results in Figure 4. The process traveler, the Standard Operating Procedures and Dr. Tuttle lead to the successful development of the P-Well. The procedures are explained in detail below in this report along with figures and calculations of our process. Figure 1: Oxidation from the lab before (taken from Figure 2: Lithography for PWELL (taken from

3 2 Figure 3: Boron deposition PWELL (taken from Figure 4: Boron Drive and re-oxidation for PWELL (taken from Photolithography This process begins with a thin layer of photoresist added to the wafer using a spinner. We first apply a layer of hexamethyldisilazane (HMDS), this is to secure the photoresist onto the wafers. The HMDS was applied to the wafer using a dropper. HDMS was placed on the center of the wafer where it was spread evenly through centrifugal force once the wafer begun to spin Next, the photoresist was applied to the wafer in the same fashion in the center of the wafer. This step also sets a layer of photoresist uniformly across the wafer. The wafers were then placed in the prebake phase and we began to set the mask aligner up for photolithography. Once the prebake was completed, each wafer was then placed in the Mask Aligner as shown in Figure 5, aligned and placed in contact with the mask. When we were satisfied with the alignment, the wafers and mask were exposed to UV light. The photoresist exposed in the open regions in the mask were diminished by the UV light, allowing us to remove it using a developer. The wafers were transferred to the lab s wet bench a chemical bath and rinse as shown in Figure 6, to remove the unwanted layer excess. We then dried the wafers and prepped them for a post bake at 120 C. The next step is to etch away the exposed layer of silicon dioxide. We took our wafers to the wet bench and started the buffered oxide etch (BOE), deglazing step. When the BOE bath and rinse

4 3 were completed, the wafers went to the acetone and methanol tub to remove any extra photoresist. After this chemical cleaning and rinse the wafers underwent a spin dry cycle. The wafers were then dried and placed under a microscope to verify our etching. At the end of this step, our wafers should look like Figure 1. Figure 5: The Mask Aligner used to perform etch the photoresist with UV to create the pattern needed for the next step (Diffusion). Figure 6: The wafers that have went through the developer, sitting in the cascade rinse tub while other wafers photoresists were being etched.

5 4 Boron Deposition and Drive Once the photolithography was completed and our wafers were etched, we then started the boron deposition process. In this process, boron atoms are deposited onto the wafers. This step is where we dope our wafers in order to create the PWELL. We began the process by calculating the temperature and time needed to dose our wafers as shown as Figure 8. In this deposition step of the process, we simply saturate the surface of the wafer with boron. In a separate step. we drive the dose deep into the wafers. We began this step with the standard clean process, this removes previous chemicals and excess dust or particles that may have collected on the surface of the wafers during previous processes. It is important to remove these impurities, because at high-temperatures these impurities may fuse into the surface of the silicon wafers. This can have adverse and detrimental effects on our wafers. The Standard Clean Process washes the wafers with ammonium hydroxide, hydrochloric acid, hydrofluoric acid, and deionized water. Each chemical has its own bath cycle and is followed by a rinse in the de-ionized water. After the chemical baths, have been applied, a final wash is done in the spin rinse and dryer. The deposition process consisted of 5 separate steps as shown in Figure 7. We began by pushing our wafers in the quartz boat at a rate of 1 inch every 12 seconds. This was to be a 5 minute process of pushing the boat all the way into the furnace. Our beginning settings were a temperature of 850⁰C. The nitrogen level being pumped into the furnace was to be at 2 slpm (standard liter per minute). The second step of this process was recovery. This was a set time and temperature of 20 mins at 850⁰C respectively. This was a process of allowing oxygen to begin flowing into the furnace. The recovery process of having mixed nitrogen and oxygen flow is needed before introducing hydrogen. Source was the third step in the deposition process. This was introducing nitrogen into the furnace. This was the shortest individual process in the deposition steps. 40 sccm (standard cubic centimeter per minute) of hydrogen began flowing for a 2 min process. The next process was the soak time. In this step, we were given the ambient gas values that were to be flowing into the furnace, which was 2 slpm of nitrogen. In this step, we needed to choose our own time and temperature depending on the values that were given to us. The dose time in this step, Q, needed to be between 7.5E13 cm -2 and 10E14 cm -2. We chose a dose value of 10E13 cm -2.

6 5 Figure 7: The simplified version of the Boron Deposition (taken from the process traveler) From the calculations attached in appendix Figure 12, by setting the temperature to 850⁰C to get the time. Thus, by solving, the deposition time was 76 mins and 20 seconds approximately based on our calculations. The final step in the process was pulling out. This was done at 1 inch every 12 seconds. The gases that were flowing during this process was just 2 slpm of nitrogen. The temperature was to continue being at 850⁰C. The reason we chose our soak temp to be 850⁰C was to keep the temperature constant throughout the entire deposition process. Once the process was complete and the wafers were removed and cooled, a deglaze process was done. This was a simple 3 step process of a BOE dip of 30 seconds, and a 3 minute cascade rinse followed. The last step was just a spin rinse/dry. After the boron deposition comes the process for the drive. We begin with the standard clean to clear the silicon wafers surface of impurities. If not cleaned, these impurities could diffuse into the silicon while in the furnace ruin our progress. The standard cleaning procedure is described earlier in the process. The wafers go into the furnace which is set to 800 C with a flow of N2 for the Low-Temperature-Oxide step (LTO). The LTO is a necessary step to remove the boronlayer that was created during the boron deposition. The growth of a thin oxide allows us to remove this layer and with it any potential impurities that have developed on top of the surface. A deglazing step is performed to remove the thin LTO oxide layer. Once completed, the wafers go back into the furnace overnight for a drive at high temperature. This step was completed by the professor due to the amount of time required.

7 6 Results Looking back through the Photolithography and Boron Deposition processes, it went pretty smoothly except for one of the wafers breaking in half as explained in the problem section later on. After the lithography step was done, we took a look at the wafers under the microscope as shown in Figure 8. From the inspection, we found that the wafers were aligned correctly. This is because there were no bubbles appearing on the wafers surfaces, the markings on the wafers were clear. The patterns on the wafers were same as the pattern on the mask and the coordinates obtained through the microscope matched the coordinates we counted without the microscope. Pictures of the patterns of the wafers were taken and shown in Figure 9. Figure 8: The microscope used to inspect the photoresist patterns. It is also connected with a camera to take pictures that were taken as the pictures in Figure 9.

8 Figure 9: The wafers in a microscopic view, we inspect the photoresist to determine if repetition of any photoresist process is needed. 7

9 8 Figure 10: The constant dose profile of boron obtained from the diffusion spreadsheet (obtain from

10 9 Problem Discuss any problems that you may have encountered during the processing. The major problem that we faced during this lab is during the PWELL Diffusion was Weng Hoong Loo s wafer broke into half as shown in Figure 11. We noticed this after the boron deposition procedure. Once the soak step was done, during the pulling procedure, at first, we noticed that the wafer was not fitting correctly on the boat, as half of the wafer was dangling from the bottom of the boat, but still contained in the boat. After pulling it out, we inspected in on a plate and were pretty amazed by how it got broken right in the middle. By gathering information from our TA and Dr. Tuttle we have some explanations of why the wafer could have broken. One of the possibilities is there could have been micro scratches done by us, from handling it too rough, It could be from scratches from the microscope while we were inspecting it. Pulling the wafer out from the mask aligner too abruptly Clipping the wafers too hard from using the tweezers. Not placing it in the boat correctly, with pressure applying on the boat holder infused with the heat, the pressure was too great and caused the wafer to snap. Manufacturing defect. The heat absorbed throughout the wafer may not have been even, that caused one area to expand faster than other causing it to crack. By analyzing the different causes and discussing with the team members, we believed that it was due to the micro scratches. Thus, we will be more cautious and gentle towards our wafers from now on then. Figure 11: The broken wafer.

11 10 Appendix Figure 12: Calculations to get the temperature and time needed for the Boron Deposition by setting the temperature to be 850⁰C re-typed from Figure 13.

12 Figure 13: Calculations by hand with the formulas in Figure 14, blood, sweat and tears (done by Andrew McNeil) 11

13 12 Figure 14: Formula used for the calculations in Figure calculations. Figure 15: The measurement of the oxide thickness from the oxidation process of the previous lab. (taken from the process traveler.)

14 Process Traveler for PWELL Lithography and Diffusion 13

15 14

16 15

17 16

EE 432/532 CyMOS process PWELL Lithography & Diffusion Feb 24, 2016

EE 432/532 CyMOS process PWELL Lithography & Diffusion Feb 24, 2016 EE 432/532 CyMOS process PWELL Lithography & Diffusion Feb 24, 2016 Friday Afternoon Group Brady Koht Sebastian Roe Peter Bonnie Joseph Wickner Lab Instructor Yunfei Zhao 1. Overview Now that a Field Oxide

More information

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers Aaron Pederson EE 432 Lab Dr. Meng Lu netid: abp250 Lab instructor: Yunfei Zhao Report 1 A. Overview The goal of this lab is to go through the semiconductor fabrication process from start to finish. This

More information

Report 2. Aaron Pederson EE 432 Lab Dr. Meng Lu netid: abp250 Lab instructor: Yunfei Zhao. Steps:

Report 2. Aaron Pederson EE 432 Lab Dr. Meng Lu netid: abp250 Lab instructor: Yunfei Zhao. Steps: Aaron Pederson EE 432 Lab Dr. Meng Lu netid: abp250 Lab instructor: Yunfei Zhao Report 2 A. Overview This section comprised of source and drain construction for the NMOS and PMOS. This includes two different

More information

EE 432 CyMOS process PWELL Photolithography and Diffusion Feb. 23th 2017

EE 432 CyMOS process PWELL Photolithography and Diffusion Feb. 23th 2017 1 EE 432 CyMOS process PWELL Photolithography and Diffusion Feb. 23th 2017 Group III Jake Asmus (Leader) John Guss Shengliang Liu Xin Chen Lab instructor Matt Weinstein 2 Overview With the field oxide

More information

CyMOS process Spring 2016 Iowa State University

CyMOS process Spring 2016 Iowa State University CyMOS process Spring 2016 Iowa State University Start Date Starting Material Orientation: Dopant: Resistivity: Ω cm Doping Concentration: cm 3 Diameter: inch Thickness: µm Lot Identification: Wafer Count

More information

Lab 2: PWELL Lithography and Diffusion

Lab 2: PWELL Lithography and Diffusion Brandon Baxter, Robert Buckley Lab Instructor: Liang Zhang Course Instructor: Gary Tuttle EE 432-532 Due: February 23, 2017 Lab 2: PWELL Lithography and Diffusion 1. Overview The purpose of this lab was

More information

Lab 1: Field Oxide. Overview. Starting Wafers

Lab 1: Field Oxide. Overview. Starting Wafers Overview Lab 1: Field Oxide Brandon Baxter, Robert Buckley, Tara Mina, Quentin Vingerhoets Lab instructor: Liang Zhang Course Instructor: Dr. Gary Tuttle EE 432-532 January 23, 2017 In this lab we created

More information

Microelectronic Device Instructional Laboratory. Table of Contents

Microelectronic Device Instructional Laboratory. Table of Contents Introduction Process Overview Microelectronic Device Instructional Laboratory Introduction Description Flowchart MOSFET Development Process Description Process Steps Cleaning Solvent Cleaning Photo Lithography

More information

EELE408 Photovoltaics Lecture 02: Silicon Processing

EELE408 Photovoltaics Lecture 02: Silicon Processing EELE408 Photovoltaics Lecture 0: licon Processing Dr. Todd J. Kaiser tjkaiser@ece.montana.edu Department of Electrical and Computer Engineering Montana State University - Bozeman The Fabrication Process

More information

Temperature Scales. Questions. Temperature Conversions 7/21/2010. EE580 Solar Cells Todd J. Kaiser. Thermally Activated Processes

Temperature Scales. Questions. Temperature Conversions 7/21/2010. EE580 Solar Cells Todd J. Kaiser. Thermally Activated Processes 7/1/010 EE80 Solar Cells Todd J. Kaiser Flow of Wafer in Fabrication Lecture 0 Microfabrication A combination of Applied Chemistry, Physics and ptics Thermal Processes Diffusion & xidation Photolithograpy

More information

This Appendix discusses the main IC fabrication processes.

This Appendix discusses the main IC fabrication processes. IC Fabrication B B.1 Introduction This Appendix discusses the main IC fabrication processes. B.2 NMOS fabrication NMOS transistors are formed in a p-type substrate. The NMOS fabrication process requires

More information

Lab #2 Wafer Cleaning (RCA cleaning)

Lab #2 Wafer Cleaning (RCA cleaning) Lab #2 Wafer Cleaning (RCA cleaning) RCA Cleaning System Used: Wet Bench 1, Bay1, Nanofabrication Center Chemicals Used: H 2 O : NH 4 OH : H 2 O 2 (5 : 1 : 1) H 2 O : HF (10 : 1) H 2 O : HCl : H 2 O 2

More information

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB Fabrication Process Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation 1 Fabrication- CMOS Process Starting Material Preparation 1. Produce Metallurgical Grade Silicon

More information

Thermal Oxidation and Growth of Insulators (Chapter 3 - Jaeger 3) Key advantage of Si: Oxidation of Si into SiO 2 (glass) Major factor in making

Thermal Oxidation and Growth of Insulators (Chapter 3 - Jaeger 3) Key advantage of Si: Oxidation of Si into SiO 2 (glass) Major factor in making Thermal Oxidation and Growth of Insulators (Chapter 3 - Jaeger 3) Key advantage of Si: Oxidation of Si into SiO (glass) Major factor in making Silicon the main semiconductor Grown at high temperature in

More information

Fabrication Technology

Fabrication Technology Fabrication Technology By B.G.Balagangadhar Department of Electronics and Communication Ghousia College of Engineering, Ramanagaram 1 OUTLINE Introduction Why Silicon The purity of Silicon Czochralski

More information

DEPARTMENT OF MECHANICAL SCIENCE AND ENGINEERING UNIVERSITY OF ILLINOIS. ME498 PV Class. Laboratory Manual on Fundamentals of Solar Cell Manufacturing

DEPARTMENT OF MECHANICAL SCIENCE AND ENGINEERING UNIVERSITY OF ILLINOIS. ME498 PV Class. Laboratory Manual on Fundamentals of Solar Cell Manufacturing DEPARTMENT OF MECHANICAL SCIENCE AND ENGINEERING UNIVERSITY OF ILLINOIS ME498 PV Class Laboratory Manual on Fundamentals of Solar Cell Manufacturing Prepared by Bruno Azeredo, and Dr. Elif Ertekin 9/21/2013

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 3D Perspective 2 3 Fabrication

More information

Total Points = 110 possible (graded out of 100)

Total Points = 110 possible (graded out of 100) Lab Report 1 Table of Contents 1. Profiles & Layout (9 Points) 2. Process Procedures (20 points) 3. Calculations (36 Points) 4. Questions (35 Points) 5. Bonus Questions (10 Points) Total Points = 110 possible

More information

How To Write A Flowchart

How To Write A Flowchart 1 Learning Objectives To learn how you transfer a device concept into a process flow to fabricate the device in the EKL labs You learn the different components that makes up a flowchart; process blocks,

More information

EE 432/532 Field oxide CyMOS process Jan. 24, 2017

EE 432/532 Field oxide CyMOS process Jan. 24, 2017 EE 432/532 Field oxide CyMOS process Jan. 24, 2017 Group 5 Trevor Brown Michael Miller Xi Zhu David Orona 1. Overview Lab instructor Le Wei An electronic wafer is a thin slice of semiconductor material

More information

Photolithography I ( Part 2 )

Photolithography I ( Part 2 ) 1 Photolithography I ( Part 2 ) Chapter 13 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Bjørn-Ove Fimland, Department of Electronics and Telecommunication, Norwegian University of Science

More information

3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005

3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005 3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005 1) This is an open book, take-home quiz. You are not to consult with other class members or anyone else. You may discuss the

More information

4. Thermal Oxidation. a) Equipment Atmospheric Furnace

4. Thermal Oxidation. a) Equipment Atmospheric Furnace 4. Thermal Oxidation a) Equipment Atmospheric Furnace Oxidation requires precise control of: temperature, T ambient gas, G time spent at any given T & G, t Vito Logiudice 34 4. Thermal Oxidation b) Mechanism

More information

PDS Products PRODUCT DATA SHEET. BN-975 Wafers. Low Defect Boron Diffusion Systems. Features/Benefits BORON NITRIDE

PDS Products PRODUCT DATA SHEET. BN-975 Wafers. Low Defect Boron Diffusion Systems. Features/Benefits BORON NITRIDE Low Defect Boron Diffusion Systems The purpose of the hydrogen injection process is to increase die yield per wafer. This is accomplished because the effects associated with the hydrogen injection process.

More information

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing CS/ECE 5710/6710 CMOS Processing Addison-Wesley N-type Transistor D G +Vgs + Vds S N-type from the top i electrons - Diffusion Mask Mask for just the diffused regions Top view shows patterns that make

More information

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing 3. Conventional licon Processing Micromachining, Microfabrication. EE 5344 Introduction to MEMS CHAPTER 3 Conventional Processing Why silicon? Abundant, cheap, easy to process. licon planar Integrated

More information

Fabrication Technology, Part I

Fabrication Technology, Part I EEL5225: Principles of MEMS Transducers (Fall 2003) Fabrication Technology, Part I Agenda: Oxidation, layer deposition (last lecture) Lithography Pattern Transfer (etching) Impurity Doping Reading: Senturia,

More information

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline: ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline: Fabrication of p-n junctions Contact Potential Things you should know when you leave Key Questions What are the necessary steps to fabricate

More information

Buffered Oxide Etch STANDARD OPERATING PROCEDURE

Buffered Oxide Etch STANDARD OPERATING PROCEDURE Buffered Oxide Etch STANDARD OPERATING PROCEDURE TABLE OF CONTENTS: 1. SUMMARY..2 2. INTRODUCTION...3 3. LOCATION OF EQUIPMENT, ACCESSORIES, TOOLS AND SUPPLIES.4 4. PERSONAL SAFETY EQUIPMENT...5 5. MATERIAL

More information

3.155J / 6.152J MICROELECTRONICS PROCESSING TECHNOLOGY TAKE-HOME QUIZ FALL TERM 2003

3.155J / 6.152J MICROELECTRONICS PROCESSING TECHNOLOGY TAKE-HOME QUIZ FALL TERM 2003 3.155J / 6.152J MICROELECTRONICS PROCESSING TECHNOLOGY TAKE-HOME QUIZ FALL TERM 2003 1) This is an open book, take-home quiz. You are not to consult with other class members or anyone else. You may discuss

More information

Semiconductor Device Fabrication Study

Semiconductor Device Fabrication Study Proceedings of The National Conference on Undergraduate Research (NCUR) 2003 University of Utah, Salt Lake City, Utah March 13-15, 2003 Semiconductor Device Fabrication Study Tsung-Ta Ho and Michael R.

More information

Supporting Information: Model Based Design of a Microfluidic. Mixer Driven by Induced Charge Electroosmosis

Supporting Information: Model Based Design of a Microfluidic. Mixer Driven by Induced Charge Electroosmosis Supporting Information: Model Based Design of a Microfluidic Mixer Driven by Induced Charge Electroosmosis Cindy K. Harnett, Yehya M. Senousy, Katherine A. Dunphy-Guzman #, Jeremy Templeton * and Michael

More information

ProTemp Furnace SOP Page 1 of 15 Revision Scope 1.1 This SOP provides instructions to operate the ProTemp Atmospheric Furnaces.

ProTemp Furnace SOP Page 1 of 15 Revision Scope 1.1 This SOP provides instructions to operate the ProTemp Atmospheric Furnaces. ProTemp urnace OP ProTemp urnace OP Page 1 of 15 1 cope 1.1 This OP provides instructions to operate the ProTemp Atmospheric urnaces. 2 Table of Contents 1 cope... 1 2 Table of Contents... 1 3 Reference

More information

PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam

PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam PHYS 534 (Fall 2008) Process Integration Srikar Vengallatore, McGill University 1 OUTLINE Examples of PROCESS FLOW SEQUENCES >Semiconductor diode >Surface-Micromachined Beam Critical Issues in Process

More information

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to Supporting Information: Substrate preparation and SLG growth: All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to aid in visual inspection of the graphene samples. Prior

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)

More information

Supporting Information for

Supporting Information for Supporting Information for Core-Shell CdS-Cu 2 S Nanorod Array Solar Cells Andrew Barnabas Wong,, Sarah Brittman,, Yi Yu,, Neil P. Dasgupta,, and Peidong Yang,,,,* Department of Chemistry, University of

More information

EE 330 Lecture 9. IC Fabrication Technology Part 2

EE 330 Lecture 9. IC Fabrication Technology Part 2 EE 330 Lecture 9 IC Fabrication Technology Part 2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this

More information

Increased Yield Using PDS Products Grade BN-975 with Hydrogen Injection

Increased Yield Using PDS Products Grade BN-975 with Hydrogen Injection Increased Yield Using PDS Products Grade BN-975 with Hydrogen Injection Technical Bulletin The purpose of the hydrogen injection process is to increase die yield per wafer. This is accomplished because

More information

Chapter 2 MOS Fabrication Technology

Chapter 2 MOS Fabrication Technology Chapter 2 MOS Fabrication Technology Abstract This chapter is concerned with the fabrication of metal oxide semiconductor (MOS) technology. Various processes such as wafer fabrication, oxidation, mask

More information

Wafer Cleaning and Oxide Growth Laboratory Dr. Lynn Fuller Webpage:

Wafer Cleaning and Oxide Growth Laboratory Dr. Lynn Fuller Webpage: ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Wafer Cleaning and Oxide Growth Laboratory Dr. Lynn Fuller Webpage: http://www.rit.edu/~lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604

More information

Diffusion/Anneal SOP Page 1 of 12 Revision

Diffusion/Anneal SOP Page 1 of 12 Revision Diffusion/Anneal SOP Diffusion/Anneal SOP Page 1 of 12 1 Scope 1.1 This document provides the procedures and requirements to introduce and/or drive dopants into silicon using the Canary furnace. 2 Table

More information

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in Chapter 5 PROCESSING OF DEVICES A discussion of crystal growth, lithography, etching, doping, and device structures is presented in the following overview gures. SEMICONDUCTOR DEVICE PROCESSING: AN OVERVIEW

More information

Major Fabrication Steps in MOS Process Flow

Major Fabrication Steps in MOS Process Flow Major Fabrication Steps in MOS Process Flow UV light Mask oxygen Silicon dioxide photoresist exposed photoresist oxide Silicon substrate Oxidation (Field oxide) Photoresist Coating Mask-Wafer Alignment

More information

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing ELEC 3908, Physical Electronics, Lecture 4 Basic Integrated Circuit Processing Lecture Outline Details of the physical structure of devices will be very important in developing models for electrical behavior

More information

Selective-Area Atomic Layer Deposition (SA-ALD) of Titanium Dioxide (TiO 2) using Poly(methyl methacrylate) (PMMA) Michael Tu 5/12/2016

Selective-Area Atomic Layer Deposition (SA-ALD) of Titanium Dioxide (TiO 2) using Poly(methyl methacrylate) (PMMA) Michael Tu 5/12/2016 Selective-Area Atomic Layer Deposition (SA-ALD) of Titanium Dioxide (TiO 2) using Poly(methyl methacrylate) (PMMA) Michael Tu 5/12/2016 Introduction The Minnesota Nano Center s Keller Hall facility includes

More information

Czochralski Crystal Growth

Czochralski Crystal Growth Czochralski Crystal Growth Crystal Pulling Crystal Ingots Shaping and Polishing 300 mm wafer 1 2 Advantage of larger diameter wafers Wafer area larger Chip area larger 3 4 Large-Diameter Wafer Handling

More information

Chapter 2 Manufacturing Process

Chapter 2 Manufacturing Process Digital Integrated Circuits A Design Perspective Chapter 2 Manufacturing Process 1 CMOS Process 2 CMOS Process (n-well) Both NMOS and PMOS must be built in the same silicon material. PMOS in n-well NMOS

More information

ABSTRACT. which indicates the implanted region did not adequately inhibit the diffusion of oxygen.

ABSTRACT. which indicates the implanted region did not adequately inhibit the diffusion of oxygen. . INVESTIGATION OF LOCOS PROCESS USING NITROGEN IMPL~NTAT ION Joseph W. Walters 5th Year Microelectronic Engineering Student Rochester Institute of Technology INTRODUCTION ABSTRACT A localized oxidation

More information

Module 1 and 2 Report

Module 1 and 2 Report Module 1 and 2 Report Interdisciplinary Microelectronics Processing Lab Group D Jaimie Stevens, Erich P. Meinig, Adam Longoria, Emily Makoutz, Ben Timmer Date: February 10, 2015 Abstract This report details

More information

EE 330 Lecture 8. IC Fabrication Technology Part II. - Masking - Photolithography - Deposition - Etching - Diffusion

EE 330 Lecture 8. IC Fabrication Technology Part II. - Masking - Photolithography - Deposition - Etching - Diffusion EE 330 Lecture 8 IC Fabrication Technology Part II?? - Masking - Photolithography - Deposition - Etching - Diffusion Review from Last Time Technology Files Provide Information About Process Process Flow

More information

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS Contents: VI Sem ECE 06EC63: Analog and Mixed Mode VLSI Design PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS 1. Introduction 2. CMOS Fabrication 3. Simplified View of Fabrication Process 3.1 Alternative

More information

Semiconductor device fabrication

Semiconductor device fabrication REVIEW Semiconductor device fabrication is the process used to create the integrated circuits (silicon chips) that are present in everyday electrical and electronic devices. It is a multiplestep sequence

More information

Schematic creation of MOS field effect transistor.

Schematic creation of MOS field effect transistor. Schematic creation of MOS field effect transistor. Gate electrode Drain electrode Source electrode Gate oxide Gate length Page 1 Step 0 The positively doped silicon wafer is first coated with an insulating

More information

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #9

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #9 Issued: Tuesday, Nov. 11, 2014 PROBLEM SET #9 Due: Wednesday, Nov. 19, 2010, 8:00 a.m. in the EE 143 homework box near 140 Cory 1. The following pages comprise an actual pwell CMOS process flow with poly-to-poly

More information

Making of a Chip Illustrations

Making of a Chip Illustrations Making of a Chip Illustrations 22nm 3D/Trigate Transistors Version April 2015 1 The illustrations on the following foils are low resolution images that visually support the explanations of the individual

More information

Chapter 3 CMOS processing technology

Chapter 3 CMOS processing technology Chapter 3 CMOS processing technology (How to make a CMOS?) Si + impurity acceptors(p-type) donors (n-type) p-type + n-type => pn junction (I-V) 3.1.1 (Wafer) Wafer = A disk of silicon (0.25 mm - 1 mm thick),

More information

Fabrication and Layout

Fabrication and Layout Fabrication and Layout Kenneth Yun UC San Diego Adapted from EE271 notes, Stanford University Overview Semiconductor properties How chips are made Design rules for layout Reading Fabrication: W&E 3.1,

More information

micro resist technology

micro resist technology Characteristics Processing guidelines Negative Tone Photoresist Series ma-n 2400 ma-n 2400 is a negative tone photoresist series designed for the use in micro- and nanoelectronics. The resists are available

More information

Silicon Manufacturing

Silicon Manufacturing Silicon Manufacturing Group Members Young Soon Song Nghia Nguyen Kei Wong Eyad Fanous Hanna Kim Steven Hsu th Fundamental Processing Steps 1.Silicon Manufacturing a) Czochralski method. b) Wafer Manufacturing

More information

Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference

Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between 2 materials Need strong selectivity from masking

More information

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley Microstructure of Electronic Materials Amorphous materials Single-Crystal Material 1 The Si Atom The Si Crystal diamond structure High-performance semiconductor devices require defect-free crystals 2 Crystallographic

More information

Chapter 3 Silicon Device Fabrication Technology

Chapter 3 Silicon Device Fabrication Technology Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale

More information

MEMS LAB MANUAL. Matthew Leone Todd Kaiser Montana State University. Special Thanks to: Andy Lingley Brad Pierson Phil Himmer

MEMS LAB MANUAL. Matthew Leone Todd Kaiser Montana State University. Special Thanks to: Andy Lingley Brad Pierson Phil Himmer MEMS LAB MANUAL 2007 A complete description of the fabrication sequence for piezoresistive MEMS sensors. This manual was designed for use with the Montana Microfabrication Facility at MSU. Special Thanks

More information

micro resist technology

micro resist technology Characteristics Processing guidelines Negative Tone Photoresist Series ma-n 1400 ma-n 1400 is a negative tone photoresist series designed for the use in microelectronics and microsystems. The resists are

More information

MEMS Surface Fabrication

MEMS Surface Fabrication ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING MEMS Surface Fabrication Dr. Lynn Fuller webpage: http://people.rit.edu/lffeee Electrical and Microelectronic Engineering Rochester Institute

More information

Scibond SL-23 Polymeric Lubrication System for Tube Drawing

Scibond SL-23 Polymeric Lubrication System for Tube Drawing Scibond SL-23 Polymeric Lubrication System for Tube Drawing I. Introduction: Scibond SL-23 is a novel water-based a polymeric lubrication system. It was developed under National Science Foundation grant

More information

Semiconductor Technology

Semiconductor Technology Semiconductor Technology von A bis Z Silicon Silicon Isotropic etch process Anisotropic etch process Wet chemistry www.halbleiter.org Contents Contents List of Figures II 1 Wet chemistry 1 1.1 Etch processes..................................

More information

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each

More information

ALD Film Characterization Rachel Brown 5/13/14

ALD Film Characterization Rachel Brown 5/13/14 ALD Film Characterization Rachel Brown 5/13/14 Objective The following set of tests was performed to determine the characteristics of films created by the Atomic Layer system and how they varied with the

More information

EE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects

EE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects EE 330 Lecture 8 IC Fabrication Technology Part II - Oxidation - Epitaxy - Polysilicon - Interconnects Review from Last Time MOS Transistor Bulk Source Gate Drain p-channel MOSFET Lightly-doped n-type

More information

Screen Printing of Highly Loaded Silver Inks on. Plastic Substrates Using Silicon Stencils

Screen Printing of Highly Loaded Silver Inks on. Plastic Substrates Using Silicon Stencils Supporting Information Screen Printing of Highly Loaded Silver Inks on Plastic Substrates Using Silicon Stencils Woo Jin Hyun, Sooman Lim, Bok Yeop Ahn, Jennifer A. Lewis, C. Daniel Frisbie*, and Lorraine

More information

CMOS LAB MANUAL CMOS LAB MANUAL

CMOS LAB MANUAL CMOS LAB MANUAL CMOS LAB MANUAL 2011 CMOS LAB MANUAL This manual was designed for use with the Montana Microfabrication Facility at MSU. The intention of the manual is to provide lab users and MSU students with a complete

More information

Photolithography Process Technology

Photolithography Process Technology Contents Photolithography Process - Wafer Preparation - Photoresist Coating - Align & Expose - Photoresist Development Process Control CD Measurement Equipment Expose System & Wafer Track Consumables Chemicals

More information

6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term Solution to Problem Set 2 (16 pts)

6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term Solution to Problem Set 2 (16 pts) 6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term 2007 By Brian Taff (Adapted from work by Feras Eid) Solution to Problem Set 2 (16 pts) Issued: Lecture 4 Due: Lecture

More information

VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents UNIT I INTRODUCTION: Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies. BASIC ELECTRICAL PROPERTIES : Basic Electrical

More information

Fabrication and Layout

Fabrication and Layout ECEN454 Digital Integrated Circuit Design Fabrication and Layout ECEN 454 3.1 A Glimpse at MOS Device Polysilicon Aluminum ECEN 475 4.2 1 Material Classification Insulators Glass, diamond, silicon oxide

More information

Isolation Technology. Dr. Lynn Fuller

Isolation Technology. Dr. Lynn Fuller ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041

More information

VLSI. Lecture 1. Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University. Based on slides of David Money Harris

VLSI. Lecture 1. Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University. Based on slides of David Money Harris VLSI Lecture 1 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University Based on slides of David Money Harris Goals of This Course Learn the principles of VLSI design Learn to design

More information

Cost Effective 3D Glass Microfabrication for Advanced Packaging Applications

Cost Effective 3D Glass Microfabrication for Advanced Packaging Applications Cost Effective 3D Glass Microfabrication for Advanced Packaging Applications Authors: Jeb. H Flemming, Kevin Dunn, James Gouker, Carrie Schmidt, Roger Cook ABSTRACT Historically, while glasses have many

More information

Low-temperature, Simple and Fast Integration Technique of Microfluidic Chips by using a UV-curable Adhesive

Low-temperature, Simple and Fast Integration Technique of Microfluidic Chips by using a UV-curable Adhesive Low-temperature, Simple and Fast Integration Technique of Microfluidic Chips by using a UV-curable Adhesive Supplementary Information Channel fabrication Glass microchannels. A borosilicate glass wafer

More information

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time IC Fabrication Technology Crystal Preparation

More information

Surface micromachining and Process flow part 1

Surface micromachining and Process flow part 1 Surface micromachining and Process flow part 1 Identify the basic steps of a generic surface micromachining process Identify the critical requirements needed to create a MEMS using surface micromachining

More information

Mostafa Soliman, Ph.D. May 5 th 2014

Mostafa Soliman, Ph.D. May 5 th 2014 Mostafa Soliman, Ph.D. May 5 th 2014 Mostafa Soliman, Ph.D. 1 Basic MEMS Processes Front-End Processes Back-End Processes 2 Mostafa Soliman, Ph.D. Wafers Deposition Lithography Etch Chips 1- Si Substrate

More information

Bulk MEMS Fabrication Blog 2017 Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

Bulk MEMS Fabrication Blog 2017 Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Bulk MEMS Fabrication Blog 2017 Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive

More information

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook CMOS Fabrication Dr. Bassam Jamil Adopted from slides of the textbook CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different

More information

Via Fill in Small Trenches using Hot Aluminum Process. By Alice Wong

Via Fill in Small Trenches using Hot Aluminum Process. By Alice Wong Via Fill in Small Trenches using Hot Aluminum Process By Alice Wong Goals for Project Good Via Fill in Small contact holes using hot aluminum process Be able to get good images of the contact holes using

More information

CALTECH CONFERENCE ON VLSI, January 1979

CALTECH CONFERENCE ON VLSI, January 1979 113 A SIMPLE TWO-LAYER ALUMINUM METAL PROCESS FOR VLSI Robert J. Huber Electrical Engineering Department University of Utah Salt Lake City, Utah 84112 I. Introduction The use of two levels of metal interconnect

More information

Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon

Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon Chapter 5 Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon 5.1 Introduction In this chapter, we discuss a method of metallic bonding between two deposited silver layers. A diffusion

More information

Because of equipment availability, cost, and time, we will use aluminum as the top side conductor

Because of equipment availability, cost, and time, we will use aluminum as the top side conductor Because of equipment availability, cost, and time, we will use aluminum as the top side conductor Top Side Conductor vacuum deposition Aluminum sputter deposit in Argon plasma CVC 601-sputter deposition

More information

Doping and Oxidation

Doping and Oxidation Technische Universität Graz Institute of Solid State Physics Doping and Oxidation Franssila: Chapters 13,14, 15 Peter Hadley Technische Universität Graz Institute of Solid State Physics Doping Add donors

More information

UPDATE ON SB 14 SEMICONDUCTOR INDUSTRY ASSESSMENT

UPDATE ON SB 14 SEMICONDUCTOR INDUSTRY ASSESSMENT UPDATE ON SB 14 SEMICONDUCTOR INDUSTRY ASSESSMENT Relly Briones California Environmental Protection Agency Department of Toxic Substances Control Office of Pollution Prevention and Technology Development

More information

GLM General information. Technical Datasheet

GLM General information. Technical Datasheet GLM 2060 Nanocomposite SU-8-negative tone photo-epoxy for layers from 6.0 to 50µm Technical Datasheet Gersteltec Sarl. Générale Guisan 26, 1009, Pully Switzerland Switzerland / Israel / Taiwan Contact:

More information

Processing guidelines. Negative Tone Photoresist Series ma-n 2400

Processing guidelines. Negative Tone Photoresist Series ma-n 2400 Characteristics Processing guidelines Negative Tone Photoresist Series ma-n 2400 ma-n 2400 is a negative tone photoresist series designed for the use in micro- and nanoelectronics. The resists are available

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2011

EE C245 ME C218 Introduction to MEMS Design Fall 2011 Lecture Outline EE C245 ME C218 Introduction to MEMS Design Fall 2011 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720

More information

Process Flow in Cross Sections

Process Flow in Cross Sections Process Flow in Cross Sections Process (simplified) 0. Clean wafer in nasty acids (HF, HNO 3, H 2 SO 4,...) --> wear gloves! 1. Grow 500 nm of SiO 2 (by putting the wafer in a furnace with O 2 2. Coat

More information

Basic&Laboratory& Materials&Science&and&Engineering& Etching&of&Semiconductors&

Basic&Laboratory& Materials&Science&and&Engineering& Etching&of&Semiconductors& ! Basic&Laboratory&! Materials&Science&and&Engineering& Etching&of&Semiconductors& M104&!!!as!of:!31.10.2013!! Aim: To gain a basic understanding of etching techniques, characterization, and structuring

More information

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width Microelectronics Introduction to the IC technology M.Rencz 11 September, 2002 9/16/02 1/37 Integrated circuits Development is controlled by the roadmaps. Self-fulfilling predictions for the tendencies

More information