Development of High Voltage Silicon Carbide MOSFET Devices in KERI

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1 Development of High Voltage Silicon Carbide MOSFET Devices in KERI Kim, Sang Cheol Power Semiconductor Device Research Center Korea Electrotechnology Research Institute

2 Contents Introduction Why Silicon Carbide Semiconductors? Power Semiconductor Research Activities in KERI Power Semiconductor Key Technologies Silicon Carbide Power MOSFET Design Silicon Carbide Power MOSFET Fabrication Results Summary & Future Works

3 Introduction Global environmental and energy problem Improve the levels of efficiency of power converters The characteristics of Si power devices have almost reached their theoretical limitations, and further improvements are now becoming difficult to achieve. Performance limit of Power Devices

4 Introduction EV Power Consumer Appliance SiC Device Aero- Space -High Voltage -High Frequency -High Temperature Industial Nuclear -High Density -Radiation -Low Loss Potential Application of SiC Devices Requirements

5 Why SiC Semiconductors? SiC exhibits a power density possibly one order of magnitude or more compared to silicon. - Current density can easily reach 5 to 10A/mm 2 - Breakdown voltage(volt/um of epilayer) is typically in the 100V/um for SiC (10V/um for Silicon) A single SiC device will drive higher current and voltage in a reduced footprint. SiC is intrinsically very high thermal conductive material. Higher electron mobility of SiC also permits higher frequency operation in switching mode.

6 Power Semiconductor Research Activities in KERI SiC Epitaxy 600V SiC SBD 2000V SiC PN Diode SiC Wafer Defect Analysis Si Dynistor Si IGCT 600V SiC VDMOSFET 1200V SiC VDMOSFET 2500V SiC VDMOSFET

7 Power Semiconductor Key Tech. Process High resolution - <0.5 um process - 64M DRAM equiv. Trench process - Surface roughness - Deep & High aspect ratio - Uniformity Thin wafer technology -Thin wafer handling - Grinding/ Roughness /damaged layer removal - High energy implantation - Low temp. activation emitter gate n+ P - base n- n0 FS layer p-layer collector Design High Performance - Tighter & Optimized active cell design - Channel/trench design for the short circuit capability High voltage - Design the thickness & concentration - Reliable high BV Junction termination High efficiency - Control injection efficiency

8 1.2kV SiC Power MOSFET Design BV=1200V Tepi > 15um Cepi < 2E15cm -3 Junc. Depth ~0.5um Cp-base > 4E17cm -3 Epi-layer Selection P-base Design VT < 5V Csurface < 7E16cm -3 Retrograde profile JFET : 2~4um Threshold Voltage Design On-resistance Design

9 1.2kV SiC Power MOSFET Design N-Sub Concentration : 1E19/ cm3 N-Epi Concentration : 2E15/ cm3 N-Epi Thickness : 15um P-well Concentration(surface) : 7E16/ cm3 P-well Concentration(junction) : 4E17/ cm3 P-well Junction Depth : 0.5~0.7um N-Source Concentration : 1E19/ cm3 N-Source Junction Depth : 0.2um Channel length : 0.5~2.0um JFET Width : 2~4um # of Fleid Limiting Ring : 8

10 SiC Power MOSFET Fabrication Initial oxidation Align key PHOTO Align key ETCH Oxidation P-Well Photo P-Well ETCH P-Well IMP EPI inspection Cleaning Oxidation PR Coat Exposure Develop Etch ashing PR Romove Cleaning Oxide depo PR coat Exposure Develop Pwell Etch Ashing PR Remove P-well I/I Oxide strip Oxidation P+ photo P+ ETCH P+ IMP Oxidation N+ photo N+ ETCH N+ IMP Cleaning Oxide depo PR Coat Exposure Develop Pwell Etch Ashing PR Remove P-Well I/I Oxide strip Cleaning Oxide depo PR Coat Exposure Develop Pwell Etch Ashing PR Remove N+ I/I Cleaning Activation anneal Gate OX Poly Poly PHOTO Poly ETCH PECVD deposition CNT Photo Contact Etch POLY back etch annel 1 st Sac. Ox. Oxide strip Cleaning Gate Ox. Poly Depo 검사 PR Coat Exposure Develop Poly Etch Ashing PR Remove Cleaning PSG depo PR Coat Exposure Develop Etch Ashing PR Remove Poly Etch Silicide metal deposition Back metal depo Silicide photo Silicide etch Silicidation Front metal MET PHOTO Metal Etch Cleaning Depo Cleaning Depo PR Coat Exposure Develop wet etch PR strip RTA Cleaning Depo PR Coat Exposure Develop Etch Dust Etch Ashing

11 Concentration [atomic/cm 3 ] Intensity [cps] Key Process in KERI Ion Implantation Condition 1E22 1E E20 1E19 1E18 1E17 1E16 1E15 14N 27Al 12C 30Si E Depth Profile [nm] P-Well Ion implantation : Junction depth = 0.6~0.8um Retrograde profile N-Source Ion implantation : Junction depth = 0.2~0.25um Box profile

12 Key Process in KERI Hard Mask for Ion Implantation PR SiO 2 Precision < 0.5um Etching angle > 83

13 Key Process in KERI Gate Oxidation & Post Oxide Annealing Gate Oxide Condition : 1150 /5hr/Dry O 2 : 55nm Post Oxide Annealing Condition : 1175 /0~3hr/NO Concentration Interface Trap Density : POA Conduction Band Edge) CN & SiN Intensity : 100% NO POA TOF-SIMS analysis)

14 Key Process in KERI Gate Oxidation & Post Oxide Annealing (Time Zero Dielectric Breakdown Characteristics) 0hr NO Annealing 1hr NO Annealing 2hr NO Annealing 3hr NO Annealing Dielectric breakdown and leakage current characteristics were improved at 3hr NO annealing condition. 3hr NO post annealing was shown excellent result in Gate oxide reliability characteristics by constant voltage stress test From those results, 1175 /3hr NO annealing is best condition for Carbon restriction at SiO 2 -SiC interface.

15 Contact Silicide Key Process in KERI N-type Ohmic Contact P-type Ohmic Contact Target of this contact process Simultaneous N- & P-Ohmic Contact condition Conventional Simple Process condition Ti/Ni is good candidate metal for low contact resistance.

16 Results 4inch SiC Wafer & MOSFET Devices SiC MOSFET Package

17 Results Forward Characteristics Forward I-V Characteristics ( VG=5V) Threshold Voltage(VTH) Characteristic

18 Results Gate Oxide Quality GOX Quality Interface Trap Density (Dit) < 1E11cm -2 ev -1 Maximum Breakdown Field of Oxide (E C ) ~ 7MV/cm

19 Results Reverse Characteristics Strong dependence on Field Limiting Ring(FLR) space Several na s leakage characteristics Superior reverse characteristics on FLR + FP structure 6 FLR is enough to 1200V breakdown voltage

20 Switching Characteristics Results Test circuit & waveform Test board T R : 874ns T D : 210ns E on : 286uJ T F : 64ns T D : 21ns E off : 21.1uJ Turn-on waveform Turn-off waveform

21 Results Fabrication Yield 1 st stage yield < 30% Device (2 nd stage) Total Operate device Yield rate 2 nd stage yield > 60% #910_10A % 312 #920_10A % Device (3 rd stage) Total 3 rd stage yield > 70% Operate device Yield rate #10_2_10A %

22 Summary & Future Plan We developed successfully 1200V/40A high voltage SiC MOSFET devices. Design & Fabrication processes are carried out Maximum breakdown voltage is exceeded 1700V. On-state resistance characteristics are less than 55mΩ cm 2. Current density is 187A/ cm 2. Design & fabrication technology were transferred to semiconductor company. Our future plan is develop 15kV high voltage SiC MOSFET devices next 5 years for HVDC system.

23 Thank you very much for your attention