EE 330 Lecture 12. Devices in Semiconductor Processes
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1 EE 330 Lecture 12 Devices in Semiconductor Processes
2 Review from Lecture 9 Copper Interconnects Limitations of Aluminum Interconnects Electromigration Conductivity not real high Relevant Key Properties of Copper Reduced electromigration problems at given current level Better conductivity Challenges of Copper Interconnects Absence of volatile copper compounds (does not etch) Copper diffuses into surrounding materials (barrier metal required)
3 Review from Lecture 9 Copper Interconnects Practical methods of realizing copper interconnects took many years to develop Copper interconnects widely used in some processes today
4 Review from Lecture 9 Damascene Process Patterning of Copper Contact Opening after SiO 2 etch Photoresist
5 Review from Lecture 9 Damascene Process Patterning of Copper Tungsten (W) CMP Target
6 Review from Lecture 9 Chemical-Mechanical Planarization (CMP) Polishing Pad and Wafer Rotate in non-concentric pattern to thin, polish, and planarize surface Abrasive/Chemical polishing Depth and planarity are critical Acknowledgement:
7 Review from Lecture 9 Patterning of Copper Damascene Process After first CMP Step CMP Target W-plug
8 Review from Lecture 9 Damascene Process Patterning of Copper After first CMP Step Oxidation
9 Review from Lecture 9 Damascene Process Patterning of Copper Photoresist Patterned with Metal Mask Defines Trench
10 Review from Lecture 9 Patterning of Copper Damascene Process Shallow Trench after Etch W-plug
11 Review from Lecture 9 Damascene Process Patterning of Copper Barrier Metal (Barrier metal added before copper to contain the copper atoms)
12 Review from Lecture 9 Damascene Process Patterning of Copper W-plug Copper Deposition
13 Review from Lecture 9 Patterning of Copper Damascene Process W-plug CMP Target Copper Deposition Copper is deposited or electroplated (Barrier Metal Used for Electroplating Seed)
14 Review from Lecture 9 Patterning of Copper Damascene Process After Second CMP Step W-plug Copper CMP Target
15 Review from Lecture 9 Dual-Damascene Process Patterning of Copper Shallow Trench Defined in PR with Metal Mask Photoresist
16 Review from Lecture 9 Dual-Damascene Process Patterning of Copper Shallow Trench After Etch Photoresist
17 Review from Lecture 9 Dual-Damascene Process Patterning of Copper Via Defined in PR with Via Mask Photoresist
18 Review from Lecture 9 Dual-Damascene Process Patterning of Copper Via Etch Defines Contact Region Photoresist (Barrier Metal added before copper but not shown)
19 Review from Lecture 9 Dual-Damascene Process Patterning of Copper Copper Deposited on Surface Copper is deposited or electroplated (Barrier Metal Used for Electroplating Seed)
20 Review from Lecture 9 Dual-Damascene Process Patterning of Copper Copper Deposited on Surface CMP Target
21 Review from Lecture 9 Dual-Damascene Process Patterning of Copper Copper Via Copper Interconnect CMP Target
22 Review from Lecture 9 Patterning of Copper Both Damascene Processes Realize Same Structure Damascene Process Two Dielectric Deposition Steps Two CMP Steps Two Metal Deposition Steps Two Dielectric Etches W-Plug Dual-Damascene Process One Dielectric Deposition Steps One CMP Steps One Metal Deposition Steps Two Dielectric Etches Via formed with metal step
23 Resistivity of Materials used in Semiconductor Processing Cu: 1.7E-6 cm Al: 2.7E-4 cm Gold: 2.4E-6 cm Platinum: 3.0E-6 cm n-si:.25 to 5 cm intrinsic Si: 2.5E5 cm SiO 2 : E14 cm
24 Temperature Coefficients Used for indicating temperature sensitivity of resistors & capacitors For a resistor: 1 dr R dt 6 TCR 10 ppm C op. temp This diff eqn can easily be solved if TCR is a constant R R T R T 2 1 e T 2 T TCR T R T 1 T T TCR 10 Identical Expressions for Capacitors
25 Voltage Coefficients Used for indicating voltage sensitivity of resistors & capacitors For a resistor: 1 dr VCR R dv ref voltage 6 10 ppm V This diff eqn can easily be solved if VCR is a constant R V R V 2 1 e V 2 V VCR V R V V V R VCR Identical Expressions for Capacitors
26 Temperature and Voltage Coefficients Temperature and voltage coefficients often quite large for diffused resistors Temperature and voltage coefficients often quite small for poly and metal resistors
27 Basic Devices and Device Models Resistor Diode Capacitor MOSFET BJT
28
29
30 group (or family) 4 valence-band Electrons All elements in group IV have 4 valence-band electrons
31 Serves as an acceptor of electrons Acts as a p-type impurity when used as a silicon dopant All elements in group III have 3 valence-band electrons Only 3 Valenceband Electrons
32
33 Serves as an donor of electrons Acts as an n-type impurity when used as a silicon dopant All elements in group V have 5 valence-band electrons Five Valenceband Electrons
34
35
36 Silicon Dopants in Semiconductor Processes B (Boron) widely used a dopant for creating p-type regions P (Phosphorus) widely used a dopant for creating n-type regions (bulk doping, diffuses fast) As (Arsenic) widely used a dopant for creating n-type regions (Active region doping, diffuses slower)
37 Diodes (pn junctions) Depletion region created that is ionized but void of carriers
38 pn Junctions Physical Boundary Separating n-type and p-type regions If doping levels identical, depletion region extends equally into n-type and p-type regions
39 pn Junctions Physical Boundary Separating n-type and p-type regions Extends farther into p-type region if p-doping lower than n-doping
40 pn Junctions Physical Boundary Separating n-type and p-type regions Extends farther into n-type region if n-doping lower than p-doping
41 pn Junctions I D V D Positive voltages across the p to n junction are referred to forward bias Negative voltages across the p to n junction are referred to reverse bias As forward bias increases, depletion region thins and current starts to flow Current grows very rapidly as forward bias increases Current is very small under revere bias
42 pn Junctions Anode I D Anode V D Cathode Cathode Circuit Symbol
43 pn Junctions As forward bias increases, depletion region thins and current starts to flow Current grows very rapidly as forward bias increases V D I D Anode Cathode D Simple Diode Model: V =0 I >0 I =0 V <0 D I D D D V D Simple model often referred to as the Ideal diode model
44 pn Junctions I D Simple Diode Model: I D V D V D pn junction serves as a rectifier passing current in one direction and blocking it In the other direction
45 Rectifier Application: D 1 V OUT Simple Diode Model: I D V IN 1K V D V IN =V M sinωt V M V IN t V OUT V M t
46 I-V characteristics of pn junction Improved Diode Model: (signal or rectifier diode) I d I S in the 10fA to 100fA range V d kt V= t q Diode Equation I D Vd Vt I e 1 S What is V t at room temp? k= (24) JK -1 q = (40) C k/q= VK -1 Diode equation due to William Schockley, inventor of BJT In 1919, William Henry Eccles coined the term diode V t is about 26mV at room temp
47 End of Lecture 12
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