ECE 659. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Manufacturing.

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1 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Manufacturing Process July 0, 00 1 CMOS Process 1

2 A Modern CMOS Process gate-oxide TiSi AlCu Tungsten SiO n+ p-well p-epi poly n-well p+ SiO p+ Dual-Well Trench-Isolated CMOS Process Circuit Under Design V DD V DD M M4 V in V out V out M1 M 4

3 Its Layout View 5 The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check 6

4 Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch spin, rinse, dry 7 Patterning of SiO Si-substrate (a) Silicon base material Si-substrate Photoresist SiO (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Chemical or plasma etch Hardened resist SiO (d) After development and etching of resist, chemical or plasma etch of SiO (e) After etching Si-substrate Hardened resist SiO SiO (f) Final result after removal of resist 8 4

5 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers 9 CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ SiN 4 SiO (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 10 5

6 CMOS Process Walk-Through SiO (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants 11 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. SiO (i) After deposition of SiO insulator and contact hole etch. 1 6

7 CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO (k) After deposition of SiO insulator, etching of via s, deposition and patterning of second layer of Al. 1 Advanced Metallization 14 7

8 Advanced Metallization 15 Design Rules 16 8

9 D Perspective Polysilicon oys Aluminum 17 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) 18 9

10 CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal Contact To Poly Contact To Diffusion Via Color Yll Yellow Green Green Red Blue Magenta Black Black Black Representation 19 Layers in 0.5 μm m CMOS process 0 10

11 Intra-Layer Design Rules Same Potential Different Potential Well Active Select 10 0 or 6 9 Contact or Via Hole Polysilicon Metal1 Metal 4 1 Transistor Layout Transisto or

12 Vias and Contacts 1 Metal to Active Contact 1 Via 1 Metal to Poly Contact 4 5 Select Layer Select 1 5 Substrate Well 4 1

13 CMOS Inverter Layout GND In V DD A A Out (a) Layout A A n p-substrate Field n + p + Oxide (b) Cross-Section along A-A 5 Layout Editor 6 1

14 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um. 7 Sticks Diagram V DD In 1 Out Dimensionless layout entities Only topology is important Final layout generated by compaction program GND Stick diagram of inverter 8 14

15 Packaging 9 Packaging Requirements Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap 0 15

16 Bonding Techniques Wire Bonding Substrate Die Pad Lead Frame 1 Tape-Automated Bonding (TAB) Sprocket hole Film + Pattern Solder Bump Test pads Lead frame Polymer film Die Substrate (b) Die attachment using solder bumps. (a) Polymer Tape with imprinted wiring pattern. 16

17 Flip-Chip Bonding Die Solder bumps Interconnect layers Substrate Package-to-Board Interconnect (a) Through-Hole Mounting (b) Surface Mount 4 17

18 Package Types 5 Package Parameters 6 18

19 Multi-Chip Modules 7 19

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