Characteristics of HfO 2 pmosfet with Ultrashallow Junction Prepared by Plasma Doping and Laser Annealing
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1 Characteristics of HfO 2 pmosfet with Ultrashallow Junction Prepared by Plasma Doping and Laser Annealing Sungkweon Baek, Sungho Heo, and Hyunsang Hwang Dept. of Materials Science and Engineering Kwangju Institute of Science and Technology (KJIST) KOREA
2 Contents ESSDERC 2002 I. Introduction & Motivation - Ultra-shallow Junction - High-k dielectric gate oxide II.Experimental Procedure -Basic property -p + /n junction diode -HfO 2 capacitor -HfO 2 pmosfet III.Results & Discussion - Ultra-shallow Junction part Hall measurement Boron SIMS profile HRTEM analysis Leakage characteristics Xj-Rs relationship -HfO 2 capacitor part C-V & I-V characteristics C & I variation with laser -HfO 2 pmosfet part V D -I D characteristics V G -I D characteristics IV. Conclusions
3 Introduction & Motivation ESSDERC 2002 Device Scaling Ultrashallow Junction To increase packing density & operation speed High-k gate dielectric & Ultra-shallow junction Junction for the source and drain Shallow junction to avoid the short channel effect Low sheet resistance to improve current driving capability Requirements for ultrashallow junction High dose ion implantation at low implantation energy Complete activation without significant enhanced diffusion
4 Introduction & Motivation ESSDERC 2002 Doping method Ultrashallow Junction Advantages Low energy ion implantation Plasma immersion ion implant Gas immersion laser doping Solid phase diffusion Anneal & Activation Method Rapid thermal annealing Laser annealing Low temp. & long time anneal Microwave annealing Low cost Low energy & High dose rate Large implant area High throughput Uniform distribution Full activation
5 Introduction & Motivation ESSDERC 2002 High-k dielectric gate oxide The problem of sub-2nm thermal SiO 2 High tunneling leakage current (>10~1000A/cm 2 ) Uniformity issue (thickness variation vs. leakage) P + gate dopant penetration : V th variation Low quality SiO x (<1nm) layer formation High defect density & Low yield Requirements of high-k gate dielectric T ox <1.5nm, leakage current <100mA/cm 2 D it <1x10 11 /cm 2 ev (negligible mobility degradation) Negligible dispersion & hysteresis Reliability and lifetime > 10years Thermal stability
6 Introduction & Motivation ESSDERC 2002 Advantages of HfO 2 High-k dielectric gate oxide High dielectric constant (ε=30) & high bandgap (E g =5.68eV) Thermal stable in contact with Si : H=271kcal/mol Resistance to interface mixing Possibly epitaxial growth on Si (a=5.11å, a si =5.43Å) Can be wet etched by hydrofluoric acid Compatibility with polysilicon Motivation The advantages of plasma doping & laser annealing + the advantages of HfO 2 & metal gate Excellent electrical characteristics without high-k oxide degradation
7 Contents ESSDERC 2002 I. Introduction & Motivation - Ultra-shallow Junction - High-k dielectric gate oxide II.Experimental Procedure -Basic property -p + /n junction diode -HfO 2 capacitor -HfO 2 pmosfet III.Results & Discussion - Ultra-shallow Junction part Hall measurement Boron SIMS profile HRTEM analysis Leakage characteristics Xj-Rs relationship -HfO 2 capacitor part C-V & I-V characteristics C & I variation with laser -HfO 2 pmosfet part V D -I D characteristics V G -I D characteristics IV. Conclusions
8 Experimental Procedure Basic Property ESSDERC 2002 P + /N junction diode N-type SI (100) Standard Cleaning HF dip (100:1) B 2 H 6 plasma doping 500V, 1x10 16 /cm 2 Annealing RTA 900~1000 o C 10s LA 500mJ/cm 2, 1pulse KrF excimer laser FA 300~500 o C 5min (N 2 ) 2000Å thermal oxide Photolithography (active) B 2 H 6 plasma doping Activation Al-1% Si sputter 4000Å Photolithography Postmetallization anneal 450 o C 30min FA (forming)
9 Experimental Procedure ESSDERC 2002 HfO 2 capacitor Hf metal sputter 50W 10sec Ar 5sccm 600 o C 1min RTA for oxidation Photolithography Pt depo. By sputter Lift-off PMA 400 o C 30min (forming) HfO 2 pmosfet Thermal oxide 2000Å HfO 2 depo. & oxidation Al & Al/TaN sputter (4000Å) Gate patterning B 2 H 6 plasma doping Laser annealing 500mJ/cm 2, 1pulse Al-1% Si sputter (5000Å) PMA 400 o C 30min
10 Contents ESSDERC 2002 I. Introduction & Motivation - Ultra-shallow Junction - High-k dielectric gate oxide II.Experimental Procedure -Basic property -p + /n junction diode -HfO 2 capacitor -HfO 2 pmosfet III.Results & Discussion - Ultra-shallow Junction part Hall measurement Boron SIMS profile HRTEM analysis Leakage characteristics Xj-Rs relationship -HfO 2 capacitor part C-V & I-V characteristics C & I variation with laser -HfO 2 pmosfet part V D -I D characteristics V G -I D characteristics IV. Conclusions
11 Results & Discussion ESSDERC 2002 Sheet Resistance & Carrier Concentration Sheet resistance (Ohm/sq.) Control Laser Anneal Laser energy : 500 mj / cm 2 Pulse : 1 Preannealing time : 5min 300 o C 400 o C Preannealing temperature ( o C) 500 o C Carrier Conc. (1x10 15 /cm 2 ) Sheet resistance (Ohm/sq.) Rapid Thermal Anneal RTA temperature 900 o C 950 o C Annealing time (sec) Carrier conc. (x10 14 /cm 2 ) Low sheet resistance and high carrier concentration compared with RTA Compatible sheet resistance with a preannealing temp.
12 Results & Discussion ESSDERC 2002 Boron SIMS depth profiles Laser Anneal Rapid Thermal Anneal Boron Conc. (/cm 3 ) Laser energy : 500 mj / cm 2 Pulse : 1 as implant 300 o C 5min FA (N 2 ) 500 o C 5min FA (N 2 ) No preanneal + LA 300 o C 5min FA (N 2 ) + LA o C 5min FA (N 2 ) + LA Depth (Å) Boron Conc. ( / cm 3 ) as implant 900 o C 10sec RTA 950 o C 10sec RTA o C 30sec RTA 900 o C 1min RTA o C 30sec RTA 950 o C 1min RTA Depth ( A ) Shallower junction depth compared with RTA Decrease of junction depth with a preannealing temp.
13 Results & Discussion ESSDERC 2002 HRTEM Analysis As implant Laser anneal Preanneal + Laser anneal RTA 900 o C 10s As implant defect-rich Only laser anneal cannot remove all defects Preanneal + LA defect-free 900 o C 10s RTA some defects are remained
14 Results & Discussion ESSDERC 2002 Leakage Current Characteristics Laser Anneal Rapid Thermal Anneal Cumulative probability ( % ) Area = 10-4 cm 2 Laser energy : 500mJ/cm 2 Pulse : o C 5min FA (N 2 ) No preannealing Leakage current at -2V ( A ) Cumulative probability (%) 100 Area = 10-4 cm o C 10sec RTA 900 o C 10sec RTA 950 o C 10sec RTA 1E-12 1E-11 1E-10 1E-9 1E-8 Leakage current at -2V (A) More uniform and lower leakage current compared with RTA annealed diode
15 Results & Discussion ESSDERC 2002 Xj Rs Relationship Sheet resistance (Ohm/sq.) Laser annealing 950 o C RTA 900 o C RTA Junction depth (A) The improvement of junction characteristics by excimer laser annealing
16 Contents ESSDERC 2002 I. Introduction & Motivation - Ultra-shallow Junction - High-k dielectric gate oxide II.Experimental Procedure -Basic property -p + /n junction diode -HfO 2 capacitor -HfO 2 pmosfet III.Results & Discussion - Ultra-shallow Junction part Hall measurement Boron SIMS profile HRTEM analysis Leakage characteristics Xj-Rs relationship -HfO 2 capacitor part C-V & I-V characteristics C & I variation with laser -HfO 2 pmosfet part V D -I D characteristics V G -I D characteristics IV. Conclusions
17 Results & Discussion ESSDERC 2002 HfO 2 capacitor C-V & I-V Characteristics Capacitance-Voltage Current-Voltage Capacitance ( F ) 18.0p 15.0p 12.0p 9.0p 6.0p 3.0p 0.0 Al Al / TaN TaN Pt Area : 9 x 10-6 cm 2 Frequency : 1MHz Gate current ( A ) Al / TaN Pt Al TaN Area : 9 x 10-6 cm Gate bias ( V ) Gate bias (V) Using the various electrode, the C-V & I-V characteristics of HfO 2 capacitor were evaluated.
18 Results & Discussion ESSDERC 2002 Capacitance & Leakage current variation -2.5V ( F ) 18.0p 15.0p 12.0p 9.0p 6.0p 3.0p 0.0 Pt Al / TaN Al TaN Leakage current ( A ) TaN Pt Fail Al / TaN Al control Laser energy ( mj / cm 2 ) control Laser energy ( mj / cm 2 ) 700 Pt gradual degradation in capacitance & leakage current Al stable with laser energy, interaction with high-k oxide Al/TaN stable up to 500mJ/cm 2, optimum electrode (capacitance, leakage current, interaction, laser reflection)
19 Results & Discussion ESSDERC 2002 HfO 2 pmosfet V D -I D Charactersitics Darin current ( A ) µ -80.0µ -60.0µ -40.0µ -20.0µ 0.0 Al/TaN electrode PMOSFET W / L = 30 / 20 µm V g = -1.5 V -1.2 V -0.9 V -0.6 V -0.3 V Darin current ( A ) -14.0µ -12.0µ -10.0µ -8.0µ -6.0µ -4.0µ -2.0µ 0.0 PMOSFET Al electrode W / L = 30 / 20 µm V g = -2.2 V -1.9 V -1.6 V -1.3 V -1.0 V Drain bias ( V ) Drain bias ( V ) Compared with Al electrode, Al/TaN electrode pmosfet shows higher drive current
20 Results & Discussion ESSDERC 2002 HfO 2 pmosfet V G -I D Characteristics Al/TaN electrode Al electrode Drain current ( A ) PMOSFET W / L = 30 / 20 µm S. S. = 75 mv / dec V d = -0.5 V Drain Current ( A ) PMOSFET W / L = 30 / 20 µm V d = 0.5V S. S. = 88 mv / dec Gate bias ( V ) Gate bias ( V ) Subthreshold swing Al/TaN electrode : 75mV/dec. Al electrode : 88mV/dec.
21 Conclusions ESSDERC 2002 HfO 2 pmosfets were demonstrated with ultra-shallow junction prepared by plasma doping and excimer laser annealing The junction depth of 20nm and sheet resistance of 230Ω/ can be obtained by preannealing at 500 o C followed by laser annealing at 500mJ/cm 2 Combination with HfO 2 and Al/TaN PMOSFETs fabricated by plasma doping and laser annealing show reasonable I-V characteristics Process compatibility for future sub-0.1um CMOS technology
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