Extending Etch and Deposition Capabilities for Implementation of 3D Packaging of MEMS in Volume Production

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1 Extending Etch and Deposition Capabilities for Implementation of 3D Packaging of MEMS in Volume Production David Butler, VP Product Management & Marketing SPTS Technologies

2 Contents Industry Trends TSV Process Flow Etch TSV Etch Evolution Endpoint Detection Oxide Etching Dielectric CVD Via Last Challenges Managing Outgassing Metallization Conventional & Ionized PVD LT MOCVD Extendibility Conclusions

3 MEMS Market Trends Never a down year in MEMS But module growth more modest: shrinks

4 More Die Per Wafer 2 x 2mm die with 0.1mm separation 200mm 150mm 100mm Most high volume MEMS production now on 200mm ST, Bosch, TSMC, UMC, TowerJazz In transition Silex, X-FAB Still on 150mm Tronics, IMT, Micralyne, Sony 100mm limited mostly to R&D

5 MEMS Drive for Miniaturization iphone Thickness (mm) iphone 3G 3GS 4 4S 5 5S 6 Thinner handsets with MORE functionality: gyros, accelerometers, microphones, cameras and combo chips 0 Accelerometers size dropped from 12 to <1.5mm 2 over 7 years

6 Even Smaller - TSV With TSV >30% reduction in X and Y >80% reduction in resistance CP Hung SEMI TSV Summit 2015 MEMS timing device TSVs between ASIC & MEMS

7 Typical Process Flow for Via Last TSV

8 TSV Etching Evolution 10 x 100µm Sc ~100nm Profile 90 Top ~89µm Base ~49µm Profile ~63 75 x 150µm Sc ~200nm Profile 91 8 x 180µm Sc <200nm 50 x 130µm Sc ~500nm Profile 92 Top ~85µm Base ~47µm Profile ~77 Apparent wall curvature due to cleave 10 x 100µm Sc ~70nm Profile 90 4 x 160µm Sc <50nm Continuous process SF 6 + passivant Switched (Bosch) process SF 6 /C 4 F 8 cycling Required Via shape depends on subsequent deposition technology

9 End-point Detection Tapered Etches (Reflectance) Vertical etches (Claritas) Si Si Variation due to differing grind thicknesses of Si EPD = Better reproducibility & higher yield

10 Oxide Etching for TSV Base layer etching within TSV PR Si TSV ~400 x 400µm Oxide multi-layer ~9µm Oxide etch Oxide remaining 1-2µm Si Apparent wall curvature due to cleave Oxide 6.3µm partial etch

11 Oxide Etching for TSV Spacer etch of TSV liner Denotes oxide layer 70 x 70µm TSV 20 x 120µm TSV OES end-point detection Oxide removed at Via base Oxide etched

12 LT PECVD Challenges PECVD System Temperature control wafer and chamber Substrate compatibility SOS, SOG Outgassing substrates the need for degas Film Engineering Electrical isolation I L & V bd Stability esp. LT TEOS SiO Sidewall coverage void-free Stress tuning & stability Diffusion barrier properties Integration Interfacial adhesion to Si, SiO and inter-stack layer CMP compatibility E & H Bow compensation Challenging to achieve all this with wafer temperature <190 C

13 Delta fxp LT PECVD Choice of chemistries for TSV liner Silane for sloped TSV and vertical TSV with AR < 2:1 TEOS for vertical TSV with AR > 2:1 Ammonia-free SiN diffusion barrier Prevent Cu diffusion into Si Stable Leakage Current Stable Stress

14 PECVD SiO in Sloped Sidewall TSV Top Corner Silane-based SiO at 150 C Excellent adhesion Excellent electrical properties No delamination after wafer dicing Volume production since mm SoG CIS Base Linear Ramp Voltage Stress IMAPS 2010

15 TEOS SiO in Vertical TSV SiN, SiO & TEOS SiO with common chamber hardware SiN barriers SiO isolation All films 200 C Aspect ratios 10:1 LT TEOS SiO in 10x80 µm TSV TEOS SiO liner in 40µm x 125µm TSV Extensive LT SiN and SiO Production Experience

16 Managing Out-Gassing in PECVD Minimize out-gassing to preserve PECVD film quality Batch process chamber Long degas times with high system throughput Without Degas Step With Degas Step dc bias (V) dc bias (V) Unstable Plasma Scrap Wafer!

17 Conventional PVD Al for Low AR TSV Tapered Etch Trench Thinned Si bonded to Taped Glass 4 µm Al [4%Cu] Deposition Wafer Centre Thickness, μm Step Cov. % Field % depth % depth Bottom corner Base

18 Ionized PVD Cu Seed for HAR 50 µm x 250 µm, AR 5 Integrated SPTS process flow Rapier DRIE Delta SiN DCVD Sigma Ti barrier Sigma Cu seed 10 µm x 100 µm AR µm x 300 µm AR 15

19 Extendibility LT MOCVD TiN Low temp MOCVD TiN FEOL MOCVD TiN 3 µm x 15 µm TSV Barrier: 75 nm C3M MOCVD TiN, 200 C Minimum sidewall coverage 46%

20 Versalis fxp: Reduced Cost R&D Low cost R&D solution Multiple processes on one platform Example configuration Rapier for Si & SiO etch 1x APM PECVD oxide & nitride 1x AHF ionized PVD barrier 1x AHF ionized PVD Cu System capability Etch deep Si via by Bosch process Etch oxide hard-mask and liner PECVD of low temperature oxide Ionized PVD of barrier & Cu seed Via reveal Si and dielectric etches APM PECVD SiO/SiN Rapier Si/SiO etch PVD Ti Degas PVD Cu Versalis reduces capex and footprint Sputter Etch

21 Summary Via-last TSV for low I/O is ramping Image sensors, MEMS, RFIC, PMIC DRIE Si and SiO etch TSV etch and base oxide liner removal Low temperature PECVD SiO liners Silane and TEOS based Tapered TSV to high aspect ratio Range of metallization options PVD ionized PVD low temp MOCVD Versalis fxp multi-tech cluster system Reduced initial capital costs

22 THANK YOU QUESTIONS?

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