EE 245: Introduction to MEMS Lecture 7m1: Lithography, Etching, & Doping CTN 9/18/ Regents of the University of California

Size: px
Start display at page:

Download "EE 245: Introduction to MEMS Lecture 7m1: Lithography, Etching, & Doping CTN 9/18/ Regents of the University of California"

Transcription

1 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Anisotropic Wet Etching Anisotropic Wet Etching (cont.) Anisotropic etches also available for single crystal Can get the following Orientation-dependent etching <111>-plane more densely packed than <100>-plane Slower E.R. Faster E.R. in some solvents 54.7 <111> <100> O (on a <100> - wafer) One such solvent KOH + isopropyl alcohol (e.g., 3.4 wt% KOH, 13.3 wt% isopropyl alcohol, 63 wt% H O) <110> <111> O E.R. <100> = 100 x E.R. <111> (on a <110> - wafer) Quite anisotropic! EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 30 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 31 licon Wafers licon Crystallography [Maluf] EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 3 Miller Indices (h k l) Planes Reciprocal of plane intercepts with axes e.g., for (110), intercepts (x,y,z) = (1,1, ); reciprocals (1,1,0) (110) (unique), {family} Directions One endpoint of origin [unique], <family> EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

2 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Determining Angles Between Planes licon Crystal Origami The angle between vectors [abc] and [xyz] is given by ( a, b, c) ( x, y, ) cosθ ax + by + cz = z ax + by + cz θ a b c x y z = cos 1,,,,, a, b, c x, y, z For {100} and {110} 45 o For {100} and {111} o For {110} and {111} 35.6 o, 90 o, and o ( )( ) ( ) ( ) EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 34 licon fold-up cube Adapted from Profs. Kris Pister and Jack Judy Print onto transparency Assemble inside out Visualize crystal plane orientations, intersections, and directions [Judy, UCLA] EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 35 Wet Etching O O + 6HF H + F 6 + H O Generally used to clear out residual oxides from contacts bubble 300nm HF nt Problem Contact hole is so thin that surface tensions don t allow the HF to get into the contact Generally the case for VLSI circuits oxide native oxide can get this just by exposing to air 1-nm-thick Solution add a surfactant (e.g., Triton X) to the BHF before the contact clear etch 1. Improves the ability of HF to wet the surface (hence, get into the contact). Suppresses the formation of etch by-products, which otherwise can block further reaction if by-products get caught in the contact EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 36 More Wet Etch Chemistries Wet etching silicon nitride Use hot phosphoric acid 85% phosphoric 180 o C Etch rate ~ 10 nm/min (quite slow) Problem lifted during such etching Solution use O as an etch mask (E.R. ~.5 nm/min) A hassle dry etch processes more common than wet Wet etchining aluminum Typical etch solution composition 80% phoshporic acid, 5% nitric acid, 5% acetic acid, 10% water (H PO 4 ) (HNO 3 ) (CH 3 COOH) (H O) (1) Forms Al O 3 (aluminum oxide) () Dissolves the Al O 3 Problem H gas bubbles adhere firmlly to the surface delay the etch need a 10-50% overetch time Solution mechanical agitation, periodic removal of wafers from etching solution EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 37

3 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Wet Etch Rates (f/ K. Williams) Film Etch Chemistries For some popular films EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 38 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 39 Dry Etching Dry Etching Physical sputtering Plasma etching Reactive ion etching ~ All based upon plasma processes. RF (also, could be μwave) Develop (-) bias) (+) ions generated by inelastic collisions with energetic e -1 s Get avalanche effect because more e -1 s come out as each ion is generated Plasma (partially ionized gas composed of ions, e - s, and highly reactive neutral species) E-field wafer Develops (+) charge to compensate for (+) ions will be accelerated to the wafer EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 40 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

4 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Physical Sputtering (Ion Milling) Bombard substrate w/ energetic ions etching via physical momentum transfer Give ions energy and directionality using E-fields Highly directional very anisotropic ions plasma film Steep vertical wall EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 4 etched down to here Once through the film, the etch will start barreling through the Problems With Ion Milling EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 43 film 1. or other masking material etched at almost the same rate as the film to be etched very poor selectivity!. Ejected species not inherently volatile get redeposition non-uniform etch grass! Because of these problems, ion milling is not used often (very rare) Plasma Etching Plasma (gas glow discharge) creates reactive species that chemically react w/ the film in question Result much better selectivity, but get an isotropic etch Plasma Etching Mechanism 1. Reactive species generated in a plasma.. Reactive species diffuse to the surface of material to be etched. 3. Species adsorbed on the surface. 4. Chemical reaction. 5. By-product desorbed from surface. 6. Desorbed species diffuse into the bulk of the gas 3 4 Film to be etched MOST IMPORTANT STEP! (determines whether plasma etching is possible or not.) EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/ plasma 5 6 Ex Polysilicon Etching w/ CF 4 and O CF 4 CF 4+ + CF 3+ + CF + + CF + + F + + F 0 + CF + + plasma Neutral radical (highly reactive!) CF 6, F 4 e - + CF 4 CF 3 + F + e - both volatile dry etching is possible. F is the dominant reactant but it can t be given a direction thus, get isotropic etch! isotropic component F 0 F 0 F 4 poly EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

5 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Ex Polysilicon Etching w/ CF 4 and O isotropic component F 0 F 0 F 4 poly Problems 1. Isotropic etching. Formation of polymer because of C in CF 4 Solution add O to remove the polymer (but note that this reduces the selectivity, S poly/ ) Solution Use Reactive Ion Etching (RIE) Reactive Ion Etching (RIE) Use ion bombardment to aid and enhance reactive etching in a particular direction Result directional, anisotropic etching! RIE is somewhat of a misnomer It s not ions that react rather, it s still the neutral species that dominate reaction Ions just enhance reaction of these neutral radicals in a specific direction Two principle postulated mechanisms behind RIE 1. Surface damage mechanism. Surface inhibitor mechanism EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 46 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 47 RIE Surface Damage Mechanism RIE Surface Inhibitor Mechanism reactive radical plasma film Enhanced reaction over Relatively high energy impinging ions (>50 ev) produce lattice damage at surface Reaction at these damaged sites is enhanced compared to reactions at undamaged areas reactive radical film plasma + (+) ions breakup the polymer layer + + get reaction Non-volatile polymer layers are a product of reaction They are removed by high energy directional ions on the horizontal surface, but not removed from sidewalls no reaction Result E.R. at surface >> E.R. on sidewalls Result surface >> E.R. on sidewalls EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 48 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

6 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Deep Reactive-Ion Etching (DRIE) DRIE Issues Etch Rate Variance The Bosch process Inductively-coupled plasma Etch Rate μm/min Two main cycles in the etch Etch cycle (5-15 s) SF 6 (SF x+ ) etches Deposition cycle (5-15 s) C 4 F 8 deposits fluorocarbon protective polymer (CF - ) n Etch mask selectivity O ~ 001 Photoresist ~ 1001 Issue finite sidewall roughness scalloping < 50 nm dewall angle 90 o ± o Etch rate is diffusion-limited and drops for narrow trenches Adjust mask layout to eliminate large disparities Adjust process parameters (slow down the etch rate to that governed by the slowest feature) Etch Etch rate rate decreases with with trench trench width width EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 50 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 51 Doping of Semiconductors Semiconductor Doping Semiconductors are not intrinsically conductive To make them conductive, replace silicon atoms in the lattice with dopant atoms that have valence bands with fewer or more e - s than the 4 of If more e - s, then the dopant is a donor P, As The extra e - is effectively released from the bonded atoms to join a cloud of free e - s, free to move like e - s in a metal Extra free e -.. P. Dope P. The larger the # of donor atoms, the larger the # of free e - s the higher the conductivity EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 5 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

7 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Doping of Semiconductors (cont.) Conductivity Equation conductivity σ = qμ n n + qμ electron mobility electron density charge magnitude on an electron If fewer e - s, then the dopant is an acceptor B.. B. Dope Lack of an e - = hole = h + When e - s move into h + s, the h + s effectively move in the opposite direction a h + is a mobile (+) charge carrier EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 54 p p hole mobility hole density B. hole. Ion Implantation EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 55 Ion Implantation Method by which dopants can be introduced in silicon to make the silicon conductive, and for transistor devices, to form, e.g., pn-junctions, source/drain junctions, The basic process Control current & time to control the dose. Result of I/I B+ B+ B+ B+ B+ B-B-B-Bx EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 56 Charged dopant accelerated to high energy by an E-Field (e.g., 100 kev) Masking material (could be, could be oxide, etc.) Depth determined by energy & type of dopant Ion Implantation (cont.) Result of I/I Ion collides with atoms and interacts with e - s in the lattice all of which slow it down and eventually stop it. B B EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 57 Damage layer at top becomes amorphous B not in the lattice, so it s not electrically active. High Temperature Anneal (also, usually do a drive-in diffusion) ( C) Now B in the lattice & electrically active! (serves as dopant) This is a statistical process implanted impurity profile can be approximated by a Gaussian distribution. 7

8 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Impurity concentration One std. dev. away 0.61N p std. dev. away 0,14N p 3 std. dev. away 0.11N p Rp ΔR p Δ Δ Statistical Modeling of I/I N(x) N p ΔR p ΔR p Unlucky ions Avg. ions R p ΔR p ΔR p Lucky ions Distance into material, x Projected range = avg. distance on ion trends before stopping Straggle = std. deviation characterizing the spread of the distribution. EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 58 Mathematically Area under the impurity distribution curve Analytical Modeling for I/I N( x) N exp ( x R ) ( ) p ΔRp = p Implanted Dose = Q = N ( x) dx [ ions / cm ] Q = π N p ΔR p EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/ For an implant completely contained within the Assuming the peak is in the silicon (putting it in one-sided diffusion form) So we can track the dopant front during a D I = Q subsequent diffusion step. D ( x R ) ( I p ΔRp ) N( x) = exp, where ( Dt) eff = π ( Dt) ( ΔRp ) eff, R p Roughly proportional to ion energy R p α ion energy (some nonlinearties) Figure 6.1 I/I Range Graphs R p is a function of the energy of the ion and atomic number of the ion and target material Lindhand, Scharff and Schiott (LSS) Theory Assumes implantation into amorphous material, i.e, atoms of the target material are randomly positioned Yields the curves of Fig. 6.1 and 6. For a given energy, lighter elements strike with higher velocity and penetrate more deeply EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 60 Figure 6. I/I Straggle Graphs Results for and O surfaces are virtually identical so we can use these curves for both EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

9 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Diffusion in licon Movement of dopants within the silicon at high temperatures Three mechanisms (in ) Diffusion EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 6 Substitutional Diffusion Interstitialcy Diffusion Impurity moves along Impurity atom vacancies in the lattice replaces a atom in the lattice Substitutes for a atom in the lattice atom displaced to an interstitial site Interstitial Diffusion Impurity atoms jump from one interstitial site to another Get rapid diffusion Hard to control Impurity not in lattice so not electrically active EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 63 Diffusion in Polysilicon In polysilicon, still get diffusion into the crystals, but get more and faster diffusion through grain boundaries Result overall faster diffusion than in silicon Basic Process for Selective Doping 1. Introduce dopants (introduce a fixed dose Q of dopants) (i) Ion implantation (ii) Predeposition. Drive in dopants to the desired depth High temperature > 900 o C in N or N /O Result dopants Fast diffusion through grain boundaries Regular diffusion into crystals Drive-in In effect, larger surface area allows much faster volumetric diffusion EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 64 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

10 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Predeposition Furnace-tube system using solid, liquid, or gaseous dopant sources Used to introduced a controlled amount of dopants Unfortunately, not very well controlled Dose (Q) range ± 0% For ref w/ ion implantation ± 1% (larger range & more accurate) Example Boron predeposition Gases O + B H 6 + carrier gas diborane (Inert gas e.g., N or Ar) O, B H 6 Furnace tube boat wafer Predeposition Temp C EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 66 Basic Procedure Ex Boron Predeposition O O BBBBBB 1. Deposit B O 3 glass Difficult to control dose Q, because it s heavily dependent on partial pressure of B H 6 gas flow this is difficult to control itself get only 10% uniformity O diffusion barrier (masks out dopants). B diffuses from B O 3 Furnace tube cross-section Less B concentration EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 67 Ex Boron Predeposition (cont.) General Comments on Predeposition For better uniformity, use solid source Furnace tube wafer Boron/Nitride wafer % uniformity EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 68 Reactions B H 6 + 3O 3H O + B O 3 + O O Higher doses only Q = cm - (I/I is ) Dose not well controlled ± 0% (I/I can get ± 1%) Uniformity is not good ± 10% w/ gas source ± % w/ solid source Max. conc. possible limited by solid solubility Limited to ~10 0 cm -3 No limit for I/I you force it in here! For these reasons, I/I is usually the preferred method for introduction of dopants in transistor devices But I/I is not necessarily the best choice for MEMS I/I cannot dope the underside of a suspended beam I/I yields one-sided doping introduces unbalanced stress warping of structures I/I can do physical damage problem if annealing is not permitted Thus, predeposition is often preferred when doping MEMS EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

11 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Diffusion Modeling Diffusion Modeling (cont.) EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 70 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 71 Diffusion Modeling (Predeposition) Diffusion Modeling (Limited Source) EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 7 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

12 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Diffusion Modeling (Limited Source) Two-Step Diffusion Two step diffusion procedure Step 1 predeposition (i.e., constant source diffusion) Step drive-in diffusion (i.e., limited source diffusion) For processes where there is both a predeposition and a drive-in diffusion, the final profile type (i.e., complementary error function or Gaussian) is determined by which has the much greater Dt product (Dt) predep»(dt) drive-in impurity profile is complementary error function (Dt) drive-in»(dt) predep impurity profile is Gaussian (which is usually the case) EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 74 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 75 Successive Diffusions The Diffusion Coefficient For actual processes, the junction/diffusion formation is only one of many high temperature steps, each of which contributes to the final junction profile Typical overall process 1. Selective doping Implant effective (Dt) 1 = (ΔR p ) / (Gaussian) Drive-in/activation D t. Other high temperature steps (eg., oxidation, reflow, deposition) D 3 t 3, D 4 t 4, Each has their own Dt product 3. Then, to find the final profile, use ( Dt) = Diti tot in the Gaussian distribution expression. i E = A D Do exp kt (as usual, an Arrhenius relationship) EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 76 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

13 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping Diffusion Coefficient Graphs Metallurgical Junction Depth, x j Substitutional & Interstitialcy Diffusers Interstitial Diffusers Note the much higher diffusion coeffs. than for substitutional x j = point at which diffused impurity profile intersects the background concentration, N B Log[N(x)] N O e.g., p-type Gaussian e.g., n-type N O -N B Log[N(x)-N B ] Net impurity conc. p-type region N B N B n-type region x j x = distance f/ surface x j x = distance f/ surface EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 78 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 79 Expressions for x j Assuming a Gaussian dopant profile (the most common case) x N = Dt j ( x j, t) = No exp N B x j = N Dt ln N o B Sheet Resistance Sheet resistance provides a simple way to determine the resistance of a given conductive trace by merely counting the number of effective squares Definition For a complementary error function profile x N = Dt j ( x j, t) = Noerfc N B x j = Dterfc 1 N N B o What if the trace is non-uniform? (e.g., a corner, contains a contact, etc.) EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 80 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

14 EE 45 Introduction to MEMS Lecture 7m1 Lithography, Etching, & Doping # Squares From Non-Uniform Traces Sheet Resistance of a Diffused Junction For diffused layers Sheet resistance R s x ( ) 1 ( ) 1 j x j σ x dx = qμn x dx o o ρ = = x j Effective resistivity Majority carrier mobility Net impurity concentration EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 8 [extrinsic material] This expression neglects depletion of carriers near the junction, x j thus, this gives a slightly lower value of resistance than actual Above expression was evaluated by Irvin and is plotted in Irvin s curves on next few slides Illuminates the dependence of R s on x j, N o (the surface concentration), and N B (the substrate background conc.) EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 83 Irvin s Curves (for n-type diffusion) Irvin s Curves (for p-type diffusion) Example. p-type Given N B = 3x10 16 cm -3 N o = 1.1x10 18 cm -3 (n-type Gaussian) x j =.77 μm Can determine these given known predep. and drive conditions Determine the R s. Example. n-type Given N B = 3x10 16 cm -3 N o = 1.1x10 18 cm -3 (p-type Gaussian) x j =.77 μm Can determine these given known predep. and drive conditions Determine the R s. EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/09 84 EE C45 Introduction to MEMS Design LecM 4 C. Nguyen 8/0/

EE C245 ME C218 Introduction to MEMS Design Fall 2009

EE C245 ME C218 Introduction to MEMS Design Fall 2009 EE C245 ME C218 Introduction to MEMS Design Fall 2009 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture Module

More information

EE C247B ME C218 Introduction to MEMS Design Spring 2017

EE C247B ME C218 Introduction to MEMS Design Spring 2017 EE247B/ME218 Introduction to MEMS Design Module 4 Lithography, Etching, & Doping EE C247B ME C218 Introduction to MEMS Design Spring 2017 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer

More information

Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very

Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very high voltages (10-600 KeV) Use analyzer to selection charge/mass

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2011

EE C245 ME C218 Introduction to MEMS Design Fall 2011 Lecture Outline EE C245 ME C218 Introduction to MEMS Design Fall 2011 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2007

EE C245 ME C218 Introduction to MEMS Design Fall 2007 EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 10: Bulk

More information

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline: ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline: Fabrication of p-n junctions Contact Potential Things you should know when you leave Key Questions What are the necessary steps to fabricate

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2010

EE C245 ME C218 Introduction to MEMS Design Fall 2010 Lecture Outline EE C245 ME C218 Introduction to MEMS Design Fall 2010 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720

More information

Fabrication Technology, Part I

Fabrication Technology, Part I EEL5225: Principles of MEMS Transducers (Fall 2003) Fabrication Technology, Part I Agenda: Oxidation, layer deposition (last lecture) Lithography Pattern Transfer (etching) Impurity Doping Reading: Senturia,

More information

Czochralski Crystal Growth

Czochralski Crystal Growth Czochralski Crystal Growth Crystal Pulling Crystal Ingots Shaping and Polishing 300 mm wafer 1 2 Advantage of larger diameter wafers Wafer area larger Chip area larger 3 4 Large-Diameter Wafer Handling

More information

Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +,

Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +, Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +, 2+ or 3+ ionization) Use analyzer to selection charge/mass

More information

1. Introduction. What is implantation? Advantages

1. Introduction. What is implantation? Advantages Ion implantation Contents 1. Introduction 2. Ion range 3. implantation profiles 4. ion channeling 5. ion implantation-induced damage 6. annealing behavior of the damage 7. process consideration 8. comparison

More information

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley Microstructure of Electronic Materials Amorphous materials Single-Crystal Material 1 The Si Atom The Si Crystal diamond structure High-performance semiconductor devices require defect-free crystals 2 Crystallographic

More information

3. Photolithography, patterning and doping techniques. KNU Seminar Course 2015 Robert Mroczyński

3. Photolithography, patterning and doping techniques. KNU Seminar Course 2015 Robert Mroczyński 3. Photolithography, patterning and doping techniques KNU Seminar Course 2015 Robert Mroczyński Critical technology processes Photolithography The aim of this process is to transfer (in the most accurate

More information

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing 3. Conventional licon Processing Micromachining, Microfabrication. EE 5344 Introduction to MEMS CHAPTER 3 Conventional Processing Why silicon? Abundant, cheap, easy to process. licon planar Integrated

More information

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica Microelettronica Planar Technology for Silicon Integrated Circuits Fabrication 26/02/2017 A. Neviani - Microelettronica Introduction Simplified crosssection of an nmosfet and a pmosfet Simplified crosssection

More information

Chemical Vapor Deposition

Chemical Vapor Deposition Chemical Vapor Deposition ESS4810 Lecture Fall 2010 Introduction Chemical vapor deposition (CVD) forms thin films on the surface of a substrate by thermal decomposition and/or reaction of gas compounds

More information

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook: HOMEWORK 4 and 5 March 15, 2009 Homework is due on Monday March 30, 2009 in Class. Chapter 7 Answer the following questions from the Course Textbook: 7.2, 7.3, 7.4, 7.5, 7.6*, 7.7, 7.9*, 7.10*, 7.16, 7.17*,

More information

Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +,

Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +, Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +, 2+ or 3+ ionization) Use analyzer to selection charge/mass

More information

CHAPTER 8: Diffusion. Chapter 8

CHAPTER 8: Diffusion. Chapter 8 1 CHAPTER 8: Diffusion Diffusion and ion implantation are the two key processes to introduce a controlled amount of dopants into semiconductors and to alter the conductivity type. Figure 8.1 compares these

More information

Changing the Dopant Concentration. Diffusion Doping Ion Implantation

Changing the Dopant Concentration. Diffusion Doping Ion Implantation Changing the Dopant Concentration Diffusion Doping Ion Implantation Step 11 The photoresist is removed with solvent leaving a ridge of polysilicon (the transistor's gate), which rises above the silicon

More information

Most semiconductor devices contain at least one junction between p-type and n-type material. These p-n junctions are fundamental to the performance

Most semiconductor devices contain at least one junction between p-type and n-type material. These p-n junctions are fundamental to the performance Ch. 5: p-n Junction Most semiconductor devices contain at least one junction between p-type and n-type material. These p-n junctions are fundamental to the performance of functions such as rectification,

More information

Midterm evaluations. Nov. 9, J/3.155J 1

Midterm evaluations. Nov. 9, J/3.155J 1 Midterm evaluations What learning activities were found most helpful Example problems, case studies (5); graphs (good for extracting useful info) (4); Good interaction (2); Good lecture notes, slides (2);

More information

MEMS Fabrication I : Process Flows and Bulk Micromachining

MEMS Fabrication I : Process Flows and Bulk Micromachining MEMS Fabrication I : Process Flows and Bulk Micromachining Dr. Thara Srinivasan Lecture 2 Picture credit: Alien Technology Lecture Outline Reading Reader is in! (at South side Copy Central) Kovacs, Bulk

More information

Chapter 3 Silicon Device Fabrication Technology

Chapter 3 Silicon Device Fabrication Technology Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale

More information

Graduate Student Presentations

Graduate Student Presentations Graduate Student Presentations Dang, Huong Chip packaging March 27 Call, Nathan Thin film transistors/ liquid crystal displays April 4 Feldman, Ari Optical computing April 11 Guerassio, Ian Self-assembly

More information

Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference

Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference Etching Etching Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between 2 materials Need strong selectivity from masking

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2010

EE C245 ME C218 Introduction to MEMS Design Fall 2010 EE C245 ME C218 Introduction to MEMS Design Fall 2010 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture EE C245:

More information

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing ELEC 3908, Physical Electronics, Lecture 4 Basic Integrated Circuit Processing Lecture Outline Details of the physical structure of devices will be very important in developing models for electrical behavior

More information

EE 143 FINAL EXAM NAME C. Nguyen May 10, Signature:

EE 143 FINAL EXAM NAME C. Nguyen May 10, Signature: INSTRUCTIONS Read all of the instructions and all of the questions before beginning the exam. There are 5 problems on this Final Exam, totaling 143 points. The tentative credit for each part is given to

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)

More information

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation. Figure 2.1 (p. 58) Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) selective oxide removal, (c) deposition of dopant atoms on wafer, (d) diffusion of dopant atoms into exposed

More information

MEMS Fabrication. Beyond Integrated Circuits. MEMS Basic Concepts

MEMS Fabrication. Beyond Integrated Circuits. MEMS Basic Concepts MEMS Fabrication Beyond Integrated Circuits MEMS Basic Concepts Uses integrated circuit fabrication techniques to make mechanical as well as electrical components on a single chip. Small size 1µm 1mm Typically

More information

Problem 1 Lab Questions ( 20 points total)

Problem 1 Lab Questions ( 20 points total) Problem 1 Lab Questions ( 20 points total) (a) (3 points ) In our EE143 lab, we use Phosphorus for the source and drain diffusion. However, most advanced processes use Arsenic. What is the advantage of

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

Process Flow in Cross Sections

Process Flow in Cross Sections Process Flow in Cross Sections Process (simplified) 0. Clean wafer in nasty acids (HF, HNO 3, H 2 SO 4,...) --> wear gloves! 1. Grow 500 nm of SiO 2 (by putting the wafer in a furnace with O 2 2. Coat

More information

Doping and Oxidation

Doping and Oxidation Technische Universität Graz Institute of Solid State Physics Doping and Oxidation Franssila: Chapters 13,14, 15 Peter Hadley Technische Universität Graz Institute of Solid State Physics Doping Add donors

More information

MICROCHIP MANUFACTURING by S. Wolf

MICROCHIP MANUFACTURING by S. Wolf MICROCHIP MANUFACTURING by S. Wolf Chapter 22 DRY-ETCHING for ULSI APPLICATIONS 2004 by LATTICE PRESS CHAPTER 22 - CONTENTS Types of Dry-Etching Processes The Physics & Chemistry of Plasma-Etching Etching

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2011

EE C245 ME C218 Introduction to MEMS Design Fall 2011 Lecture Outline EE C245 ME C218 Introduction to MEMS Design Fall 2011 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720

More information

Temperature Scales. Questions. Temperature Conversions 7/21/2010. EE580 Solar Cells Todd J. Kaiser. Thermally Activated Processes

Temperature Scales. Questions. Temperature Conversions 7/21/2010. EE580 Solar Cells Todd J. Kaiser. Thermally Activated Processes 7/1/010 EE80 Solar Cells Todd J. Kaiser Flow of Wafer in Fabrication Lecture 0 Microfabrication A combination of Applied Chemistry, Physics and ptics Thermal Processes Diffusion & xidation Photolithograpy

More information

Make sure the exam paper has 9 pages total (including cover page)

Make sure the exam paper has 9 pages total (including cover page) UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2010 EE143 Midterm Exam #2 Family Name First name SID Signature Solution Make sure the exam

More information

EE 330 Lecture 12. Devices in Semiconductor Processes

EE 330 Lecture 12. Devices in Semiconductor Processes EE 330 Lecture 12 Devices in Semiconductor Processes Review from Lecture 9 Copper Interconnects Limitations of Aluminum Interconnects Electromigration Conductivity not real high Relevant Key Properties

More information

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi

More information

Fabrication Technology

Fabrication Technology Fabrication Technology By B.G.Balagangadhar Department of Electronics and Communication Ghousia College of Engineering, Ramanagaram 1 OUTLINE Introduction Why Silicon The purity of Silicon Czochralski

More information

3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005

3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005 3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005 1) This is an open book, take-home quiz. You are not to consult with other class members or anyone else. You may discuss the

More information

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in Chapter 5 PROCESSING OF DEVICES A discussion of crystal growth, lithography, etching, doping, and device structures is presented in the following overview gures. SEMICONDUCTOR DEVICE PROCESSING: AN OVERVIEW

More information

Today s Class. Materials for MEMS

Today s Class. Materials for MEMS Lecture 2: VLSI-based Fabrication for MEMS: Fundamentals Prasanna S. Gandhi Assistant Professor, Department of Mechanical Engineering, Indian Institute of Technology, Bombay, Recap: Last Class What is

More information

Atomic Layer Deposition(ALD)

Atomic Layer Deposition(ALD) Atomic Layer Deposition(ALD) AlO x for diffusion barriers OLED displays http://en.wikipedia.org/wiki/atomic_layer_deposition#/media/file:ald_schematics.jpg Lam s market-leading ALTUS systems combine CVD

More information

Semiconductor Manufacturing Process 10/11/2005

Semiconductor Manufacturing Process 10/11/2005 Semiconductor Manufacturing Process 10/11/2005 Photolithography Oxidation CVD PVD Photolithography The purpose of photolithography is to imprint the desired pattern of a micro component on a substrate,

More information

Chapter 5. UEEP2613 Microelectronic Fabrication. Diffusion

Chapter 5. UEEP2613 Microelectronic Fabrication. Diffusion Chapter 5 UEEP613 Microelectronic Fabrication Diffusion Prepared by Dr. Lim Soo King 4 Jun 01 Chapter 5 Diffusion...131 5.0 Introduction... 131 5.1 Model of Diffusion in Solid... 133 5. Fick s Diffusion

More information

Review of CMOS Processing Technology

Review of CMOS Processing Technology - Scaling and Integration Moore s Law Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from

More information

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB Fabrication Process Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation 1 Fabrication- CMOS Process Starting Material Preparation 1. Produce Metallurgical Grade Silicon

More information

VLSI. Lecture 1. Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University. Based on slides of David Money Harris

VLSI. Lecture 1. Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University. Based on slides of David Money Harris VLSI Lecture 1 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University Based on slides of David Money Harris Goals of This Course Learn the principles of VLSI design Learn to design

More information

Section 4: Thermal Oxidation. Jaeger Chapter 3. EE143 - Ali Javey

Section 4: Thermal Oxidation. Jaeger Chapter 3. EE143 - Ali Javey Section 4: Thermal Oxidation Jaeger Chapter 3 Properties of O Thermal O is amorphous. Weight Density =.0 gm/cm 3 Molecular Density =.3E molecules/cm 3 O Crystalline O [Quartz] =.65 gm/cm 3 (1) Excellent

More information

ME 189 Microsystems Design and Manufacture. Chapter 9. Micromanufacturing

ME 189 Microsystems Design and Manufacture. Chapter 9. Micromanufacturing ME 189 Microsystems Design and Manufacture Chapter 9 Micromanufacturing This chapter will offer an overview of the application of the various fabrication techniques described in Chapter 8 in the manufacturing

More information

CTN 10/1/09. EE 245: Introduction to MEMS Lecture 11: Bulk Micromachining. Copyright 2009 Regents of the University of California

CTN 10/1/09. EE 245: Introduction to MEMS Lecture 11: Bulk Micromachining. Copyright 2009 Regents of the University of California MUMPS: MultiUser MEMS ProcesS Foundry MEMS: The MUMPS Process Originally created by the Microelectronics Center of North Carolina (MCNC) now owned by MEMSCAP in France Three-level polysilicon surface micromachining

More information

EE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects

EE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects EE 330 Lecture 8 IC Fabrication Technology Part II - Oxidation - Epitaxy - Polysilicon - Interconnects Review from Last Time MOS Transistor Bulk Source Gate Drain p-channel MOSFET Lightly-doped n-type

More information

Silicon Manufacturing

Silicon Manufacturing Silicon Manufacturing Group Members Young Soon Song Nghia Nguyen Kei Wong Eyad Fanous Hanna Kim Steven Hsu th Fundamental Processing Steps 1.Silicon Manufacturing a) Czochralski method. b) Wafer Manufacturing

More information

CMOS VLSI Design. Introduction. All materials are from the textbook Weste and Harris, 3 rd Edition CMOS VLSI DESIGN. Introduction

CMOS VLSI Design. Introduction. All materials are from the textbook Weste and Harris, 3 rd Edition CMOS VLSI DESIGN. Introduction CMOS VLSI Design Introduction ll materials are from the textbook Weste and Harris, 3 rd Edition CMOS VLSI DESIGN Introduction Chapter previews the entire field, subsequent chapters elaborate on specific

More information

Regents of the University of California

Regents of the University of California Surface-Micromachining Process Flow Photoresist Sacrificial Oxide Structural Polysilcon Deposit sacrificial PSG: Target = 2 m 1 hr. 40 min. LPCVD @450 o C Densify the PSG Anneal @950 o C for 30 min. Lithography

More information

Chapter 3 CMOS processing technology

Chapter 3 CMOS processing technology Chapter 3 CMOS processing technology (How to make a CMOS?) Si + impurity acceptors(p-type) donors (n-type) p-type + n-type => pn junction (I-V) 3.1.1 (Wafer) Wafer = A disk of silicon (0.25 mm - 1 mm thick),

More information

ECE520 VLSI Design. Lecture 7: CMOS Manufacturing Process. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 7: CMOS Manufacturing Process. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 7: CMOS Manufacturing Process Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last

More information

ECE321 Electronics I

ECE321 Electronics I ECE321 Electronics I Lecture 19: CMOS Fabrication Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 Miller Effect Interconnect

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 3D Perspective 2 3 Fabrication

More information

Lect. 2: Basics of Si Technology

Lect. 2: Basics of Si Technology Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from fractions of nanometer to several micro-meters

More information

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009 Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology

More information

EELE408 Photovoltaics Lecture 02: Silicon Processing

EELE408 Photovoltaics Lecture 02: Silicon Processing EELE408 Photovoltaics Lecture 0: licon Processing Dr. Todd J. Kaiser tjkaiser@ece.montana.edu Department of Electrical and Computer Engineering Montana State University - Bozeman The Fabrication Process

More information

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS Contents: VI Sem ECE 06EC63: Analog and Mixed Mode VLSI Design PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS 1. Introduction 2. CMOS Fabrication 3. Simplified View of Fabrication Process 3.1 Alternative

More information

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant substrate Creates latch up protection for CMOS Buried Epi

More information

EE 330 Lecture 9. IC Fabrication Technology Part 2

EE 330 Lecture 9. IC Fabrication Technology Part 2 EE 330 Lecture 9 IC Fabrication Technology Part 2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this

More information

Section 4: Thermal Oxidation. Jaeger Chapter 3

Section 4: Thermal Oxidation. Jaeger Chapter 3 Section 4: Thermal Oxidation Jaeger Chapter 3 Properties of O Thermal O is amorphous. Weight Density =.0 gm/cm 3 Molecular Density =.3E molecules/cm 3 O Crystalline O [Quartz] =.65 gm/cm 3 (1) Excellent

More information

A Deep Silicon RIE Primer Bosch Etching of Deep Structures in Silicon

A Deep Silicon RIE Primer Bosch Etching of Deep Structures in Silicon A Deep Silicon RIE Primer Bosch Etching of Deep Structures in Silicon April 2009 A Deep Silicon RIE Primer 1.0) Etching: Silicon does not naturally etch anisotropically in fluorine based chemistries. Si

More information

IC/MEMS Fabrication - Outline. Fabrication

IC/MEMS Fabrication - Outline. Fabrication IC/MEMS Fabrication - Outline Fabrication overview Materials Wafer fabrication The Cycle: Deposition Lithography Etching Fabrication IC Fabrication Deposition Spin Casting PVD physical vapor deposition

More information

Total Points = 110 possible (graded out of 100)

Total Points = 110 possible (graded out of 100) Lab Report 1 Table of Contents 1. Profiles & Layout (9 Points) 2. Process Procedures (20 points) 3. Calculations (36 Points) 4. Questions (35 Points) 5. Bonus Questions (10 Points) Total Points = 110 possible

More information

Metallization deposition and etching. Material mainly taken from Campbell, UCCS

Metallization deposition and etching. Material mainly taken from Campbell, UCCS Metallization deposition and etching Material mainly taken from Campbell, UCCS Application Metallization is back-end processing Metals used are aluminum and copper Mainly involves deposition and etching,

More information

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width Microelectronics Introduction to the IC technology M.Rencz 11 September, 2002 9/16/02 1/37 Integrated circuits Development is controlled by the roadmaps. Self-fulfilling predictions for the tendencies

More information

Lecture 12. Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12. ECE Dr. Alan Doolittle

Lecture 12. Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12. ECE Dr. Alan Doolittle Lecture 12 Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12 Evaporation and Sputtering (Metalization) Evaporation For all devices, there is a need to go from semiconductor to metal.

More information

Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high

Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high vacuum ~10-7 torr Removes residual gases eg oxygen from

More information

Lecture 22: Integrated circuit fabrication

Lecture 22: Integrated circuit fabrication Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................

More information

CHAPTER 4: Oxidation. Chapter 4 1. Oxidation of silicon is an important process in VLSI. The typical roles of SiO 2 are:

CHAPTER 4: Oxidation. Chapter 4 1. Oxidation of silicon is an important process in VLSI. The typical roles of SiO 2 are: Chapter 4 1 CHAPTER 4: Oxidation Oxidation of silicon is an important process in VLSI. The typical roles of SiO 2 are: 1. mask against implant or diffusion of dopant into silicon 2. surface passivation

More information

Chapter 4. UEEP2613 Microelectronic Fabrication. Oxidation

Chapter 4. UEEP2613 Microelectronic Fabrication. Oxidation Chapter 4 UEEP2613 Microelectronic Fabrication Oxidation Prepared by Dr. Lim Soo King 24 Jun 2012 Chapter 4...113 Oxidation...113 4.0 Introduction... 113 4.1 Chemistry of Silicon Dioxide Formation... 115

More information

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 36 MOSFET I Metal gate vs self-aligned poly gate So far, we have discussed about

More information

Isolation Technology. Dr. Lynn Fuller

Isolation Technology. Dr. Lynn Fuller ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041

More information

Regents of the University of California 1

Regents of the University of California 1 Electroplating: Metal MEMS Nickel Surface-Micromachining Process Flow Photoresist Wafer Release Etchant Use electroplating to obtain metal μstructures When thick: call it LIGA Pros: fast low temp deposition,

More information

4/10/2012. Introduction to Microfabrication. Fabrication

4/10/2012. Introduction to Microfabrication. Fabrication Introduction to Microfabrication Fabrication 1 MEMS Fabrication Flow Basic Process Flow in Micromachining Nadim Maluf, An introduction to Microelectromechanical Systems Engineering 2 Thin Film Deposition

More information

THERMAL OXIDATION - Chapter 6 Basic Concepts

THERMAL OXIDATION - Chapter 6 Basic Concepts THERMAL OXIDATION - Chapter 6 Basic Concepts SiO 2 and the Si/SiO 2 interface are the principal reasons for silicon s dominance in the IC industry. Oxide Thickness µm 0. µm 0 nm nm Thermally Grown Oxides

More information

Development of Silicon Pad and Strip Detector in High Energy Physics

Development of Silicon Pad and Strip Detector in High Energy Physics XXI DAE-BRNS High Energy Physics Symposium 2014, IIT Guwahati Development of Silicon Pad and Strip Detector in High Energy Physics Manoj Jadhav Department of Physics I.I.T. Bombay 2 Manoj Jadhav, IIT Bombay.

More information

Department of Electrical Engineering. Jungli, Taiwan

Department of Electrical Engineering. Jungli, Taiwan Chapter 3 Fabrication of CMOS Integrated Circuits Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Background Outline The CMOS Process Flow Design Rules Latchup

More information

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #9

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #9 Issued: Tuesday, Nov. 11, 2014 PROLEM SET #9 Due: Wednesday, Nov. 19, 2010, 8:00 a.m. in the EE 143 homework box near 140 Cory 1. The following pages comprise an actual pwell CMOS process flow with poly-to-poly

More information

Regents of the University of California

Regents of the University of California Topography Issues Degradation of lithographic resolution PR step coverage, streaking Thickness differences pose problems for reduction steppers Direction of Spin PR PR PR Stringers Problematic when using

More information

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 2001 by Prentice Hall Chapter 17 Doping Processes Common Dopants Used in Semiconductor Manufacturing Acceptor Dopant Group IIIA

More information

PHYSICAL ELECTRONICS(ECE3540) Brook Abegaz, Tennessee Technological University, Fall 2013

PHYSICAL ELECTRONICS(ECE3540) Brook Abegaz, Tennessee Technological University, Fall 2013 PHYSICAL ELECTRONICS(ECE3540) Brook Abegaz, Tennessee Technological University, Fall 2013 1 Chapter 1 The Crystal Structure of Solids Physical Electronics: Includes aspects of the physics of electron movement

More information

L5: Micromachining processes 1/7 01/22/02

L5: Micromachining processes 1/7 01/22/02 97.577 L5: Micromachining processes 1/7 01/22/02 5: Micromachining technology Top-down approaches to building large (relative to an atom or even a transistor) structures. 5.1 Bulk Micromachining A bulk

More information

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each

More information

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook CMOS Fabrication Dr. Bassam Jamil Adopted from slides of the textbook CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different

More information

Semiconductor Very Basics

Semiconductor Very Basics Semiconductor Very Basics Material (mostly) from Semiconductor Devices, Physics & Technology, S.M. Sze, John Wiley & Sons Semiconductor Detectors, H. Spieler (notes) July 3, 2003 Conductors, Semi-Conductors,

More information

Lecture #18 Fabrication OUTLINE

Lecture #18 Fabrication OUTLINE Transistors on a Chip Lecture #18 Fabrication OUTLINE IC Fabrication Technology Introduction the task at hand Doping Oxidation Thin-film deposition Lithography Etch Lithography trends Plasma processing

More information

Defects and Diffusion

Defects and Diffusion Defects and Diffusion Goals for the Unit Recognize various imperfections in crystals Point imperfections Impurities Line, surface and bulk imperfections Define various diffusion mechanisms Identify factors

More information

MOSFET. n+ poly Si. p- substrate

MOSFET. n+ poly Si. p- substrate EE143 Midterm #1 Solutions Fall 2005 (maximum score is 97) Problem 1 Processing Modules and Simple Process Sequence (25 points total) The following schematic cross-section shows a MOSFET together with

More information