New Applications of CMP for Non-Traditional Semiconductor Manufacturing. Robert L. Rhoades, Ph.D. Entrepix, Inc.

Transcription

1 New Applications of CMP for Non-Traditional Semiconductor Manufacturing Robert L. Rhoades, Ph.D. Entrepix, Inc.

2 Outline Introduction New Applications of CMP MEMS Non-CMOS Devices New Materials Epitaxial Layers and Engineered Substrates Direct Wafer Bonding Summary and Future Outlook

3 Introduction CMP has been a mainstream process <15 years CMP processes in CMOS flow include: Oxide (pre-metal or interlevel dielectric planarization) Tungsten (contacts, plugs, local interconnect) Shallow trench isolation Copper dual damascene Other technologies are now adapting CMP to solve planarization challenges Some require only process modifications and some require new pads and/or slurries

4 CMP Process Complexity Wafer / Materials Parameters Size / Shape / Flatness Film Stack Composition Metals (Al, Cu, W, Pt, etc.) Oxide (TEOS, PSG, BPSG, etc.) Other (polysilicon, low-k polymers, etc.) Film Quality Issues Stress (compressive or tensile) Inclusions and other defects Doping or contaminant levels Final Surface Requirements Ultralow surface roughness Extreme planarization, esp. Copper Low defectivity at <0.12 um defect size Pad Issues Materials (polyurethane, felt, foam, etc.) Properties must be chosen for the job Conditioning method often not optimized Lot-to-lot consistency Slurry Issues Chemistry optimization often required Mixing and associated inconsistency Shelf life and pot life sometimes very short Slurry distribution system (design, cost, upkeep) Agglomeration and gel formation Filtration is often required Cleaning method specific to slurry and film Waste disposal and local regulations Process Issues Long list of significant input variables Downforce Platen speed Carrier speed Slurry flow Conditioning method Disk used (material, diamond size, spacing, etc) Force Speed Sweep profile Highly sensitive to local pattern variation Must maintain consistency at high throughput Must optimize for variation of incoming films Integration Issues Materials Compatibility Electrochemical interactions with two or more metals Film integrity and delamination, esp. low-k Film stack compressibility Interactions with adjacent process modules Photolithography Metal deposition and metal etch Dielectric deposition and etch Electrical design interactions Feature size constraints Interactions with local pattern density Line resistance variation, esp. damascene copper Dielectric thickness variation Contact resistance variation Any one of these areas can create major headaches for process engineers & integration teams.

5 MEMS Applications Typical Devices: Accelerometers Torque sensors Optical devices Microfluidic processors Typical Materials Undoped oxides (TEOS, silane, etc.) Doped oxides (PSG, BPSG, etc.) Polysilicon Some metals (specialized apps) Key Aspects of the Application Materials and core processes generally adapted from CMOS fabrication CMP is an enabling technology for many designs Thicknesses and step heights substantially larger than typical of CMOS Lengthy polish times challenge process stability & consumables lifetime Photos downloaded from web sites, including Sandia National Lab

6 MEMS Processing Typical Parameters & Targets Film Thickness 2 15 microns Topography 2 20 microns Removal Rate > 0.5 um/min Planarization Efficiency > 90% MEMS Examples: Thick Poly Stop on oxide Thick Oxide Stop on poly Thick Oxide Stop on silicon Thick Metal Stop on oxide Tungsten Stop on oxide Copper Stop on oxide Any dielectric Stop mid-layer And many more

7 Example: MEMS over CMOS Key Process Metrics & Constraints Metric Incoming Value Post-CMP Target Actual Oxide film thickness 6.5 um 3.0 um 3.02 um Step Height 2.8 um < 0.4 um 0.2 um Removal Rate (um/min) n/a Critical Concerns: Final topography must be < 0.4um Smooth No sharp corners anywhere Batch to batch consistency Removal Rate (Ang/min) Run #

8 Selectivity for Specialized Integrations Example Parameter Top layer material Bottom layer material BPTEOS removal rate Selectivity (BPTEOS:SiN) Planarization Efficiency Value or Description BPTEOS oxide LPCVD silicon nitride 4900 Ang/min >25 : 1 > 98% Example: BPTEOS on Silicon Nitride Topography patterned in nitride Deposit doped (or undoped) TEOS for inlaid planarization layer Goal of CMP process is to stop on nitride without breaking through and planarize across all inlaid features Other Systems Polysilicon over oxides Oxides over single crystal silicon Inlaid metals (damascene)

9 Direct Wafer Bonding Typical Materials Silicon-on-Something Ge-on-Something TEOS over almost anything Compound semi sandwich Inlaid structures Types of Devices High performance substrates Integrated optics devices Buried device functionality Key Aspects of the Technology Surface roughness is generally the most critical metric Short range and long range topography also major metrics on patterned wafers Post-CMP cleaning is often supplemented by aggressive pre-bond cleaning New applications for DWB are emerging at a rapid pace

10 Examples: DWB Material Stack TEOS on Silicon Incoming Ra (A) 7 Post-CMP Ra (A) 3 Example #1: TEOS on X Oxide surfaces tend to bond well when polished to sufficiently low Ra TEOS on SiC TEOS on Polysilicon TEOS on AlN TEOS on Metal Incoming roughness driven by surface prep of underlying material Sufficient oxide thickness must be deposited to remove at least 2x initial peak-to-valley roughness Example #2: Inlaid Cu in TEOS Incoming topography >2.5 ka Goal of <200 A total topography Flat across Feature POST-CMP TOPOGRAPHY ACHIEVED Angstroms

11 Backside Stress Relief CMP Backgrind is a nearly universal technique for wafer thinning CMOS, discrete devices, MEMS, sensors, etc. Different device technologies have different drivers. [1] Packaging (space limitations, 3D systems, ultrathin applications, etc.) Heat dissipation Lower noise and other electrical performance improvements Damage created during backgrind creates a compressive stress layer that penetrates into the Si crystal. (Previous studies indicate a depth between 8 and 30 microns.) [2] Wafer and die strength are compromised by the damage layer. [3] CMP is an effective technique for creating low-defect surfaces and can be used to remove the damage layer (similar to prime wafer polishing). [1] M. Reiche and G. Wagner, Wafer Thinning: Techniques for Ultra-thin Wafers, Advanced Packaging, March [2] C. McHatton and C. Gumbart, Eliminating Backgrind Defects with Wet Chemical Etching, Solid State Technology, November [3] E. Gaulhofer, Wafer Thinning and Strength Enhancement to Meet Emerging Packaging Requirements, IEMT Symposium, IEEE, April 2000.

12 Example: Backside CMP 7 6 Significant subsurface damage evident as pits or scratch tracks after decoration etch Minimal surface pitting after decoration etch 5 As ground surface (20x objective lens) Deep grooves easily seen with naked eye Surface Rating Post decoration etch (50x objective lens) Clean (no visible particles) with very mild etch roughening No pits or strong dislocation lines observed Thickness Removed (um) Conclusion Regardless of backgrind or CMP process parameters, decoration etch does not reveal significant damage as long as CMP removes at least 4.5 um of silicon.

13 New Materials Reasons for introducing new materials Enhance performance of next generation device Develop completely new type of device Improve yield or lower cost Largest volume application is CMOS Strained layer technology Low-k dielectrics Pt, Ru, or other refractory metals Many new device applications being developed

14 Evolution of CMP applications... And that s just Si electronics!! Future Trend?

15 Engineered Substrates Typical Materials SOI Strained Layer SiGe Custom III-V or II-IV composites Epi Layer Base Substrate Key Aspects of the Application SOI helps circuit isolation and power consumption (less coupling) Strained layer technology being used to increase carrier mobility in Si devices Heteroexpitaxy of mismatched materials seeing growing # of applications Usually creates huge density of threading dislocations and other issues Extremely high roughness needs to be polished to achieve <1nm Ra Some materials (esp. II-IV blends) difficult to polish w/o anisotropic etching Cleaning of polished surfaces is often difficult (some are etched by NH4OH)

16 Specialty Substrates: SiGe Layers Metric Incoming Value Target Actual Surface Roughness, Ra >10 nm <1 nm nm Removal Rate n/a >500 A/min A/min Total Mtrl Removal n/a um Within 5% Polish Rate (Ang/min) Roughness, Ra (nm) % 20% 40% 60% 80% 100% Epi Layer %Ge 0 Pre-CMP Post-CMP

17 Other Novel CMP Applications Integrated Optics Waveguides Reflective surfaces Active switches, multiplexers, etc. In-plane or through plane Packaging Applications Large Cu vias and feedthroughs Polymer planarization for multiple layers Compound Semiconductor Devices Unique integration schemes and process flows Much more delicate substrates Generally involve smaller wafer sizes (100mm, etc.)

18 Current Status CMP is accepted as a mainstream process Adaptation to numerous other technologies is well underway Often involve materials not found in CMOS mfg Film thickness can be 10 s of microns or more! Specialization of pads/slurries is usually only required if standard products fail Difficult to predict which segments will grow the fastest, but MEMS has the lead CMP suppliers and technologists will continue to be challenged as new applications emerge

19 Acknowledgments Jeanie Simmons, Terry Pfau, Paul Lenkersdorfer, Donna Grannis, Dwaine Halberg, and the rest of the Entrepix process staff. For more information, please contact: Rob Rhoades Chief Technology Officer Tel: Fax: Mike Bowman Director of Business Development Tel: Bob Tucker VP and General Manager Tel: