Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley

Transcription

1 Microstructure of Electronic Materials Amorphous materials Single-Crystal Material 1

2 The Si Atom The Si Crystal diamond structure High-performance semiconductor devices require defect-free crystals 2

3 Crystallographic Planes Unit cell: Si lattice constant = 5.431Å 5 x 1022 atoms/cm3 View in <100> direction View in <110> direction View in <111> direction 3

4 Crystallographic Notation Miller Indices Notation (hkl) Interpretation {hkl} equivalent planes [hkl] crystal direction <hkl> equivalent directions crystal plane h: inverse x-intercept k: inverse y-intercept l: inverse z-intercept (Intercept values are in multiples of the lattice constant; h, k and l are reduced to 3 integers having the same ratio.) 4

5 Carrier Concentrations of Intrinsic (undoped) Si electron - Bottom of conduction band Energy gap =1.12 ev hole + Top of valence band n (electron conc) = p (hole conc) = ni 5

6 Dopants in Si By substituting a Si atom with a special impurity atom (Column V or Column III element), a conduction electron or hole is created. Donors: P, As, Sb Acceptors: B, Al, Ga, In 6

7 n-type Semiconductor If ND >> NA (such that ND NA 10 ni): = + ND /cm3 n-type NA /cm3 2 n ND N A and ni p ND N A Note n >> p 7

8 p-type Semiconductor If NA >> ND (such that NA ND 10 ni): = + ND /cm3 NA /cm3 p-type 2 p N A ND and ni n N A ND Note p >> n 8

9 Adding parts/billion to parts/thousand of dopants to pure Si can change resistivity by 8 orders of magnitude! 1 Note: -m = 100 Resistivity Range of Materials Si with dopants SiO2, Si3N4 -cm 9

10 Principle of Monolithic Process Integration * A sequence of Additive and Subtractive steps with lateral patterning Example: CMOS Integrated Circuit Processing Steps Si wafer

11 Czochralski Crystal Growth Crystal Pulling Shaping and Polishing Crystal Ingots 300 mm wafer 11

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14 Purity of Starting IC Si Wafer % (so(so-called eleven nines )!! Maximum impurity of starting Si wafer is equivalent to 1 mg of sugar dissolved in an Olympic-size swimming pool..

15 Solar Cell Grade Silicon For reference only Metallurgic Grade Silicon (MG): Si 90-99%, US$ 1 2.5/kg Solar Grade Silicon (SG)*: Si %, US$ 30 40/kg Electronic Grade Silicon (EG): Si > %, over US$ 60/kg

16 Photolithography glass plate chromium Processing Temperature Ambient Positive Resist Region exposed to light will be dissolved in development solution. 16

17 Example : Deep UV Photolithography Sequence: (1)Surface Prime, (2) Coat, (3) Prebake, (4) Expose, (5) Post Exposure bake, (6) Develop, (7) Hard Bake

18 Example : Deep UV Photolithography (continued)

19 Example : Deep UV Photolithography (continued) *All baking sub-steps are similar but with different temperature and time

20 Etching Pattern resist mask Etching thin film Etching completed Remove resist mask Anisotropic Processing Temperature (e.g. Reactive Ion Etching RIE ) Ambient Isotropic (e.g. Wet Etching) 20

21 Etching Selectivity Example: HF solution etches SiO2 but not Si HF SiO2 Si solution Si * A high etching selectivity is usually desired 21

22 Anisotropic Wet Etching of Si Crystals Etchants : KOH or EDP (Ethylene-Diamine_Pyrocatechol) Cross-section Top view (100) Si substrate Etching stops Etching continues Effect of different mask opening 22

23 Thermal Oxidation Processing Temperature oc Si + O2 SiO2 Si + 2 H2O SiO2 + 2H2 Oxide (Xox) thickness t t O2 (or H2O) diffuses through SiO2 and reacts with Si at the interface to form more SiO2. 1 m of SiO2 formed consumes 0.44 m of Si substrate. Thin oxide growth (e.g. gate oxide) - use O2. Dry oxidation Thick oxide growth (e.g. field oxide) - use H2O. Wet oxidation Oxidation time(t) 23

24 Uneven surface topography with window oxidation 1st oxidation SiO2 Si Si Realistic topography with 2-dimensional effect SiO2 Si Pattern oxide window by litho and etch 2nd oxidation SiO2 SiO2 Si Si Note uneven Si surface after window oxidation 24

25 Local Oxidation silicon nitride as oxidation mask O2 Si3N4 pad oxide ~100 A Si Thermal Oxidization LOCOS Process nitride SiO2 Si 25

26 Ion Implantation typically used to introduce dopants into semiconductors Ion Energy ~1 kev to 200 kev Processing Temperature Room temp during implantation. After implantation, a 900oC-1000oC anneal step is needed to: 1) activate dopants 2) restore Si crystallinity 26

27 Diffusion To introduce dopants into semiconductors [ Predeposition] To spread out the dopant profile [ Drive-in] Processing Temperature oc D D0 e Q kt D Diffusion Constant Q Activation Energy T Temp in K D as T 27

28 Predeposition Si surface concentration maintained at constant Cs (solid-solubility) during predep. Dose of dopant incorporation (in #/cm2) C s 2 Dt = 28

29 Predeposition and Drive-in Drive-in means removing dopant supply after Predep step and anneal at high temperature Half-gaussian depth profile after long drive-in. Predep only Predep +Drive-in Dopant dose conserved during drive-in. Diffusion distance Dt Concentration (in #/cm3) versus Depth 29

30 Physical Vapor Deposition (1) Evaporation Deposition Si Substrate Substrate at ~ room temp Deposited Al film (polycrystalline) evaporation Al charge (Tsource >>Tboiling of Al, 700OC) 30

31 Physical Vapor Deposition (2) Sputtering Deposition Si Substrate Substrate at room temp Deposited Al film (polycrystalline) Ar+ Ar ions with ~ kev kinetic energy Al atoms ejected due to Ar ion bombardment Al target 31

32 Chemical Vapor Deposition (CVD) 32

33 Chemical Vapor Deposition (CVD) of SiO2 Si (C 2 H 5 O ) 4 2 H 2 O SiO 2 4C 2 H 6 O or SiH 4 O 2 SiO 2 2H 2 LTO TEOS Temperature range: 350oC to 450oC for silane ~700oC for TEOS Process: Precursor gases dissociate at the wafer surface to form SiO2 No Si on the wafer surface is consumed Film thickness is controlled by the deposition time oxide thickness t time, t

34 Plasma Enhanced CVD Plasma generates dissocated and Ionized chemical species Lower CVD process temperature can be used. 34

35 Epitaxial Growth Processing Temperature oC Requires an ultra-clean Si surface prior to epi growth. Requires deposition of Si at very high temperature for perfect crystallinity. 35

36 Chemical Mechanical Polishing (CMP) Wafer is polished using a slurry containing silica abrasives (10-90 nm particle size) etching agents (e.g. dilute HF) Backing film provides elasticity between carrier and wafer Polishing pad made of polyurethane, with 1 m perforations rough surface to hold slurry Ambient Temperature 36

37 Chemical Mechanical Polishing (CMP) CMP is used to planarize the surface of a wafer at various steps in the process of fabricating an integrated circuit. interlevel dielectric (ILD) layers shallow trench isolation (STI) copper metallization Shallow Trench Oxide p+ n p+ SiO2 p n+ p n+ ILD with 5 layers of Al wiring

38 Copper Plating Dual Damascene Process (IBM Corporation) (1) (2) (3) courtesy of Sung Gyu Pyo, Hynix Semiconductor (4) (5)

39 Rapid Thermal Annealing (RTA) Special annealing tools have been developed to enable much faster temperature ramping, and precise control of annealing time ramp rates as fast as 200oC/second anneal times as short as 0.5 second typically single-wafer process chamber Sub-micron MOSFETs need ultra-shallow junctions (xj<50 nm) Dopant diffusion during activation anneal must be minimized Short annealing time (<1 min.) at high temperature is required Ordinary furnaces (e.g. used for thermal oxidation and CVD) heat and cool wafers at a slow rate (<50oC per minute)

40 Rapid Thermal Annealing Tools There are 2 types of RTA systems: 1. Furnace-based steady heat source + fast mechanical wafer transport 2. Lamp-based stationary wafer + time-varying optical output from lamp(s) Furnace RTA Lamp RTA A.T. Fiory, Proc. RTP2000

41 Microfabrication Module Summary List Lithography Thermal Oxidation Etching (Chemical, RIE) Ion Implantation Diffusion (Furnace Annealing, Rapid Thermal Annealing RTA) Physical Vapor Deposition PVD Chemical Vapor Deposition CVD, Epitaxial Growth, PECVD Chemical Mechanical Polishing CMP Metal Plating Others. 41

42 Pr o c e s s Te m p e r a t u r e in C PROCESSING TEMP RANGE AND MATERIAL FAILURE TEMP Si Melting Point (1450C) Al-Si Eutectic (560C) Photoresist Reflow (180C)