CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing
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1 CS/ECE 5710/6710 CMOS Processing Addison-Wesley N-type Transistor D G +Vgs + Vds S N-type from the top i electrons - Diffusion Mask Mask for just the diffused regions Top view shows patterns that make up the transistor Polysilicon Mask Mask for just the polysilicon areas 1
2 Combine the two masks IC Fabrication IC fabrication is very similar to screenprinting Image is created (positive or mask) Exposed onto a screen (photo emulsion) Unexposed parts are washed away Remainder is used as a mask (stencil) for the processing (application of ink) You get an N-type transistor There are other steps in the process Screen Printing IC Fabrication Like Screenprinting At a much finer scale of course Start with a mask that defines where the processing should happen at each step (for each color) Expose mask onto photoresist (emulsion) Wash away unexposed parts Use hardened polymer as a mask for processing Screen Printing Multiple masks (separations) are used to make multi-color images Processing order is important Addison-Wesley 2
3 Photolithographic Process Photolithographic Process Photolithographic Process Photolithographic Process Photolithographic Process Photolithographic Process 3
4 Photolithographic Process Look at Inverter Layout Again A Cutaway View CMOS structure with both transistor types How many layers? How many processing steps? 4
5 Addison-Wesley Addison-Wesley 5
6 Growing the Silicon Crystal Need single crystal structure Single crystal vs. Polycrystalline silicon (Poly) Czochralski Method Slice Crystal into Wafers Need single-crystal silicon to accept impurities correctly Donor elements provide electrons Acceptor elements provide holes Pull a single crystal of silicon from a puddle of molten polycrystalline silicon Slice into thin wafers (.25mm - 1.0mm), and polish to remove all scratches Lapping and Polishing Oxidation, Growing SiO2 Essential property of silicon is a nice, easily grown, insulating layer of SiO2 Use for insulating gates ( thin oxide ) Also for field oxide to isolate devices 6
7 Making the Mask Adding Photoresist Photoresist can be positive or negative Does the exposed part turn hard, or the unexposed part? Steppers Expose the Mask Develop and Bake Photoresist Use very short wavelength UV light Single frequency, nm Expensive! ~$5,000,000/machine Developed photoresist is soft, unexposed is hardened So you can etch away the soft (exposed) part Now Etch the SiO2 Etch the SiO2 to expose the wafer for processing Then Spin Rinse, and Dry Add a Processing Step Now that we ve got a pattern etched to the right level, we can process the silicon Could be: Ion Implantation (i.e. diffusion) Chemical Vapor Deposition (silicide, Poly, insulating layers, etc.) Metal deposition (evaporation or sputtering) Copper deposition (very tricky) 7
8 Ion Implantation Chemical Vapor Deposition Implant ions into the silicon Donor or Acceptor Metal Deposition Advanced Metalization Typically aluminum, gold, tungsten, or alloys Copper is Tricky 40% less resistance than Aluminum 15% system speed increase Addison-Wesley But, copper diffuses into Silicon and changes the electrical properties 8
9 Ashing - Removing Photoresist Final Layer: Passivation Basically a final insulating layer (SiO2 or Si3N4) to protect the circuit CMOS Fabrication Start from single-crystal silicon wafer Use photolithography to pattern device layers Exception Essentially one mask/photolithographic sequence per layer Built (roughly) from the bottom up 6 - Metal Metal Metal Polysilicon 3 - Diffusions 1 Tub (N-well) Via Via Contact Self-Aligned Gates Addison-Wesley CMOS Inverter Thinox in active regions, thick elsewhere Deposit Polysilicon Etch thinox from active region (Poly serves as mask for etch/diffusion) Implant dopant 9
10 N-well Mask Active Mask Poly Mask N+ Select Mask P+ Select Mask Contact Mask 10
11 Metal Mask Other Cutaway Views Another View of Fab Circuit Under Design Taken from slides by Jan Rabaey From his text Digital Integrated Circuits This two-inverter circuit (of Figure 3.25 in Rabaey s text ) will be manufactured in a twin-well process. Circuit Layout Start Material A A Starting wafer: n-type with doping level = /cm 3 * Cross-sections will be shown along vertical line A-A 11
12 N-well Construction N-well Construction (1) Oxidize wafer (2) Deposit silicon nitride (3) Deposit photoresist (4) Expose resist using n-well mask N-well Construction N-well Construction (5) Develop resist (6) Etch nitride and (7) Grow thick oxide (8) Implant n-dopants (phosphorus) (up to 1.5 µ m deep) P-well Construction Grow Gate Oxide Repeat previous steps µm thin 12
13 Grow Thick Field Oxide Polysilicon layer 0.9 µm thick Uses Active Area mask Is followed by! threshold-adjusting implants Source-Drain Implants Source-Drain Implants n+ source-drain implant (using n+ select mask) p+ source-drain implant (using p+ select mask) Contact-Hole Definition Aluminum-1 Layer (1) Deposit inter-level! dielectric (SiO 2 ) 0.75 µm (2) Define contact opening! using contact mask Aluminum evaporated! (0.8 µm thick) followed by other metal! layers and glass 13
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