The 3D Silicon Leader. Company Presentation. SMTA Houston, 14th March 2013

Transcription

1 The 3D Silicon Leader Company Presentation SMTA Houston, 14th March 2013

2 Who are we? Independent Company located in Caen, Normandy, France Dedicated to manufacturing of leading edge Integrated Passive Devices Strong R&D team and collaborations with leading research institutes Operating our own wafer fab in France with 150K wafers capacity 2

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14 IPDIA s technology 27/02/

15 Silicon Capacitor The Designer Paradigm 27/02/

16 The Derating Phenomenon Temperature, Ageing and Electrical stress have a big influence in the derating phenomenon Higher effects on Tantalum and MLCC technologies Principal sources of variation for different types of component Silicon Capacitors from Ipdia, no more Headache for Designers! 27/02/

17 Capacitance stability in temperature Ceramic VS. 3D-Si Capacitor Capacitor 27/02/

18 Capacitance change (%) Capacitance stability in temperature Tantalum VS. 3D-Si Capacitor 20 Temperature coefficient PICS vs. Tantalum capacitors Ta 0 PICS Temperature ( C) 27/02/

19 Capacitance change (%) Capacitance stability in voltage Ceramic capacitors vs. PICS 10 0 DC Voltage stability MLCC capacitors vs. PICS PICS C0G X7R Superior DC voltage stability (<0.1%/V) No capacitance change over voltage variation. Y5V Bias voltage (V) 19

20 Oustanding performance for High Temperature applications The gap from typical ceramic capacitor (X7R) Extreme stability in High temperature environments Exceptional low derating To 3D Silicon capacitor (HTSC) 20

21 High Temperature Silicon Capacitor (HTSC) 1000nF 1206 EIA Case size Capacitors comparison High Temperature Applications (-55 C to 200 C) 100nF 5.6nF 1.5nF 0.68nF 27/02/

22 DC leakage current 3V) vs Time & Temperature C= 100nF I(120s) < 25 C Ip (A) 5.0E E E E E E E E E E E+00 Ip 85 Ip 200 C Ip 250 C Ip 275 C Ip 300 C Time (s) I(120s) < C 27/02/

23 Last High Temperature package in development Molding 4.8 mm 70µm 850 µm 200µm Die #3 Die #2 Die #1 100µm DAF Dedicated Lead Frame NiPd Mitsui 27/02/ BSOB (ball stitch on ball) to limit the height

24 Capacitor value Cubic path Capacitance roadmap for 220 c package MODULE «C» MODULE «D» 47µF 10µF Puc e #3 Puc e #2 Pu ce #3 Pu ce #2 - NEW PACKAGE 4.88 x 4.6 x 0.85 mm - New leadframe design - 3 stacked dies of 3.3uF - Bonding with 25µm gold wires - Double pads and 3 wires bonding per pad to improve ESR and ESL - Capa density 250nF/mm² - BV = 11V - STYCAST resin E NEW PACKAGE 4.88 x 3.6 x 1.2 mm - New leadframe design - 5 stacked dies of 2.2uF - Bonding with 25µm gold wires - Double pads and 3 wires bonding per pad to improve ESR and ESL - Capa density 250nF/mm² - BV = 11V - STYCAST resin E2517 June/2013 September/ /02/

25 High Temperature Silicon interposer 25

26 Ultra stable low profile resistor From -55 to 225 C From 0 to 150 C From 0 to 225 C Rsq=13,5 Ohm/sq +/-20% +/-10% +/-15% Rsq=765 Ohm/sq +/-6% +/-1% +/-3% Rsq=2K Ohm/sq +/-14% +/-4% +/-4% Relative temperature variation for 3 resistor types 1,3 1,2 1,1 1,0 Rsq=13,5 Ohm/sq Rsq=765 Ohm/sq Rsq=2 kohm/sq 0,9 0, temp-tnom ( C) 27/02/

27 PICS Inductances : Q factors Q-factor : RFCMOS, PICS1, Qexceed & Qexceed+ Qexceed Cu (2 metal layers) Qexceed+ Cu (3-metal layers) PCS1 Aluminum RFCMOS45n Aluminum Comparison based on a 4 nh coil 27/02/

28 Application example: DC/DC C Texas Instrument TPS62000DGS with adjustable output Most passive components around the ASIC could be integrated into one single IPD. PCB space saving Improved performance at high temperature (200 C) New technical option to allow circuits closer to the hottest points e.g. sensors for better measurement accuracy. 28

29 IPDiA integration proposals : Chip-on-Board (COB) assembly (1/2) COB with Die Stacking + Wire Bonding ASIC IPD IPD: mixed components network Microphotography IPD thickness: 400µm Compatible with standard wire bonding assembly. For example with Al-Si-Cu finishing, wedge Aluminum is recommended. On request other finishing options are possible such as thick gold (Min 2µm). 29

30 IPDiA integration proposals : Wafer Level Chip-Scale Package Active die flipped onto IPD which in turn is flipped onto PCB. Bump 1 location ASIC 400µm bump diameter Microphotography IPD 30

31 Example of a module with many active dies stacked on the top of an RF IPD Radio module Active dies RF IPD Laminate Au wires 27/02/

32 3D silicon passive devices with outstanding performances Capacitors (from pf to µf) Superior temperature stability (<30ppm/ C) Technology characterized to +250 C Very low leakage current (<100pA) Superior DC voltage stability (<0.1%/V) No capacitance change over voltage variation. Low ESR < 40mOhm and very low ESL < 75pH Negligible aging (<0.001% / 1000 hours) Excellent matching (better than 1.5%) Tolerance: 5%, 15% C 0 e S S Coils (up to 200nH in 1,8mm²) Superior Q-factor (> 80) Self-res. freq. > 45GHz Excellent matching (better than 1%) Tolerance : 5% Resistors (up to 10M in 1mm²) Excellent matching (better than 0.2%) Tolerance: 5% Zener Diodes up 150V and ESD Capability 15KV Air discharge (IEC , level4) 27/02/

33 Your Questions 27/02/

34 27/02/ Thanks for your attention