Chapter 3 CMOS processing technology

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1 Chapter 3 CMOS processing technology (How to make a CMOS?) Si + impurity acceptors(p-type) donors (n-type) p-type + n-type => pn junction (I-V) (Wafer) Wafer = A disk of silicon (0.25 mm - 1 mm thick), (75 mm to 230 mm in diameters) Czochralski method (Fig.3.1) - Crucible: - Ingot: Controlled amount of impurities are added to the melt to provide the crystal with the required electrical properties Oxidation (produce SiO 2 ) Oxidation of silicon is achieved by heating silicon wafer in an oxidizing atmosphere such as oxygen or water vapor. A. Wet Oxidation : Water Vapor -> rapid process (900º-1000ºc) B. Dry Oxidation : pure oxygen -> slow process (1200ºc) SiO 2 layer grows almost equally in both vertical directions. Check SiO 2 (field oxide) in Fig3.2 1

2 3.1.3 Epitaxy, Deposition, Ion-implantation, and Diffusion To generate silicon that contains varying portions of donor or acceptor impurities. A. Epitaxy ( ): grow a single crystal film on the silicon surface. B. Deposition : Evaporate dopant material onto the silicon surface followed by a thermal cycle (to drive the impurity from the Si surface into the bulk) C. Ion implantation : subject the Si substrate to highly energized donor or acceptor atoms.the injected impurities will travel below the surface of the Si, forming regions with varying doping concentration. D. Diffusion : at temp. > 800ºc Impurities will diffuse from areas of high concentration to area of low concentration. =>It's important once the doped areas have been put in place, to keep the remaining process steps at as low a temperature as possible. Impurities: Boron : acceptors Arsenic, phosphorous : donors Amount is controlled by 1. energy and time of Ion implantation. 2. Time and temperature of deposition and diffusion. Mask: Implantation occurs/not occurs Deposition - Common materials used as masks include: 1. photoresist 2. polysilicon (polycrystalline silicon) 3. silicon dioxide (SiO 2 ) 4.silicon Nitride (Si 3 N 4 ) (SiN) - Function : form a barrier against doping impurities (selective diffusion) very important!! steps 1. patterning "windows" in a mask material on the surface of the wafer 2. subjecting exposed areas to a dopant source. 3.remove any undesired mask materials. SiO2 is removed using an etching technique. A. Use a acid resistant coating (photoresist)(pr) which can be polymerized by ultraviolet (UV) light. B. The polymerized areas may be removed with an organic solvent. 2

3 C. Etching of exposed SiO 2 then may proceed. A-B-C "Positive resist" "Negative resist" = unexposed PR is dissolved by the solvent. *Note diffraction around the edges of the mask patterns (= 0.8um) *Alternative approach : (high cost, precise) Electron beam lithography (EBL) (watch Fig.3.3) 3

4 3.1.4 Silicon gate process Si -> Single-crystal form Poly crystalline form (polysilicon) Polysilicon is used as interconnect wires in silicon IC's and as the gate electrode on MOS transistors. => Can be used as the "mask" for drain & source Polysilicon is formed when silicon is deposited on SiO 2 or other surfaces. For example, in CMOS, undoped polysilicon is deposited on the gate insulator. 4

5 SiO2 1. Gate-oxide (thinox) 2. Field-oxide (thick) 3. Self-aligned process (source & drain donor extend over the gate) 4. "Field device" or "Parasitic MOS transistors" 5

6 3.2 CMOS Process Technology 1. n-well process 2. p-well process 3. Twin-tub process 4. Silicon-on-insulator (SOI) Basic n-well CMOS process 1. Start with a lightly doped p-type substrate (wafer) 2. Create the n-type well for the p-channel device. 3. Build the n-channel transistor in the "native" p-substrate (watch Fig.3.6 & Fig.3.7) 4. CMOS process and layout drawing conventions 6

7 n-well-shallow is better n-well, n-tub (for p-device) Grow SiO2/SiN Channel-stop implant : prevent conduction between unrelated transistor Grow field oxide (LOCOS) (bird s break) smaller L adjust threshold voltage add polysilicon etch 7

8 N+ mask (self-aligned by poly) Light-Doped Drain (LDD) P+ mask (LDD is not required) Grow SiO2 Etch SiO2 (Define contact cut) Add metal (circuit connectivity) 8

9 Substrate contact (well contacts, body ties, tub ties) 1.Place n+ region in the n-well (VDD contacts) 2.Place p+ region in the p-type substrate (Vss contacts) p-well process 1.n-well process is more popular in recent years (p-well process is popular in the past) 2.n-well <-> p-well in process 3.The device in the substrate has better characteristics -> p-well process has better p devices than the n devices -> note p-devices have lower gain than the n devices -> n-well process exacerbates the difference <-> p-well process balance the diffusion Twin-tub CMOS process 1. Provide separate optimization of the n-type and p-type transistors 2. Make it possible to optimize "Vt", "body effect", and the "gain" of n, p devices independently. 9

10 3. Steps: A. Starting material: an n+ or p+ substrate with lightly doped - "epitaxial" or "epi" layer -> to protect "latch up" B. Epitaxy" a. Grow high-purity silicon layers of controlled thickness b. With accurately determined dopant concentrations c. Electrical properties are determined by the dopant and its concentration in Si C. Process sequence a. Tub formation b. Thin-Oxide construction c. Source & drain implantations d. Contact cut definition e. Metallization Balanced performance of n, p devices can be constructed. (substrate contacts are included in Fig.3.10) 10