Cypress Semiconductor Package Qualification Report

Transcription

1 ackage Qualification Report QT# VERSION 1.1 December 2007 Wafer Level CS Image Sensor (WLCS) (6.6 x 6.4mm) SnAgCu, MSL3, 245C Reflow XINTEC, Taiwan CYRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Fredrick Whitwer Mira Ben-Tzur rincipal Reliability Engineer Reliability Engineering Director (408) (408)

2 ackage: Wafer Level CS Image Sensor (WLCS) age 2 of 6 ACKAGE QUALIFICATION HISTORY QUAL REORT DESCRITION OF QUALIFICATION UROSE Qualify Xintec Incorporated Taiwan as a new assembly site for R3 Wafer Level CS Image Sensor (6.6x6.4mm) in ShellOC (Open Cavity) Technology using NEG bare glass, 353ND epoxy for top glass bond, U300 for bottom glass bond and Sn (96.5%) Ag (3%) Cu (0.5%) Solder Bump at MSL3, 245C Solder Reflow DATE COM. Dec 07

3 ackage: Wafer Level CS Image Sensor (WLCS) age 3 of 6 MAJOR ACKAGE INFORMATION USED IN THIS QUALIFICATION ackage Designation: SC70A ackage Outline, Type, or Name: Wafer Level CS Image Sensor (WLCS) Lead Seal Method: N/A Glass Lid Material: Schott AF45 bare glass Solder Ball: Sn(96.5%) Ag(3%)Cu (0.5%) Die Backside reparation Method/Metallization: Backgrind Die Separation Method: Saw Die Attach Supplier: Epotek Die Attach Material: 353ND Top glass, U300 Bottom glass Bond Diagram Designation: Thermal Resistance Theta JA C/W: 33 C/W ackage Cross Section Yes/No: N/A Assembly rocess Flow: Name/Location of Assembly (prime) facility: Xintec, Taiwan MSL Level 3 Reflow profile 245C ELECTRICAL TEST / FINISH DESCRITION Test Location: CML

4 ackage: Wafer Level CS Image Sensor (WLCS) age 4 of 6 RELIABILITY TESTS ERFORMED ER SECIFICATION REQUIREMENTS Stress/Test Test Condition (Temp/Bias) Result /F High Temperature Operating Life Latent Failure Rate Temperature Cycle Temperature Humidity Bias Electrostatic Discharge Charge Device Model (ESD-CDM) Electrostatic Discharge Human Body Model (ESD-HBM) Dynamic Operating Condition, Vcc Max (Core) = 2.875V, 125 C JEDEC22 Method A104C, Condition G, -40 C to 125C recondition: JESD22 Moisture Sensitivity Level Hrs 30 C/60%RH+3IR-Reflow, 245 C+0, -5 C 85C, 85%RH, 2.75V recondition: JESD22 Moisture Sensitivity Level Hrs 30 C/60%RH+3IR-Reflow, 245 C+0, -5 C 500V Cypress Spec ,800V JESD22 Method A114-E Constructional Analysis Cypress Spec External Visual Cypress Spec / High Temperature Storage 150C, no bias Mechanical Shock Mil Std 883 Method 2002 Condition B Mechanical Vibration Mil Std 883 Method 2007 Condition A hysical Dimension Cypress Spec

5 ackage: Wafer Level CS Image Sensor (WLCS) age 5 of 6 Reliability Test Data QT #: Device Fab Lot # Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: CONSTRUCTIONAL ANALYSIS R3MAL (R3MAL) KC5819 Wafer 3 XT-TAIWN COM 1 0 STRESS: ESD-CHARGE DEVICE MODEL, 500V R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN COM 9 0 STRESS: ESD-HUMAN BODY CIRCUIT ER JEDEC EIA/JESD22-A114-E, 1,800V R3M2AL (R3M2AL) KC5819 Wafer 1 XT-TAIWN COM 3 0 STRESS: EXTERNAL VISUAL R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN COM STRESS: HIGH TEMERATURE STORAGE R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN STRESS: HIGH TEM DYNAMIC OERATING LIFE-LATENT FAILURE RATE, 150C, 1.85V, Vcc Max R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 2 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 2 XT-TAIWN STRESS: HYSICAL DIMENSIONS R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN COM 5 0 R3MAL (R3MAL) KC5819 Wafer 2 XT-TAIWN COM 5 0 R3MAL (R3MAL) KC5819 Wafer 3 XT-TAIWN COM 5 0 STRESS: TC COND. C 40C TO 125C RE COND 192 HR 30C/60%RH, MSL3 R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 2 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 2 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 2 (A) XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 2 (A) XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 2 (B) XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 2 (B) XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 3 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 3 XT-TAIWN

6 ackage: Wafer Level CS Image Sensor (WLCS) age 6 of 6 Reliability Test Data QT #: Device Fab Lot # Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism STRESS: TEM HUMIDITY BIAS, 2.75V, RECONDITION 192 HRS 30C/60%RH, MSL3 R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN R3MAL (R3MAL) KC5819 Wafer 2 XT-TAIWN STRESS: MECHANICAL SHOCK CONDITION B R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN COM 15 0 R3MAL (R3MAL) KC5819 Wafer 2 XT-TAIWN COM 15 0 R3MAL (R3MAL) KC5819 Wafer 3 XT-TAIWN COM 15 0 STRESS: MECHANICAL VIBRATION CONDITION A R3MAL (R3MAL) KC5819 Wafer 1 XT-TAIWN COM 15 0 R3MAL (R3MAL) KC5819 Wafer 2 XT-TAIWN COM 15 0 R3MAL (R3MAL) KC5819 Wafer 3 XT-TAIWN COM 15 0