Semiconductor Manufacturing Process 10/11/2005

Transcription

1 Semiconductor Manufacturing Process 10/11/2005

2 Photolithography Oxidation CVD PVD

3 Photolithography The purpose of photolithography is to imprint the desired pattern of a micro component on a substrate, normally on silicon substrates. Patterns in micro scale are produced from photo-reduction of the same pattern drawn in macro scale. Typically, the photo-reduced patterns are imprinted on masks that are commonly made of dimensionally stable transparent substrates such as quartz. The mask with micro patterns is then placed on the top of a silicon substrate, or a silicon dioxide over the silicon substrate, coated with a thin layer of photoresist. Upon exposing the photoresist to special light beams through the mask, part of the photoresist would dissolve in the subsequent development process. The remaining part of the photoresist will bear the desired patterns for the micro component. Photolithography needs to be performed in Class 10 or better clean rooms. The process is illustrated in Fig. 8.1

4 Illustration of a photolithography process Positive resist: Substrate (a) Photoresist Substrate (b) UV light or other sources Mask Negative resist: (c) Substrate (a) Processes: (a) Development (b) Etching (c)resist removal (b) (c)

5 Photoresists and application Positive photoresists: The photoresists that dissolve after exposed to light. PMMA is the most popular positive photoresist. Negative photoresists: The photoresists that dissolve under shadow. Kodak KTFR is a popular negative photoresist. Positive photoresists usually result in clear line definition: (a) by negative resists Application of photoresists: Dispenser Resist puddle Vacuum chuck Spinner motor To vacuum pump Resist spray Wafer To drain & exhaust Catch cup (b) by positive resists Edge bead Vacuum chuck Photoresist Wafer The chuck spins at rpm for seconds. Photoresist thickness is in µm. Edge beds is a problem. They can be mitigated by controlling the spin speed of the chuck.

6 Light sources Most photoresists are sensitive to light with wavelength in nm. Popular light source is mercury vapor lamps at nm. Deep UV light is used with wavelength at nm. In rare cases, such as in the LIGA process, x-ray at wavelength of 4 to 50 A is used. Photoresist development Substrates or wafers with photo-exposed negative photoresists are developed in the same chuck that is used in the photoresist application, except that solvents, such as xylene are spray from the overhead nozzle. Development for positive photoresists require stronger developer such as KOH or TMAH, which are common etchants in microfabrication processes. Descumming process takes place following the development of photoresists. This process involve the application of mild oxygen plasma to remove the bulk of the photoresists. The wafer or substrate is then baked at 120 o C for 20 minutes to dry.

7 Oxidation Oxidation in microelectronics and MEMS means to produce a thin layer of SiO 2 at the surface of silicon substrates. Oxide layers serve two principal purpose of providing thermal and electrical insulation at the desired locations. Wire bond Piezoresistor Metal film Dielectric layer Silicon gel Silicon Diaphragm Pyrex Glass Constraining Base Interconnect Die Attach Passage for Pressurized Medium Metal Casing Piezoresistors Mask for insulator (SiO 2) SiO 2 insulator Silicon die

8 Thermal oxidation Thermal oxidation involves creating oxide layer on top surface of silicon substrates by blowing dry oxygen gas, or steam at elevated temperature. Chemical reactions for producing silicon dioxide in silicon substrates are: For dry oxidation: For wet oxidation: Si (solid) + O 2 (gas) SiO 2 (solid) Facility for thermal oxidation: Si (solid) + 2H 2 O (steam) SiO 2 (solid) + 2H 2 (gas) O 2 or H 2 O + carrier gas Resistance heater Fused quartz cassette Wafers Controlled air chamber to vent Resistance heater Fused quartz tubular furnace

9 Chemical Vapor Deposition (CVD) CVD is one of the most commonly used methods in depositing thin films on silicon or other substrates. Thin films build-up in MEMS is either necessary for required 3-dimensional geometry, or for accomplishing specific functions. Thin films made of silicon compounds including SiO 2 and metals such as Al, Ag, Au, Ti, W, Cu, Pt and Sn can be deposited on substrates using this method. CVD is also used to deposit unusual materials, e.g. SMA NiTi and piezoelectric materials such as ZnO for some MEMS devices. Working principle of CVD A selected reactant material is diffused in a carrier gas that flows over the hot substrate surface. The heat from the hot substrate surface prompt chemical reactions between the reactant and the carrier gas to form the desired thin film on the substrate surface. Carrier gases include O 2, NO, NO 2, CO 2 and H 2.

10 Reactors for CVD Resistance heater By-products and gas out Horizontal reactors Reactant and gas in Substrate Susceptor Substrates Vertical reactors Resistance heater Reactant and gas in To exhaust

11 Chemical reactions for common thin films by CVD For SiO 2 : Reactant is silane, SiH 4 SiH 4 + O 2 SiO 2 + 2H 2 at o C For Si 3 N 4 : 3SiH 4 + 4NH 3 Si 3 N H 2 at o C 3SiCl 4 + 4NH 3 Si 3 N HCl at 850 o C 3SiH 2 Cl 2 + 4NH 3 Si 3 N 4 + 6HCl + 6H 2 at o C For Polysilicon, Si by pyrolysis: SiH 4 Si + 2H 2 at o C

12 Rate of CVD CVD is a common way to produce thin films over substrates. The rate of production is of a prime concern to process and design engineers. Since CVD processes involve carrier gas flow over the substrate s surface, the issue of fluid/solid interface must be dealt with in assessing the effectiveness of CVD. Whenever a fluid flowing over a solid surface, a boundary layer is created: Reactant and gas flow x Hot silicon substrate x y Reactant and gas flow V(x) x G s δ(x) Hot silicon surface The boundary layer acts as a barrier to transfer of heat or transport of medium. Boundary layer In the case of CVD, the boundary layer plays a significant role in the rate of deposition. The thickness of the boundary layer over the substrate surface at a distance x from the leading edge can be evaluated by: δ ( x ) = x Re( x) Re(x) = Reynolds number at x x

13 Rate of CVD - Cont d It is apparent that the carrier gas and the reactant have to diffuse through the boundary layer in order to reach the substrate surface. The diffusion flux of the reactant, N ρ can be obtained by the expanded version of the Fick s law: ρ D N = δ ( ) N G N s where D = diffusivity of the reactant in the carrier gas (cm 2 /s) N G = Concentration of reactant at the top of the boundary layer (molecules/m 3 ) N s = concentration of reactant at the surface of the substrate (molecules/m 3 ) Example 8.4 on the determination of N G and N s (P.291) For most cases in CVD process, the carrier gas flows over the substrate surface at very low velocity, with Re < 100, this makes the diffusion of reactant through the boundary layer affected by the chemical reactions in the boundary layer and on the substrate surface. Consequently, the diffusion flux, N ρ in the above expression to be modified as: ϖ N = D N G k D+δ k where k s = surface reaction rate constant of the reactant on substrate surface. s s

14 Rate of CVD - Cont d The rate of thin film growth over the substrate surface can be obtained by the following expressions: A. For δ k s D : B. Forδ k s << D : γ r r D = N γδ N G = k γ G s in which = number of atoms (or molecules) per unit volume of the thin film. We may use the following expression for estimating the value of : 1 γ = 4 π 3 where a = radius of atoms or molecules of the thin film on the substrate surface. Example 8.5 on the estimation of the rate of SiO 2 thin film growth on silicon substrate using CVD. a 3 γ

15 Enhanced CVD The rate of CVD is affected by the following parameters: The temperature, T 3/2 The pressure, P -1 The velocity of carrier gas, V -1 The distance in the direction of gas flow, x 1/2 Of the above parameters, better performance of CVD can be achieved by either increasing the temperature and distance of gas flow, or by reducing the pressure and gas velocity. Increase temperature may result in adverse effect on the substrates due to incompatible CTE of the deposited thin films and that of the substrates. Reducing the gas velocity would result in non-uniformity of the deposition. A viable option on CVD enhancement is thus left to the reduction of pressure.

16 Enhanced CVD- Cont d Low-pressure CVD (LPCDV) LPCVD is a very popular CVD. It operates in vacuum at about 1 torr (1 mm of Hg). The reactor used for LPCVD is similar to that for APCVD (atmospheric pressure CVD) except the chamber is made leak-proof. LPCVD offers better quality thin film deposition with more uniform thickness than those by APCVD. RF source Plasma-enhanced CVD (PECVD) Unlike APCVD and LPCVD, PECVD can operate at relatively lower temperature, as the required energy for CVD is provided by RF plasma with RF at 3 KHz to 300 GHz. Lower operating temperature means less possibility of damaging the deposited thin films and the substrate. Electrode Resistance heater Substrates Rotating susceptor Heating elements PECVD usually operates at high vacuum for fast growth of thin films. Reactant and gas in Out to vacuum pump

17 Comparison of various CVD processes CVD Process APCVD LPCVD PECVD Pressure/ Temperature KPa/ o C 1-8 Torr/ o C Torr/ o C Normal Deposition Rates, (10-10 m/min) 700 for SiO 2 Simple, high rate, low temperature for SiO for Si 3 N for polysilicon for Si 3 N 4 Advantages Disadvantages Applications Excellent purity and uniformity, large wafer capacity Lower substrate temperature; fast, good adhesion. Poor step coverage, particle contamination High temperature and low deposition rates Vulnerable to chemical contamination Doped and undoped oxides Doped and undoped oxides, silicon nitride, polysilicon, and tungsten. Lowtemperature insulators over metals, and passivation.

18 Physical Vapor Deposition - Sputtering Unlike CVD, which operates at elevated temperature, the PVD (physical vapor deposition) operates at room temperature. PVD is used to deposit thin metal films in the order of 100 A ο (= 10-8 m) These metal films are often used as the pads for soldering electrical wires as shown below: Metal wire bond Metal layer Piezoresistors Insulation layer Silicon diaphragm Wire bond Metal layers Insulation surface Die bond: Adhesive Pressurized medium Constraint Base Metal leads Diffused piezoresistor PVD operates in similar principle as PECVD, in which the metal vapor is deposited on the substrate surface using carrier gas such as Argon gas. High vacuum in the order of 5x10-7 torr is involved.

19 Etching Etching is one of the most important microfabrication processes for MEMS and microsystems production. In opposite to vapor deposition, etching involves removing material from substratesthereby creates 3-dimensional geometry. There are generally two types of etching technologies available: (1) Chemical etching (or wet etching): Use chemical to dissolve the parts of material to be removed from the substrate There are: (a) isotropic etching, and (b) anisotropic etching. (2) Plasma etching (or dry etching): Use plasma containing high energy charge-carrying ions to knock off molecules in the part of the substrate. More detail description of etching will be given in Bulk Micromanufacturing.

20 SUMMARY 1. All microfabrication techniques are by physical-chemical means, which is radically different from traditional mechanical fabrication techniques. 2. Most of these techniques are imported from those used in microelectronics. 3. Photolithography is most critical in producing MEMS. It is the only way to establish patterns in micrometer scale on substrates. 4. Principal fabrication technique include: Ion implantation for doping piezoresistors at room temperature. Diffusion for more uniform doping but at elevated temperature. Oxidation for introducing thermal or electric insulation in substrates by either a wet or dry process. Both processes operate at elevated temperature. Chemical vapor deposition (CVD) deposit thin films of various materials on substrate surface, or on other thin films. APCVD at lower temperature but poor quality; LPCVD operates at high temperature and vacuum with good quality; PECVD operates at low temperature and high vacuum with good quality. Sputtering, or physical vapor deposition (PVD) deposits metallic thin films on substrate. Epitaxy deposition deposits thin films of same substrate materials. Etching removes materials from substrates at desirable locations. There are wet and dry etching processes available.

21 Etching

22 Isotropic etching Isotropic wet etching or Isotropic plasma etching means the chemistry (etchant or plasma gas) etches the substrates with total disregard for their crystal planes. It etches in all directions at the same rate. Etcha nts Protective Resist Etcha nts Substrate Etched Substrate (a) Substrate in wet etching (b) Partially etched substrate Isotropic etchants are available for oxide, nitride, aluminum, polysilicon, gold and silicon. Hydrofluoric acid (HF) is the most commonly used chemistry for silicon. Isotropic etching is not desirable in micromanufacturing because lack of control of the geometry of the finished product.

23 Anisotropic etching Silicon crystals are not isotropic in nature. Some planes are stronger and more resistant to etching chemicals than others. There are three planes in silicon crystal on which etching take place: z y x (100) plane (110) plane (111) plane The (100) plane is easiest to be etched, The (110) plane results in most clear etched surface, The (111) plane is toughest plane to be etched. The uneven resistance to etching chemicals by various planes in the silicon crystal result in different amount of materials that can be etched away using the same etching chemical for the same duration, as can be seen in the etching of a micro pressure sensor diaphragm.

24 Anisotropic etching-cont d One may prove that the (111) plane in a silicon crystal-the toughest plane to etching makes an off-normal angle of o angle with the (100) plane-the plane that is easiest to be etched. The complementary angle to the (110) plane is o. If etching is taken place on the (100) plane, I.e. in the normal direction of <100>, then we can expect having a cavity in the shape as follows: Unetched wafer: (100) Plane Wafer etched in the <100> direction (100) plane o Etched cavity <100> orientation

25 Etchants Etchants are the chemicals that dissolve or remove materials from substrates. Etchants in wet etching are chemicals in solvents, whereas etchants used in dry etching are plasmas that contains charge-carrying ions. Wet etchants for silicon substrates For isotropic etching: HNA (acidic agents, e.g. HF/HNO 3 /CH 3 COOH) at room temperature. For anisotropic etching: Alkaline chemicals with PH > 12. Popular etchants: Potassium hydroxide (KOH) Ethylene-diamine and pyrocatecol (EDP) Tetramethyl ammonium hydroxide (TMAH) Most wet etchants are diluted with water, normally 1:1 by weight.

26 Typical etching rates for silicon and silicon compounds Materials Etchants Etch Rates Silicon in <100> Silicon in <100> KOH EDP µm/min 0.75 µm/min Silicon dioxide Silicon dioxide KOH EDP nm/hr 12 nm/hr Silicon nitride Silicon nitride KOH EDP 5 nm/hr 6 nm/hr

27 Selectivity ratio of etchants to silicon substrates The selectivity ratio of etchants is defined as the ratio of etching rate of silicon to the etching rate of another material using the same etchant. It is of great importance to the process design engineers in selecting the suitable material for the mask used in the etching process. Selectivity ratio of etchants to two silicon substrates is given below: Substrates Etchants Selectivity Ratios Silicon dioxide KOH TMAH EDP Silicon nitride KOH TMAH EDP We notice that the selectivity of SiO 2 has selectivity ratio of > 10 3 that means that SiO 2 has more than 1000 time slower etching rate than that in the silicon substrate. This feature makes SiO 2 as less expensive but an attractive candidate material for using as an etching mask. Si 3 N 4 would have been a better choice for mask material, but it is more costly to produce than SiO 2.

28 Inadequate selection of mask material: The following undesirable situations may occur in etching with the use of improper mask materials: SiO 2 or Si 3 N 4 mask Etchants Silicon substrate SiO 2 or Si 3 N 4 mask Etchants Silicon substrate SiO 2 or Si 3 N 4 mask Etchants Silicon substrate (a) Ideal etching (b) Under-etching (c) Under cutting In general SiO 2 is used as a masking material with KOH etchant for relatively shallow trenches. Si 3 N 4 is used for etching processes for deep trenches, in which long periods in etching is a common practice.

29 Etch stop - a control of wet etching There are two ways the engineer can stop wet etching in silicon substrates: Dopant-controlled etch stop: In general, doped silicon can dissolve in etchants faster than the undoped silicon. Thus, one may dope the parts of the silicon substrate that need to be etched away faster than the other parts of the substrate. Electrochemical etch stop: Since doping in silicon may alter the etching rates in wet chemicals, we may use the p-n borders to slow down or stop etching, as illustrated in the following set-up: Inert substrate container Current adjustment V Constant voltage supply The electric current is used to prompt the functioning of the p-n junction. The difference in electric resistance in the p- and n-silicon produces the different etching rates for the control of the etching in the doped substrate. n-type silicon p-type silicon SiO 2 or Si 3 N 4 Masking Counter electrode

30 Dry etching of silicon substrates Dry etching involves the removal of substrate materials by gaseous etchants without wet chemicals or rising. There are generally 3 dry etching techniques: (1) Plasma. (2) Ion milling. (3) Reactive ion etch. Common practice, however, involves Plasma and Reactive ion etch. Relatively recent develop has been in the Deep Reactive Ion Etching, or DRIE. Dry etching of silicon substrates typically is faster and cleaner than wet etching. A typical dry etching rate is 5 µm/min, which is about 5 times faster than that by wet etching. However, dry etching requires more costly equipment. On the other hand, it is the only way to produce deep trenches with near-vertical side walls using the DRIE process, which is critical for many MEMS and microsystems components.

31 Plasma Etching Plasma is a neutral ionized gas carrying a large number of free negatively charged electrons and positively charged ions. Radio frequency (RF) is a common energy source for the production of plasma. To etch silicon or silicon-compound substrates, one needs to add chemically reactive gas, e.g. CCL 2 F 2 to the plasma. The added reactive gas produces reactive neutrals when it is ionized in the plasma. Both the reactive neutrals and the ions in the plasma carry high kinetic energies. They attack the substrate materials by bombarding the surfaces of the substrate as illustrated in the next slide.

32 Plasma etching process: The neutrals (N) produced by ionization of the reactive gas chemical in the plasma attack the substrate in all directions, with simultaneous chemical reactions with the contacted substrate material. The ions (+) in the plasma itself attack the substrate only in the normal direction. Etching of the substrate material is accomplished by instant local evaporation of substrate material after high energy impingement of (N)-neutrals and (+) ions. RF Source Mask Plasma with ions and reactive neutrals + + ions N N N N Reactive neutrals N N Etched substrate Plasma etching rate is in the order of 2 µm/min.

33 Common reactant gas chemical for plasma etching: Materials Conventional Chemicals Silicon and Silicon dioxide, CCl 2 F 2 SiO 2 CF 4 C 2 F 6 C 3 F 8 New Chemicals CCl 2 F 2 CHF 2 /CF 4 CHF 3 /O 2 CH 2 CHF 2 Silicon nitride, Si 3 N 4 CCl 2 F 2 CF 4 /O 2 CHF 3 CF 4 /H 2 CHF 3 CH 3 CHF 2 Polysilicon Cl 2 or BCl 3 /CCl 4 /CF 4 /CHCl 3 /CHF 3 SiCl 4 /Cl 2 BCl 2 /Cl 2 HBr/Cl 2 /O 2 HBr/O 2 Br 2 /SF 6 SF 6 CF 4 Gallium Arsenate CCl 2 F 2 SiCl 4 /SF 6 /HF 3 /CF 4

34 Rate and quality of plasma etching

35 Deep reactive ion etching (DRIE) for silicon substrates Many MEMS components, such as resonators and micro accelerometers require etching trenches in the silicon substrates with sufficient depth (H) and vertical side walls, i.e. θ 0 in the figure below to the right. Etched cavity θ Depth, H Substrate These trenches are of typically high aspect ratio (The ratio of the dimension in the thickness (H) to those of the surface). Wet etching and conventional dry etching could not accomplish deep etching with vertical walls.

36 MEMS of high aspect ratio using DRIE DRIE is the only etching technique that is capable of producing trenches with aspect ratio up to 300 and a near vertical walls at θ = 2 o. A micro spring

37 Working principle of DRIE DRIE works on a similar principle as the plasma etching. A major difference, however, is that DRIE involves the production of thin protective polymer films on the side walls during the etching process. These thin protective films prevent etching of the side walls. As result etching can only take place in the normal (the depth) direction in the trench. The DRIE process is illustrated below: Mask Plasma with ions and reactive neutrals + + ions N N N N N N N N Reactive neutrals DRIE etched substrate Thin protective polymer films

38 DRIE - cont d The reactants that can produce thin protective polymer films is fluoropolymers (ncf2) in the plasma Argon gas ions. The rate of DRIE is in the range of 2-3 µm/min. Examples of high aspect ratio of trenches produced by DRIE are: Sidewall protection materials Selectivity ratio Aspect ratio, A/P Polymer 30:1 Photoresists 50:1 100:1 Silicon dioxide 120:1 200:1 Depth of trenches at 300 µm with vertical walls at 2o were produced in silicon substrates.

39 Comparison of wet versus dry etching Parameters Dry etching Wet etching Directionality Good for most materials Only with single crystal materials (aspect ratio up to 100) Production-automation Environmental impact Masking film adherence Selectivity Materials to be etched Process scale up Cleanliness Critical dimensional control Equipment cost Good Low Not as critical Poor Only certain materials Difficult Conditionally clean Very good (< 0.1 µm) Expensive Poor High Very critical Very good All Easy Good to very good Poor Less expensive Typical etch rate Slow (0.1 µm/min) to fast (6 µm/min) Fast ( 1 µm/min and up) Operational parameters Control of etch rate Many Good in case of slow etch Few Difficult