An introduction to SiC power device research in the School of Engineering

Transcription

1 An introduction to SiC power device research in the School of Engineering Dr Peter Gammon 27 th April 2018

2 Power Electronics and the legacy of silicon.

3 MV AC HV AC Conversion AC-HVDC Conversion Siemens/TenneT HelWin 2 HVDC-AC Conversion AC-DC conversion on the majority of domestic appliances. 690 MW Wind Power 1 Coal powered Station Energy for around 900,000 homes

4 Power Conversion 90 % converter efficiency?? = 34% Wasted Energy (237 MW in German example)

5 Power Converter Efficiency DC AC Converter efficiency DC device efficiency AC AC DC

6 An ideal power semiconductor device On State: R ON = 0 V ON = Small, positive V I Limit = Off State: R OFF = V BD = I Leakage = 0 V BD = R ON = 0 Also: F SW =, P SW,P ON,P OFF = 0, T MAX =, = 0 Weight, size = 0, MTTF =

7 A real power semiconductor device On State: R ON > 0 V ON > 0 I Limit < Off State: R OFF < V BD < I Leakage > 0 R ON > 0 Also: F SW <, P SW,P ON,P OFF > 0, T MAX <, > 0 Weight, size > 0, MTTF < V BD <

8 Electric Field [V/cm] On-Resistance versus Breakdown voltage (Simple Diode) OFF-STATE To maximise breakdown voltage: + + P+ W D N- N+. V BD = W D E max,si W D qn D 2ε s E max,si Drift doping, N D, should be minimised V BD Drift Region width, W D, should be maximised W D X [cm]

9 On-Resistance versus Breakdown voltage (Simple Diode) ON-STATE To minimise resistance: + + P+ W D N- N+. R ON = W D AqN D μ n Drift doping, N D, should be maximised R ON Drift Region width, W D, should be minimised

10 On-Resistance versus Breakdown voltage (MOSFET) The same situation: W D To minimise resistance, Drift doping, N D, should be maximised Drift Region width, W D, should be minimised To maximise breakdown voltage, Drift doping, N D, should be minimised Drift Region width, W D, should be maximised

11 Unipolar Limit of Silicon The trade-off in W D imposes a material-based limit on all power devices. This unipolar limit of silicon imposes a minimum R ON achievable at each V BD. Bipolar devices cheat this limit by injecting charge, but suffer greater switching losses.

12 Unipolar Limit of Silicon

13 Silicon Carbide Efficient. Fast. Hot. Small.

14 Silicon Carbide Natural Oxide SiO 2 Wide Bandgap: 3.26 ev High Critical Electric Field: 2.2 MV/cm Very high Temp Performance ( potentially > 300 o C ) 4 Wafer cost > $2-5k

15 Another way Introducing the wide bandgap semiconductors To maximise breakdown voltage: V BD = W D E max,sic W D qn D 2ε s Si SiC GaN Bandgap, E G (ev) Critical Electric Field, E max (MV/cm) Thermal Conductivity (W/cmK)

16 Unipolar Limit of Silicon Carbide The increase in critical field imposes a new unipolar limit. Now, much lower R ON is possible at every V BD. Fast switching SiC unipolar devices can now compete with slow Si bipolar devices.

17 Unipolar Limit of Silicon Carbide

18 A brief history of Silicon Carbide Until 2002 the SiC material quality was not good enough for commercial device manufacture. In 2002 SiC Schottky diodes became commercially available, MOSFETs followed in Both are commercially available from V.

19 A brief history of Silicon Carbide Now, the market is growing

20 A brief history of Silicon Carbide and the applications are becoming more and more exciting. ROHM supplies Full SiC Power Modules to Formula E racing team Venturi

21 Silicon Carbide: Outstanding Challenges Several challenges remain before SiC will achieve major market penetration. These include: Long term reliability, particularly in terms of the MOSFET gate. Development of high voltage devices ( 3.3 kv), particularly bipolar devices (IGBT, thyristors). Development of devices for harsh environment. Reduction of defects in substrates and epitaxy processes; development of 3C-SiC. Scaling up of wafers to 200mm diameter; the reduction of substrate/epi cost. Industry adoption, achieved through increased case studies, demonstrators, mainstream articles and reduction in cost.

22 Silicon Warwick

23 Silicon Carbide Projects at Warwick Developing bipolar SiC devices, such as IGBTs. >15kV SiC IGBTs are being developed for grid applications. Unconventional processing is required to develop the materials due to no available P+ substrates. Only 4 groups worldwide have ever developed these, none yet in the EU. Significant IP generation expected. Underpinning Power Electronics: Switch Optimisation Theme EPSRC Project: EP/R00448X/1 Warwick Team: Peter Gammon (PI), Phil Mawby, Tianxiang Dai, Guy Baker. With Cambridge, Newcastle and Coventry Universities

24 Silicon Carbide Projects at Warwick Improving SiC epitaxial growth processes. SiC materials focus: developing >30 kv rated materials >30 kv devices (Schottky, PiN, MOSFET) to be developed with large areas for large current capability. Switching efficiency improvements by improving materials carrier lifetime >10 µs. Feeds back into SiC materials chain, allowing practical mass production. Industrial exploitation expected. Ultra-high voltage (>30 kv) power devices through superior materials EPSRC Project: EP/P017363/1 Warwick Team: Vishal Shah (PI), A. Ben Renz. With Dynex Semiconductor and Cambridge Microelectronics

25 Silicon Carbide Projects at Warwick Improving the long term reliability of SiC power devices. Predicting device failure and managing the remaining usable life of a power converter Developing technologies that can improve the reliability of SiC power devices and monitor their health on-line De-risking SiC uptake in conservative applications: automotive, traction, aerospace, and grid connected converters Underpinning Power Electronics: Reliability and Health Management EPSRC Project: EP/R004366/1 Warwick Team: Layi Alatise (PI), Li Ran, Jihong Wang, Jose Ortiz Gonzalez. With Bristol, Newcastle and Nottingham Universities

26 Silicon Carbide Projects at Warwick Developing the 3C polytype of SiC. 3C can be grown directly on Si, lending itself to mass production. Its 2.3eV bandgap lends itself to MV applications such as automotive Warwick involved with the design of novel V device architectures. Development of Gate Oxide Reliability test methods H2020 Project: Warwick Team: Mike Jennings (PI), Phil Mawby, Fan Li. 13 Partners in total incl. CNM-IMM, ST Microelectronics and Silvaco

27 Silicon Carbide Projects at Warwick Developing SiC devices for Space Applications. Si-on-SiC substrates developed to exploit both materials. Highly radiation tolerant design. Designed for use in Space missions and satellites Source P+ N+ Gate Field Oxide N+ Drain P body N drift region (linear-doped) New H2020 grant recently submitted developing all-sic power devices for Communication Satellites. Semi-insulating 6H-SiC Substrate Si on SiC for the Harsh Environment of Space (SaSHa) Potential 15% weight saving using all SiC H2020 Project: power conditioners. Warwick Team: Peter Gammon (PI), Fan Li, Chunwa Chan With Cambridge Microelectronics, UCL Belgium and Tyndall Ireland

28 Future Silicon Carbide Projects at Warwick Scale it up 10, 15, 25kV 100, 500, 1000 A Warwick Send it to Space High Rad, High Rel Novel Devices Bidirectional switch, Circuit breakers Ga 2 O 3? Diamond? Al 2 O 3? 2018 on Wireless Power Transfer Power + GHz

29 Silicon Carbide On Tour.

30 Silicon Carbide Facilities at Warwick 2m Class 1000 cleanroom built in 2010 and extended in High temperature SiC furnace <1600 o C Several tube furnaces and RTA annealing ICP/RIE Etcher TEOS Furnace Metal evaporator and sputterer Several wet benches

31 Silicon Carbide Facilities at Warwick ISO class-8 packaging cleanroom built in ATV SRO-704 Solder reflow / thermal processing / RTA oven. Cammax Precima EDB65 eutectic pick and place die bonder Dage Series 4000 bond tester Orthodyne model 20 wire bonder Mascoprint S200HFC semi- automatic screen printing

32 Silicon Carbide Facilities at Warwick State of the art Characterisation Facilities. Brand new probe station and parameter analyser capable of electrical characterisation on-chip and in package: up to 10kV/500A up to 300 C Cryogenic characterisation down to 20 K. 20kV Inductive Switching Test Rig Power Cycling Test rig Physical characterisation in MAS building, including TEM, AFM, FIB, AFM, XPS, XRD techniques.

33 Silicon Carbide Facilities at Warwick Material Growth UK s only SiC CVD Reactor installed in Industry standard; Sizes up to 150mm wafer Thin, thick and super thick epitaxial layers Multilayer (p (Al) and n (N)) in one run Reduced pressure process capability Hi temperature robotized handling Industry s shortest heat up / cool down Growth rate: up to 90 µm/h

34 Silicon Carbide Over and Out.