A Wafer Level CSP based on a Low Cost Electroless Redistribution Layer

Transcription

1 A Wafer Level CSP based on a Low Cost Electroless Redistribution Layer Thomas Oppert, Thorsten Teutsch, Elke Zakel, Pac Tech Packaging Technologies GmbH Am Schlangenhorst D Nauen, Germany Phone: +49 (0)3321/ Fax: +49 (0)3321/ oppert@pactech.de Abstract A driving force to achieve increased speed and performance along with higher I/O count is the Flip Chip (FC) Technology which has therefore an high level of importance for a variety of applications. A breakthrough, however, will be the use of flip chip due to cost reduction. For this aim it is essential to use low cost bumping techniques. However, to provide FC technologies also for devices with high I/O count and high pin density applications like Microcontrollers, RAMBUS devices, etc... it is necessary to redistribute the historically peripheral bond pads with ultra fine pad pitch into a wafer level CSP. This paper describes a low cost electroless Ni/Au Under Bump Metallization (UBM) and a wafer level redistribution process based on electroless copper circuitization. It includes the use of a novel plasma enhanced chemical vapour deposition (PECVD) process to deposit a bifunctional nano-layer acting as an adhesion promotor and as a catalyst for electroless copper deposition. The described techniques are suitable for all wafer passivation types, which are used in industry today. The complete redistribution process is based on batch processing and less masking and photoimaging steps. By using the electroless Nickel process and wafer level stencil solder printing the process is highly cost efficient and has large volume manufacturing capability. Results and also reliability measurements will be presented. Finally a roadmap regarding the implementation of this process into backend high volume production is shown. Introduction There are two major reasons, which will make it necessary to redistribute an existing device layout: 1) Due to the dualism between FC and wirebond assembly techniques most of the available device types will have a peripheral pad layout, which will lead to ultra fine pitch structures on devices with high I/O count, such as microprocessor, etc. Standard low cost bumping techniques using solder reflow for assembly can not fulfill the requirements of bumping these tight pitches, which are below the process limitations of all commercially available solder bumping techniques. Also the PCB technology is not able in these days to deliver low cost boards (FR4, FR5) for these applications. A pad redistribution into an area array layout will increase the pitch and provide FC optimized and FC capable dies. 2) The second reason to redistribute a chip is the possibility to design and manufacture a wafer level CSP, which has advantages compared to standard COB assembly techniques. The increase in reliability due to the larger gap between chip and substrate and the reduce of manufacturing costs, in cause of the absence of an underfilling process. For nearly all existing FC techniques - also for the redistribution process - a bump formation on the chip I/O is needed. Established techniques like the C4 process [1,2] do not fulfill the cost requirements for the consumer market. A selective chemical plating method can reduce bumping cost significantly since it does not require masking or metal sputtering. Additionally this technique easily allows a parallel processing of multiple wafers, leading to a high throughput. The special cost advantage of electroless Ni is given by the possibility of parallel batch processing. Fig. 1 shows a batch of wafers which are processed in parallel.

2 been proven in a series of published technical papers [3,4,5]. Figure 3 shows electroless Ni/Au as a basis for Anisotropic Conductive Adhesive (ACF) Flip Chip Assembly, for polymeric Flip Chip Assembly (Conductive Adhesive) and for soldering and direct chip attach type of applications using different solder alloys. Electroless Ni/Au UBM Fig. 1: Wafers in parallel batch processing It was shown earlier [3] that parallel electroless Ni processing is capable up to 300 mm wafers, which will bring additional cost advantages: no specific equipment or additional invest is needed (Fig.2). Fig. 2: Automatic Electroless Nickel/Au Bumping Line In the FC assembly Ni/Au bumps are used as an UBM for solder applications. Besides of this the Ni can also offer a stand-off, e.g. for chip on glass (COG) using ACF [5]. The feasibility and reliability of this bumping process has Anisotropic Conductive Adhesive Polymer Flip Chip Technology (Conductive Adhesive) Flip Chip Solder Interconnection possible alloys: SnPb63/37 PbSn95/05 AuSn80/20 leadfree solder of next generation Fig. 3: Electroless Nickel/Au UBM - for different Flip Chip Assembly Processes Regarding the low cost wafer level redistribution, it is especially the ultra fine pitch capability of electroless Nickel which will be recommend itself as the ultimate solution of an universal UBM formation for a rewiring process. The connecting redistribution traces and the redistributed bond pads will be processed in an semiadditive process by using electroless Cu plating on a special photodielectric. Due to the selective plating capability of Electroless Ni/Au on Al and Cu, Ni bumps can be used as an UBM on the redistributed Cu pads, too. After solder reflow (Bumping and FC Assembly) the Ni/Au bumps fulfill the following function. They protect the Al or the Cu and act as an adhesion layer and a diffusion barrier and guarantee a stable and reliable contact to the Al or redistributed Cu bond pads [4]. Summarizing all this advantages and capabilities it becomes very reasonable, that electroless Nickel as an UBM is a key process for a low cost wafer level redistribution process. Additionally it is necessary to reduce the manufacturing costs of the complete redistribution process, by using low cost techniques for Cu plating and less photomasking and serial process steps.

3 Backend Processing Probed Wafer Ni/Au Bumping & Redistribution The equipment available for these standard processes based on large work pieces or printed circuit boards is not suitable for wafer bumping. In order to fulfill the specific requirements for wafer bumping a new modular electroless Ni wafer bumping line has been developed. Each module can take batches of 50 wafers 8" or 10 wafers 12". Such processing is a key to the extremely high throughput of this bumping line which again determines the overall cost of the bumping process. Electroless Ni/Au Bumping FCOB or CSP Backside Coating Aluminium Cleaning Test/ Burn In Zincate Pretreatment Ship to customer Fig. 4: Electroless Ni/Au and wafer level redistribution in backend processes Figure 4 shows a possibility to integrate electroless bumping and wafer level redistribution in backend processes. Electroless Ni/Au bumping The electroless Ni/Au bumping is a wet-chemical and maskless process. With the developed manufacturing process all types of wafers can be bumped with a standard process in excellent quality. In a special designed bumping line wafers, from 4 (100 mm) to 12 (300 mm) diameter can be plated [3,7]. The key for a successful, reproducible and reliable manufacturing process is in the used chemicals and equipment. The electroless Nickel bumping process can be performed with standard chemicals available on the market for simple test structures and test dies without electrical inner circuitry. However, when applied to functional wafers with complex inner electrical structures, different metallization and different passivations, the process requires specific proprietary chemical compositions and know how for a reproducible and reliable result. Here is the key to electroless Nickel implementation in production. This is an explanation for the multitude of investigations and research projects in industry and in institutes which did not lead to a direct manufacturing process in the past. Electroless Nickel is used in industry for a wide range of applications in which Al work pieces are plated with Ni. Electroless Ni Immersion Gold Coating Removal Fig. 5: Process Flow of electroless Ni/Au- Before the wafers can be metallized in the line the wafer backside has to be covered by a stable resist prior to the chemical bumping process. The next step is a treatment of the pads in an Al cleaner which removes oxide layers while the Al surface is micro-etched. The pretreatment is done in the first modules of the line. An alkaline zincate solution is used for activating the Al surface. For the electroless Ni plating a bath based on sodium hypophosphite is used. The rate of Ni deposition is 20µm/h. A final Au coating on the Ni is necessary to prevent oxidation and enables long-time solderability of bumps. With this Au coating a maximum Au thickness of 0.25µm can be achieved (typ. 0.05µm). The complete process flow is shown in figure 5. The quality of bumps is controlled by optical microscopy, profilometer measurements and shear tests. For detailed analysis crosssectioning, SEM and EDX are used.

4 Feature Wafer size Wafer backside Pad geometry Acceptable Range 4 (100 mm) 12 (300 mm) Any Any (square, rectangular, round) Pad size > 40 µm for production (>10 µm for prototyping) Pad spacing 2x bump height + 10µm for production (>5 µm for prototyping) Fig. 6: Ultra fine pitch bumping (Pitch: 50µm) The minimal bump height is 1µm to have a closed and voidless Ni-Layer. The maximal height is limited by the pad to pad spacing. The bump height must not be larger than ½ pad spacing minus 5µm to avoid short circuits between neighboring pads by over-growing Ni. A height of 5µm is recommended for FC soldering. Figure 6 shows a part of an electroless Ni/Au bumped Wafer with a pad pitch of 50µm. This meets the requirements of reliability and fast processing. The adhesion of the bumps on the Al pads depends on the pad area. For 100 x 100 µm pads the shear strength is at least 100g. Bump characteristic Recommended height for FC Soldering Maximum height Specification 5 µm Material NiP 10% Resistivity Hardness Adhesion to Al 100x100 µm² pad ½ pad spacing -5µm 70 µωcm 550 mhv >100g (typ.150g) Au coating thickness µm Tab. 1: Characteristics of Ni/Au Bumps The uniformity of bump height is ± 2% on 4 (100 mm) wafers, ± 4 % on 8 (200 mm) wafers and ± 5 % on 12, which is sufficient for nearly all types of applications. Detailed data on the reliability of the Al/Ni interface was published [4]. The Ni/Au bump characteristics are summarized in table 1. Metallization Al thickness Wafer probing Passivation scribeline AlSi 1%, AlSi 1% Cu 0.5% or AlCu 2% 1 µm for production (0.5 µm for prototyping) Before or after Ni/Au plating Defect-free nitride, oxide, polyamide, without any residues on the pads Isolated (test pads acceptable) Tab. 2: Design rules for the Ni/Au bumping process For achieving reliable and reproducible results regarding the electroless Ni/Au bumping of several types of wafers from 4" up to 12", design rules have been defined. As pad materials AlSi 1%, AlSi 1% Cu 0.5%, AlCu 2% and other alloys of these metals were investigated. All types have been processed with good results. Nevertheless there are some restrictions on the wafers to be Ni bumped. The Al bondpad thickness should be 1µm or more in order to have sufficient Al after cleaning and activation. There are no limits to passivation thickness but the passivation must be free of defects. Cracks cause a growth of Ni which can produce short circuit. This will also occur on parts of a wafer surface which were scratched by improper handling. Ni also grows on Si which is not covered by an oxide or passivation layer. Unprotected Si in the wafer scribe line will cause plating of a Ni layer with low adhesion. Therefore the scribe line should be almost insulated, except for defined process control structures. A summary of the wafer design rules is shown in table 2 [7]. All these results and requirements can be transferred to electroless Ni/Au bumping on Cu pads. Of course the Ni/Au process has to be modified, especially the pretreatment and activation processes have to be changed for bumping on an other bond pad metallurgy. The new electroless Ni/Au on Cu process will be qualified together with the redistribution process within the

5 Full Area Copper Deposition next few months by doing the necessary reliability investigations. Wafer Level Redistribution ElastoPAC To start with the wafer level redistribution a redistribution design has to be made first. Fig. 8: Process flow for Wafer Level Redistri-bution (Photomasking steps in red) Fig. 7: Redistribution Layout for Pac 2.1 Test Wafer As an example and a test vehicle Pac Tech s 4 inch test wafer Pac2.1 with a peripheral layout of 200 micron pitch and a PSG passivation was used. Figure 7 shows the redistribution design for the Pac 2.1 test wafer. Initially the redistribution starts with Ni/Au bumping of the Al bond pads up to an Ni height of 5 µm (Fig. 8). Then a epoxy based dielectric is spinned on the existing wafer passivation. The mechanical and electrical properties of the dielectric are listed in table 3. Dielectric characteristic Specification Material Epoxy based Thickness 10 µm PbSn Dielectric Constant 1 MHz: 4.1 Soldermask 1 GHz: 3.4 Interposer Insulating Resistance Ω Passivation Ni/Au-Bump Al-Pad Redistribution (Cu) Si CTE ppm/ C Fig. 9: Cross section of wafer level redistribution T G C Water Absorption < 0,5% Tab. 3: Characteristics of Photodielectric Ni/Au - Bumping of Bond Pads Spinning of Dielectric Layer Photo Imaging: Opening of Ni/Au Bond Pads Wafer passivation material can be SiN, SiO 2, PSG as well as PI. Additionally to our standard dielectric BSC and PI is currently under evaluation. For full area copper deposition a seed layer formation will be followed by an electroless Cu plating batch process. There are two prerequisites of electroless copper metallization of a dielectric material. First, adhesion must be obtained and second, proper catalytic activation has to be achieved. The seed layer generation takes place as a gas phase plasma process (PECVD). Therefore, a plasma reactor with a parallel plate design and a RF-powered circular substrate electrode is used. This process is developed by Atotech for Formation of Seed Layer

6 direct metallization of dielectrics for future requirements in PCB industry [6] and specially adapted for wafer applications. Figure 10 shows a scheme of the PECVD chamber and gives the standard plasma parameters. Fig. 11: Cu Redistribution Layer Solder bump formation can be done by solder stencil printing, where an automatic printing machine is used. Typical solder paste are Pb37Sn63 alloys with particle sizes below 20 µm. The stencil apertures are adapted to the specific application. The volume of the printed paste is determined by the aperture diameter and stencil thickness. The selection of appropriate stencil geometry is essential for printing with high yield. Special design rules have been developed for this process [7]. The subsequential solder is reflowed and flux residues are cleaned. The solder volume after reflow will be approx. 50% of the paste volume. Figure 12 shows printed solder paste after reflow in a pitch of 180 µm. Fig. 10: Scheme of the PECVD chamber The plasma metallization consists of three different steps. In a first pretreatment step the dielectric is conditioned by plasma without roughening the surface in contrast to wet chemical processes. The second step is the deposition of a 5-10 nm thick transition metal layer by PECVD. In a subsequent third step, this catalytically active seed layer activates an electroless copper metallization bath. This direct metallization by PECVD is applicable to a wide range of polymers which are used as dielectric in electronic industry like PI, epoxy resins or even fluoro polymers for high-frequency applications. It leads to very strong polymer-metal adhesion without roughening of the polymer surface. E. g. on PI adhesion of more than 20 N/cm (peel off test) is reachable. The Cu becomes structured by an photomasking and etching process. At least the surface is covered by an solder mask and the opened Cu bond pads are NiAu bumped again. The results of the Cu redistribution Layer for our test vehicle is shown in figure 11. Fig. 12: Stencil printed Solder Bumps Figure 9 shows a detailed cross section drawing of the complete redistribution layers. Wafer Level CSP ElastoPAC To implement the wafer level redistribution into a wafer level CSP it is necessary to increase the solder bump height. Pac Tech is using a propriety process, which cannot be shown in detail at the moment. Essentially it is necessary to use techniques like LS 2 and SB 2 for solder ball attach [8,9]. The LS 2 process, like it is shown in figure 13, combines 2 techniques: 1) solder ball gang placement by using a stencil 2) solder ball reflow by using a laser scanner The advantages due to stencil printing are, the possibility to apply a higher solder volume on the redistributed pads and the much easier and more efficient flux cleaning compared to an oven reflow, because of the only locally applied laser energy, which will not effect the

7 flux residues beneath the solder spheres. An additional advantage of a ElastoPAC as a wafer level CSP is that for encapsulation halogen-free components can be use. The SB 2 is used for repair of sites with missing or bridged balls. Figure 14 shows stencil printed SnAg4Cu0,5 solder bumps after reflow and flux cleaning on a layout with 250 µm pitch. 200µm pitch is currently under development. Lead-free bump characteristic Data Chip Ball Placement Shear force 96,75 g Standard deviation 5,24 g Laser Shear mode Bulk solder Scanner TCU Bump height 101 µm Chip Laser Detection + Laser Reflow Standard deviation 1.72 µm Cleaning result Excellent Camera Pad size 100 µm Chip Laser Ball Placement SB² Chip Optical Inspection Hs3 Automatic integrated Repair with SB² Fig. 13: LS 2 Ball Gang Placement and Laser Reflow [9] The whole process is comparable due to cost and process time with the stencil printing technique. Lead-free Solder and environmental Aspects Concentrating on the material aspects there are a lot of different opportunities due to the usage of different solder materials as well for the wafer level redistribution as for the wafer level CSP. In the case of the LS 2 or SB 2 solder application for CSP it is easy to understand that different solder alloys, especially lead-free solder, can be imple-mented without any further process development or additional costs only by using the commercially available solder balls of the specific alloys. On the other hand lead-free solders, which are currently not available for ultra-fine pitch stencil printing, can than used for solder printing of the redistributed wafers, in cause of the increased and now suitable pitch. Preliminary results of lead-free solder printing are presented in the following. Fig. 14: Reflowed SnAgCu solder Bumps Tab. 4: Results of lead-free solder stencil printing The result is shown in figure 14 and the measured data is summarized in table 4. SnAg3,5 solder paste is also tested and for prototyping quantities available. The results are comparable with SnAgCu. The transfer of this process on redistributed surfaces will be done and reliability results will be available soon. Summary and Outlook A new low cost wafer level redistribution process was presented. Using eletroless Ni as a key technology the process fulfills together with other wet chemical batch plating techniques, like electroless Cu, and the less masking steps the requirements of a low cost process. Further advantages of electroless Ni are the selective plating on Al and Cu bond pads and the ultra fine pitch capability. The epoxy based photodielectric makes the process capable for all wafer passivation types, which are used in industry today and offers as a plating base a reliable adhesion for the Cu redistributed bond pads and circuits. The PECVD deposition of the seed layer for electroless Cu plating opens due to the flexibility of the process beside high adhesion also perspectives for the metallization of future polymer dielectrics. Solder application can be done by stencil printing and in the case of an wafer level CSP by LS 2 method. The advantage of using LS 2 due to solder alloy flexibility and reliability aspects was pointed out. In the near future reliability data on all of the presented new techniques will be available: - Reliability tests for high melting lead-free solder compounds stencil printed on Ni/Au UBM for automotive applications are under performance

8 - Redistribution of 2 sensor devices followed by assembly and thermal cycling investigations are under preparation and will be available in Q2/ Ni/Au on Cu is already available for prototyping services and will be qualified on customer products soon References [1] De Haven, Dietz, Controlled Collapse Chip Carrier (C4) an Enabling Technology, Proceedings of the 1994 Electronic Components and Technology Conference (44 th ECTC), Washington D.C., pp [2] L. F. Miller, Controlled Collapse After Reflow Chip Joining, IBM J. Res. Develop., Vol. 13, pp , May, [3] T. Oppert, T. Teutsch, E. Zakel, D. Tovar, A Bumping Process for 12" Wafers, Proceedings of the International Electronics Manufacturing Technology Symposium (24 th IEMT), Austin TX, pp , October 18-19, 1999 [4] T. Oppert, E. Zakel, T. Teutsch, A Roadmap to Low Cost Flip Chip and CSP using Electroless Ni/Au, Proceedings of the International Electronics Manufacturing Technology Symposium (IEMT) Symposium, Omiya, Japan, April 15-17, 1998 [5] M. Vrana, J. De Baets, A. Van Calster, D. Wojciechowski, A. Ostmann, H. Reichl, An Anisotropic Adhesive Flip Chip Technology for LCD Drivers, Proceedings of the SID Conference 1996 [6] R. Heinz, E. Klusmann, H. Meyer, R. Schulz, PECVD of transition metals for the production of high-density circuits, Surface and Coatings Technology (1999) [7] Pac Tech Webpage: [8] P. Kasulke, W. Schmidt, L. Titerle, H. Bohnaker, T. Oppert, E. Zakel, Solder Ball Bumper SB 2 -A flexible manufacturing tool for 3-dimensional sensor and microsystem packages, Proceedings of the International Electronics Manufacturing Technology Symposium (22 nd IEMT), Berlin, April 27-29, 1998 [9] G. Azdasht, L. Titerle, H. Bohnaker, P. Kasulke, E. Zakel, Ball Bumping for Wafer Level CSP - Yield Study of Laser Reflow and IR-Oven Reflow, Proceedings of the Chip Scale International, San Jose CA, September 14-15, 1999