CMOS Processing Technology

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1 CHAPTER 2 CMOS Processing Technology

2 Outline 2 1. CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues

3 CMOS Technologies 3 n-well Process : p-substrate p-well Process : n-substrate Twin-well Process Optimized for each transistor type Triple-well Process (deep n-well) Good isolation between analog & digital blocks BiCMOS Process (SiGe) Silicon-on-insulator (SOI) Process

4 Process Steps 4 Wafer formation Photolithography Well and Channel formation Isolation Gate oxide Gate & Source/Drain formation Contacts & Metalization Passivation

5 Photolithography 5 Greek: Photo(light)+lithos(stone)+graphe(picture) Resolution enhancement techniques Optical proximity correction (OPC) : local distortion, Phase shift masks (PSM): light diffraction, Off-axis illumination (OAI): contrast enhancement of repetitive pattern. Carving pictures in stone using light

6 Well and Channel Formation 6 Vary portions of donor(n) & acceptor(p) Epitaxy: single-crystal film growth Deposition: Chemical Vapor Deposition (CVD) + Drive-in Implantation: ion implantation + diffusion + anneal (standard well and source/drain definition)

7 Schematic and Layout of CMOS Inverter 7

8 Cross Section of CMOS Inverter 8

9 Photomasks of n-well CMOS Inverter 9

10 n-well CMOS Process (a) Define n-well diffusion (mask #1) (b) Define active regions thin oxide (mask #2) (c) LOCOS oxidation field oxide (d) Polysilicon gate (mask #3)

11 n-well CMOS Process (e) n+ diffusion (mask #4) (f) p+ diffusion (mask #5) (g) Contact holes (mask #6) (h) Metallization (mask #7)

12 Cross-Sectional Diagram of MOSFET 12

13 Silicon Dioxide (SiO 2 ) 13 Wet oxidation Oxidizing atmosphere contains water vapor, Temp: 900~1000 o C, quick for thick oxides. Dry oxidation Oxidizing atmosphere is pure oxygen, Temp: ~1200 o C, highly controlled thin oxides. Atomic layer deposition Thin chemical layer deposition for various requirement (SiO 2, metal, dielectrics)

14 Isolation : LOCOS 14 LOCOS : Local Oxidation of Silicon Low density, high electrical field : bird s beak

15 Isolation : STI 15 STI : Shallow Trench Isolation High density & better isolation, need Chemical Mechanical Polishing (CMP) to planarize the structure.

16 Gate Oxide 16 Shorter gate L thinner gate oxide EOT : Effective Oxide Thickness Use stack gate structure with high-k dielectric to decrease EOT. Dual gate oxide for core and I/O.

17 Gate & Source/Drain Formation 17 Self-aligned polysilicon (poly) gate Lightly doped drain (LDD) structure

18 LDD & Salicide 18 LDD Reduce electrical field of drain junction & hot-electron damage High sheet resistance Salicide : self-aligned silicide Refractory metal to reduce the interconnection resistance of gate, source/drain. CMP : Structure planarization for further stack process.

19 Chemical Mechanical Polishing (CMP) 19

20 Contacts & Metallization 20 Contact VIA Metal Poly, Metal Diffusion Metal Metal CMP : Structure planarization for further stack process.

21 Outline CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues

22 Layout Design Rule 22 Design rule: geometric constraint and tolerance for high probability of correct fabrication. Feature size, separations and overlaps. Well rule : isolation Transistor rule : channel quality Poly, active region, n+/p+ implant. Contact : single size for precisely process control Metal & Via rule: productivity & conductivity Top metal with loser size, space and via rules.

23 N-well Process Transistor 23

24 Design Rule 24

25 Micron Design Rule 25

26 Outline CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues

27 CMOS Process Enhancement 27 Multiple threshold voltage & oxide thickness Low core voltage for low power High I/O voltage for interface compatibility Silicon on Insulator : higher speed High-K gate dielectrics : thinner EOT Higher mobility : SiGe BJT, strained silicon Low-leakage transistor : finfet, gate-all-around (GAA) FET Plastic Transistors : flexible electronic paper High-voltage transistor : LCD driver, power electronics Copper interconnection : high conductivity Low-K dielectrics : low wire capacitance

28 Silicon on Insulator 28 Pros. No capacitance between source/drain and body higher speed device. No Latch-up. Cons. Floating body history effect Self heating effect. Parasitic BJT pass-gate leakage

29 High-K & Higher Mobility 29 SiGe bipolar transistor Strained Silicon High-K + Metal Gate Mark Bohr, The New Era of Scaling in an SoC World, Plenary session, ISSCC 2009

30 FinFET & GAA Structure 30 Mark Bohr, The New Era of Scaling in an SoC World, Plenary session, ISSCC 2009

31 Transistor Scaling 31

32 Intel Technology Trend 32

33 Plastic Transistor 33 Electronic Paper Plastic transistor structure & process flow

34 Copper Interconnect 34 Copper atoms diffuse into the silicon and dielectrics, destroying transistors Barrier layers are necessary The processing required to etch copper wires is tricky. Copper oxide forms readily and interferes with good contacts. Care has to be taken not to introduce copper into the environment as a pollutant

35 Copper Damascene Process 35 Pros. : High conductivity Cons. :Complex process

36 Capacitors 36 MiM Capacitor Fringe Capacitor

37 MIM vs. MOM 37 Metal-Insulator-Metal Need extra layer More routing capability Metal-Oxide-Metal Free with modern process More layers : higher density

38 Resistor & Conductor 38 Non-silicide high-resistivity Poly resistor Planar spiral Inductor

39 Memory Category 39

40 Non-Volatile Memory (NVM) 40 Mask-programmed ROM (Read-Only Memory) NOT programmable after manufacture. One-Time Programmable (OTP) memory Fuse constructed programming flow EPROM: Electrically Programmable ROM Electrical Programming, UV Erase EEPROM: Electrically Erasable PROM Electrical Programming & Erase, Byte-level programming. Flash Block-level programming, faster & cheaper than EEPROM

41 Flash Memory 41

42 BJT in CMOS Process 42 Usage : bandgap voltage reference

43 MEMS 43 Micro Electro Mechanical Systems (MEMS) Comb drive Actuator

44 Carbon Nanotube (CNT) Transistor 44 IBM CNTFET Smaller channel length Higher speed Lower power Better electrical performance than Si but complex process

45 Outline CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues

46 Design Rule Check (DRC) 46 Tolerate nonideal effects and guarantee device successful fabrication: Mask alignment error Shift SiO 2 PMOS Region SiO 2 SiO 2 PMOS Region SiO 2 n well n well p substrate p substrate SiO 2 p+ Poly SiO 2 SiO 2 p+ Poly SiO 2 p+ p+ n+ p+ p+ n+ n well p substrate Short n well p substrate Ex: alignment of N well and active region masks

47 Design Rule Check (DRC) 47 Exposure and etching variation Ex: different contact windows different contact resistance Contact widows SiO 2 SiO 2 P+ P+ N+ N well P substrate Two types of design rules Poly overlap Resolution Minimum width Minimum spacing Contact overlap Poly-diff. spacing Alignment Poly-contact spacing Contact overlap

48 Design Rule Check (DRC) 48 Minimum channel width CO.W CO.E.1 Minimize S/D diffusion width (x d ) CO.W.1 + CO.E.1 + CO.C.1 x d x d

49 Layout v.s. Schematic (LVS) 49 Guarantee the layout is the same as the simulated netlist Check device parameters, interconnections and i/o ports. Model name Channel width Channel length VDD VDD VI VO VI VO GND GND

50 Parasitic Extraction (PEX) 50 Evaluate interconnection RC effects VDD VDD VDD VDD VI VO VI VO VI VO VI VO GND GND GND GND Only C effect Only R effect

51 Gate Layout Slide 51 Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology V DD and GND should abut (standard height) Adjacent gates should satisfy design rules nmos at bottom and pmos at top All gates include well and substrate contacts

52 Example: Inverter Slide 52

53 Simplified λ-based Design Rules 53

54 Example: NAND3 54 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 l by 40 l

55 Stick Diagrams 55 Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers

56 Wiring Tracks 56 A wiring track is the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track

57 Well spacing 57 Wells must surround transistors by 6 l Implies 12 l between opposite transistor flavors Leaves room for one wire track

58 Area Estimation 58 Estimate area by counting wiring tracks Multiply by 8 to express in l

59 Example: O3AI 59 Sketch a stick diagram for O3AI and estimate area Y A B C D

60 Example: O3AI 60 Sketch a stick diagram for O3AI and estimate area Y A B C D

61 Outline CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues

62 Antenna Rules 62 Maximum area of metal connected to gate without discharge element

63 Layer Density Rule 63 CMP & Uniform etch process requirement : Planarization Solution : Pattern Fill (by CAD) Reference: