Make sure the exam paper has 9 pages total (including cover page)

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1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2010 EE143 Midterm Exam #2 Family Name First name SID Signature Solution Make sure the exam paper has 9 pages total (including cover page) Instructions: DO ALL WORK ON EXAM PAGES This is a 90-minute exam (4 sheets of notes allowed) Grading: Please be concise with your answers. For answers requiring explanation, adding sketches can be very effective. To obtain full credit, show correct units and algebraic sign. Numerical answers orders of magnitude off will receive no partial credit. Problem 1 (25 points) Problem 2 (30 points) Problem 3 (20 points) Problem 4 (25 points) TOTAL (100 points) 1

2 Problem 1 Thin-Film Deposition (25 points) (a) Poly-Si is deposited by CVD using SiH4 gas. There is a transition temperature T transition between the mass-transfer limited and surface-reaction limited regimes. (i) (3 points) How will you define the transition temperature using the CVD deposition rate model parameters? Show your reasoning. Grove Model for CVD: Deposition Rate = [1/ (1/ ks +1/ hg )] ( Ng / Nsolid ) with k s (T) = k so exp [ -E A /kt] and hg (T) = D o T 3/2 / P The transition temperature can be defined as the temperature where k s (T) = hg (T) (ii) (4 points) Suppose we maintain all CVD conditions the same except the gas flow velocity is reduced. Sketch a new deposition rate curve versus 1/T in the above figure. [No credit will be given without a brief explanation] EXPLANATION- k s does not change with flow rate and h G decreases with slower flow velocity ( U). (iii) (3 points) Describe the mass depletion problem due to gas inlet in CVD and the approach to minimize this effect. Recation surface close to gas inlet will consume chemical reactants, hence diluting the gas concentration. Reaction surfaces further from the inlet will have a lower deposition rate. One approach to minimize rate nonuniformity is to use a distributed gas inlet system ( e.g. shower heads). (iv) (3 points) Do you think deposition rate of Atomic Layer Deposition (ALD) will depend on the gas flow velocity? Explain why or why not. No. ALD rate is determined by the cycle time for Gas-A absorption/purge/gas-b absorption/purge. Dependence of absorption time on gas flow velocity ( h G ) is minimal. 2

3 (b) Sputtering Deposition Why is sputtering deposition advantageous to prepare compound thin films (e.g. Al-2%Cu)? Compared with Evaporation (3 points) - Compound evaporation needs separate evaporation sources and precise independent control of each evaporation flux. Sputtering deposition only needs a sputtering target of the Al-2% Cu composition. Compared with Chemical Vapor Deposition (3 points) - Difficult to find a Copper CVD precursor. With gas mixtures which have different activation energies for different chemical reactions, precise control of composition is difficult for a specific ratio is difficult since we can use only one deposition temperature. (c) (6 points) Evaporation is used to deposit a thin film on a wafer with the following geometry: By keeping other evaporation parameters the same, indicate in the table below how the thickness uniformity factor will change (= increase, = decrease, 0 = no change) Thickness Uniformity Factor (Thickness at edge of wafer / Thickness at center of wafer) Wafer Diameter D Wafer-Source Distance H Wafer tilt angle (left edge) right edge Evaporation source area A Emission flux angular dependence factor n Evaporation source temperature T 0 3

4 Problem 2 Etching (30 points total) (A) (10 points) The following figure shows the cross-section of a tapered mask opening (45 ) over a film. The mask and the film have equal thickness. Sketch accurately in the same figure the cross sections of mask and film when the bottom of film has just cleared. Also, find numerical values of the angles of the sidewall slopes. Given: Etching Selectivity of Film:Mask = 2:1. Degree of anisotropy for mask etching [A f (Mask) ] =1 Degree of anisotropy for film etching [A f (Film) ] =1 (Mask etching rate) = 1 (Film etching rate) 2 Etching is completely anisotropic for mask and film (i.e., no lateral etching velocity) Angle of sloped mask sidewall= 45 o Angle of sloped film sidewall = tan -1 (2) = 63.4 o. (B) Worst case etching consideration 200nm of poly-si over SiO 2 is to be patterned using reactive ion etching with an etching rate of 100nm/min. The poly thickness has a variation of ±10% and the poly etching rate also has a variation of ±10%. Since the poly is running over steps at some parts of the chip, we'll allow an over-etch time fraction of 10%. (a) (4 POINTS) Use worst-case consideration to find the time difference between maximum time to clear poly-si and minimum time to clear poly-si. Maximum time to clear poly at foot of step = h poly ( 1.1 v poly 0.9 ) 1.1 Minimum time to clear poly on flat regions = h poly v poly ( ) Time difference =t = h poly v poly ( ) = 2 min (0.526) = 1.05 min (b)(4 POINTS) If process requirement allows less than 5 nm of SiO 2 being removed during the poly-si overetching duration, what is the minimum selectivity required for poly-si : SiO 2 ( i.e., vertical poly etching rate / vertical SiO 2 etching rate)? t v < 5 nm implies v < 4.76 nm /min Therefore v poly v > 21 is required for minimum selectivity 4

5 Problem 2 continued (C) (12 points) The following figure illustrates the three different etching mechanisms responsible for plasma etching as functions of ion bombardment energy and gas pressure. (i) Explain why physical sputtering dominates at high ion energy and low pressure. Do you expect this etching to be isotropic or anisotropic? High ion energy gives high sputtering yields. Low pressure implies long mean free path (less ion neutral collisions) and low gas density (less chemical radicals). This regime will be dominated by physical sputtering and little chemical etching. Anisotropic. (ii) Explain why chemical etching dominates at low ion energy and at high pressure. Do you expect this etching to be isotropic or anisotropic? Low ion energy gives low sputtering yields. High pressure implies short mean free path (more ion neutral collision) and high gas density (more chemical radicals). This regime will be dominated by chemical etching. Isotropic. (iii) Based on the three etching mechanisms indicated in the figure, discuss how RIE selectivity will be affected by pressure and ion energy. Selectivity induced by physical bombardment is typically less than that of chemical reactions. The high ion energy/low pressure regime (sputtering dominated) will give lower selectivity The low ion energy/high pressure regime ( chemical etching dominated) will give high selectivity The medium ion energy/pressure regime (ion assisted etching) will give intermediate selectivity. 5

6 Problem 3 Metallization (20 points total) (a) (10 points) Pure aluminum is used as the contact metal to a n+/p junction. A sintering step after metallization shows an electrical short to the substrate which is identified to be the Aluminum spiking problem. In the table below, indicate whether the Al-spikng problem will improve, degrade, or unchange (check the appropriate box) if the following process modifications are made. Provide a brief explanation. t Al x j n+ p-si substrate Process Modification Decrease the junction depth x j Increase the sintering step temperature Increase the metal overlap of contact hole Replace pure Al with Al-1%Si alloy Deposit a TiN layer (diffusion barrier) over the n+ region before Al deposition Improve Degrade Unchange Explanation A larger Al spike is needed to touch p- substrate, creating a Schottky ohmic contact Increase Si solubility in Al and higher Si diffusivity in Al Larger voids (and large spikes) will form because more Si is needed to saturate the Al to solid solubility limit. Less Si from substrate is needed to saturate Al to solid solubility limit TiN acts as a diffusion barrier to block Si diffusion into the Al 6

7 Problem 3 continued (b) (10 points) No suitable reactive ion etching recipe has yet been identified to etch copper interconnect lines. Sketch simple process flows to fabricate copper interconnect lines on substrates using the following alternative techniques. [For simplicity, no diffusion barrier is necessary in these process flows]. (i) Ion beam sputtering mechanism Deposit Cu on. Deposit and pattern a low sputtering yield (S) material and form etching mask with wet or dry etching. The unprotected Cu region is then sputtered away using ion bombardment. Ar + Ion beam Mask with low S Deposited Cu film Mask with low S Cu Cu (ii) Liftoff Process Directional Cu deposition ( e.g. collimated sputtering) Cu Photoresist Surface layer treated by chlorobenzene Form overhang of photoresist ( harden surface with chlorobenzene before resist development). Directional deposition of Cu. Then dissolve photoresist. (iii) Chemical Mechanical Polishing 7

8 Problem 4 Process Integration (25 points total ) The following cross-sections show structure of an advanced CMOS. The materials used are labeled at the right. Poly-Si Silicide Al alloy Oxide (a) (10 points) Design a process flow to fabricate the trench isolation structure. Your process description starts with a p- (epi layer) / p+ Si wafer and ends with both n-well and p-well completed. Use a left column for your process description and sketch the cross-sections in a right column. Key Ideas: RIE trenches in Si and fill with CVD poly. Planarize surface with CMP. Starting Material : p/p+ Trench patterning Mask (M1) Reactive ion etching of trench to p+ substrate Strip mask Thermal Oxidize trench sidewall slightly Refill with thick CVD poly-si. Planarize surface with CMP Selectively etch poly-si till poly slightly below trench surface Reoxidize poly till trench oxide is planar. [If a larger oxide area is needed to butt against the S/D, pattern the oxide area (mask), etch another shallow trench, refill with CVD oxide, planarize with CMP] Pattern n-well area (M2) n-well implant Pattern p-well area (M3) p-well implant Well drive in 8

9 Problem 4 continued (b) (15 points) Design a process flow to fabricate the SALICIDE + LDD MOSFET structure for both NMOS and PMOS. Your process description starts with both p-well and n-well completed and ends with Metal 1 (M1) completed. Use a left column for your process description and sketch the cross-sections in a right column. Key Ideas: 1) Add the LDD implant before oxide spacer step for the generic SALICIDE process. 2) Protect PMOS when doing NMOS source/drain and vice versa. VT threshold Implants (optional) Clean surface oxide formed during drive-in Gate oxide oxidation Poly-gate CVD Poly-gate patterning (mask) NMOS LDD implant (mask, protect PMOS) PMOS LDD implant (mask, protect NMOS) Reoxidize poly gate Blanket CVD oxide Anisotropic RIE to form gate sidewall spacer NMOS S/D and n+ gate implant (mask, protect PMOS) PMOS S/D and p+ gate implant (mask, protect NMOS) Blanket deposition of Ti Annealing to form silicide on S/D and poly gate Selectively remove unreacted Ti CVD oxide Contact via opening (mask) Metal 1 deposition Pattern Metal 1 (mask)..etc 9