Low Dielectric Constant Spin-on-Glass Passivation for High-Speed Complementary Metal-Oxide-Silicon Devices

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1 Journal of the Korean Physical Society, Vol. 43, No. 3, September 2003, pp Low Dielectric Constant Spin-on-Glass Passivation for High-Speed Complementary Metal-Oxide-Silicon Devices Sam-Dong Kim and Hyung-Moo Park Department of electronic engineering, Dongguk University, Seoul Si-Beom Kim System IC Division, Hynix Semiconductor, Ichon (Received 4 March 2003) We examined the effects of the non-etchback passivation process using a low dielectric constant (ɛ r) methylsilsesquioxane spin-on-glass (SOG) on the electrical characteristics of high-speed Si-based memory devices which are very sensitive to the parasitic coupling capacitance among the interconnection metal lines. The pass rate ratio of the fully functional on-wafer chips strongly depends on the dielectric constants, as well as on the local planarization, of SOG materials consisting of passivation structures deposited over the second metal lines. When low ɛ r ( 2.7) methylsilsesquioxane SOG of a 6600 Å as-coated thickness is used for the passivation, a relative pass rate ratio of 92 % is obtained. This pass rate is almost comparable with the device yield of unpassivated chips (effective dielectric constant = 1) and is much higher than that ( 62 %) of chips passivated by using the conventional oxide/silicon-nitride structures. Compared to the conventional passivation structures, no significant shift in threshold voltage is observed in either active or field transistors with low ɛ r SOG-based passivation structures, which suggests no electrical side effect on the metal-oxide-silicon transistors due to the methylsilsesquioxane SOG chemicals. PACS numbers: 73 Keywords: CMOS, SOG, Passivation, Low-k I. INTRODUCTION The dimensions of the ultra-large scaled integrated (ULSI) circuits have been continuously scaled down to the sub-0.2 µm region to increase the density of memory devices. In parallel, the switching speed required for the ULSI circuits has also kept increasing to accommodate the device performance required by the present age. Therefore, modern interconnection processes for high-speed complementary metal-oxide-silicon (CMOS) devices include a variety of issues such as the cross-talk between signal lines [1] and the signal transmission time loss due to RC delay [2,3]. In order to overcome these obstacles, much effort has been made to realize low dielectric constant (ɛ r ) inter-metal dielectric (IMD) thin film processing [4 6] for CMOS devices. For this reason, the role of the final passivation layers needs to be re-examined to reduce the wiring capacitance between the final metal lines and to protect the chips effectively against severe exterior environment. For example, conventional passivation layers, such as the stacked oxides and silicon nitrides deposited using plasma enhanced chemical vapor deposition (PECVD) exhibit relatively high effective ɛ r and poor sidewall step coverage at submicron metal spacings. A variety of materials, such as spin-on-glass (SOG) [7], polymer [8], and porous silica [9] layers, have been examined for future applications in CMOS passivation for minimizing the parasitic capacitance among the metal lines or suppressing the key-hole generation which can be observed in conventional passivation layers with poor step coverage. Even though these new materials can exhibit desirable electrical and physical stability, some arguments still exist about the substantial possibility of applications to real ULSI fabrication and about the CMOS reliability. In this study, low ɛ r ( 2.7) methylsilsesquioxane SOG is adopted for the passivation structure for real device fabrication, and the performance of the passivation is evaluated by investigating the effect on the device yield and on the CMOS characteristics. II. EXPERIMENTAL PROCEDURE samdong@dgu.edu; Tel: ; Fax: Two kinds of SOG chemicals were used for the synchronous static random-access-memory (SSRM) device -386-

2 Low Dielectric Constant Spin-on-Glass Passivation for High-Speed Sam-Dong Kim et al Table 1. Major properties of the methylsiloxane and the methylsilsesquioxane SOGs used in this study. Properties Chemical I [10] Chemical II [10] (Methylsiloxane SOG) (Methylsilsesquioxane SOG) Organic content (%) % Viscosity (cp) Solid content (%) Dielectric constant after baking Gap-filling (µm) passivation processes. As specified in Table 1, the type- II SOG chemical (methylsilsesquioxane) has a higher organic content, solid percentage in solution, and fluid viscosity than type-i (methysiloxane). However, it shows a much lower ɛ r of 2.7 when deposited and stabilized on unpatterned SiO 2 /Si substrates. Moreover, methylsilsesquioxane SOG layers show, in general, a better local planarization than the methysiloxane SOG when both types of SOG layers are spin-coated onto line-and-space metal patterns at the same coating thicknesses on unpatterned samples. To examine the effect of low ɛ r passivation on the device performance, we employed a variety of passivation structures for high-speed SSRAM devices of the 0.5 µm MOS design rule, as summarized in Table 2. For the metal interconnection of the devices, the conventional aluminum-based double-layer metallization (DLM) scheme was used. Especially, for the second metals, 300 Å TiN/ 8000 Å Al/ 700 Å Ti stacked structures were deposited in a DC magnetron sputter system at a total height of 0.9 µm, including the liner and the antireflection coating layers. These metal lines were then patterned at a spacing of 1.0 µm in the areas of highest pattern density. All samples were prepared on 8 inch wafers, and 50 dies of identical positions were sampled out of the on-wafer chips fabricated with each passivation condition. These test dies were characterized using an on-wafer probe machine to examine the CMOS characteristics and the chip total functionality. and F). When SOG local planarization among the metal lines is not perfectly achieved, as shown in the cases C and E, the final silicon nitride (ɛ r = 6 7) passivation layers will play a significant role in increasing the inter-metal capacitance. Therefore, the effective wiring capacitance (EWC) between the second metal lines will be affected not only by the SOG chemical type but also by the degree of local planarization (DOLP). The EWC for each passivation structure can be calculated using a 2-D model with DOLPs and dielectric Fig. 1. Schematics of the cross-sectional passivation structures of (a) case A, (b) case B, (c) cases C and E, and (d) cases D and F. Each passivation structure is defined in Table 2. III. RESULTS AND DISCUSSION Inter-metal gap-filling capability of the SOG layers is well known to depends on various parameters, such as the spin process condition, the pattern density of the metal interconnection lines, and the viscous fluidity of the SOG chemical [11]. In general, SOG planarization exhibits excellent gap-filling and global planarization among fine metal lines and under severe underlayer topography. As Fig. 1 illustrates, the degree of local passivation planarization among the metal patterns can strongly depend on the coating thickness and on the chemical type of the SOG in each passivation structure (cases C, D, E Fig. 2. Normalized effective wiring capacitance calculated for each passivation structure used in this study.

3 -388- Journal of the Korean Physical Society, Vol. 43, No. 3, September 2003 Table 2. Experimental conditions of the various passivation structures used in this study. The thicknesses of the SOG layers shown in this table were measured after spin-coating before the baking process. A B GROUP No passivation Oxide/Nitride Passivation C SOG-I Passivation D SOG-I Passivation E SOG-II Passivation F SOG-II Passivation SOG CHEMICLAS None None Chemical I Chemical II constants measured for each SOG chemical type and thickness, and the calculated results for each passivation structure are shown in Fig. 2. As we discussed earlier, the calculated effective capacitance results also show a strong dependence of the EWC on both the local planarization of the SOG layers and the passivation materials. Because the passivation structure with a thinner SOG layer has a more concave shape at the metal spacings, as shown in Fig. 3, higher EWCs are obtained due to the presence of high- r silicon nitride layers between the metals. Figure 4 shows the relative pass rates in percent (the pass rate of the case A is defined to be equal to 100 %) of the fully functional SSRAM on-wafer chips out of the total measured dies when six different passivation structures were used for real device fabrication. When a high r PECVD oxide/nitride structure were used for the passivation, a very low pass rate ratio of 62 % was measured, as shown in the case of B. With full planarization SOG passivations (cases D and F), we obtained much Fig. 3. Cross-sectional SEM views of the cross-sectional passivation structures of (a) case A, (b) case B, (c) cases C and E, and (d) cases D and F. Each passivation structure is defined in Table 2. PASSIVATION STRUCTURES Air passivation PECVD-Ox. 3000/ PECVD-Ox. 1500/SOG 4400/ PECVD-Ox. 1500/SOG 6600/ PECVD-Ox. 1500/SOG 4000/ PECVD-Ox. 1500/SOG 6000/ improved pass rate ratios greater than 80 % than we did with partial SOG planarization (cases C and E). Moreover, a more enhanced pass rate of 92 % is observed even at the same SOG thickness of 6600 A if a lower r SOG type (methylsilsesquioxane) material is used. The dependence of the device pass rate on the passivation structure shown in Fig. 4 can be replotted to illustrate the dependence on the EWC of the passivation as shown in Fig. 5. Figure 5 clearly shows the effects of the EWC on the pass rate of fully functional SSRAM device. As many earlier studies on the RC delay effect due to the inter-metal-dielectrics (IMDs) explained [2,3], the EWC of the passivation, which depends on both the SOG planarity and the effective dielectric constant, will affect the device cycle time, which is the response to the charging and discharging events in the passivation dielectric. Figure 6 shows a plot of the cycle times calculated at various equivalent values of r for the passivations, which were obtained by using a full-layout simulation of the Fig. 4. Relative pass rate of SSRAM devices measured for each passivation structure used in this study.

4 Low Dielectric Constant Spin-on-Glass Passivation for High-Speed Sam-Dong Kim et al Fig. 5. Relative pass rate of the SSRAM devices versus the normalized effective wiring capacitance for each SSRAM devices. Fig. 7. Threshold voltages (V T H) for the n/p active and field MOS transistors fabricated using the various passivation structures used in this study. voltage shifts [14 16], possibly due to H 2 O permeation into the field or gate oxides have been reported. Shown in Fig. 7 are comparative measurements of threshold voltages (V T H ) for n/p active and field MOS transistors fabricated using the various passivation structures. Compared to the conventional oxide/nitride passivation structure, no significant shift in V T H was seen in either the active or the field transistor with each SOG-based passivation structure. IV. CONCLUSIONS Fig. 6. Calculated cycle time of the SSRAM devices for various equivalent dielectric constants of the passivation structures. SSRAM cell used in this study. This result shows, as expected, that the EWC of the passivation structure is one of the key factors influencing the pass rates of highspeed devices. Moreover, the lower EWC of the passivation structure can produce much less cross-talk noise [1,12,13] among the metal lines. Therefore, this will enhance the pass rate due to other corresponding device performances. We also examined the electrical characteristics of MOS field effect transistors (MOSFETs) in the active and the isolation areas to observe any possible side effects due to silanol groups ( (Si-OH) n ) included in the SOG chemicals on the electrical behaviors of the active transistors and on the isolation properties. In some cases of organic SOG IMD applications, degradations of MOS transistors, such as n-channel field inversions and threshold In this article, the effects of a non-etchback low ɛ r SOG passivation process on the electrical characteristics of high speed SSRAM devices were examined. The parasitic wiring capacitance among the final metal interconnect lines, which depends of both ɛ r and the local planarity of the SOG layers, strongly affected the onwafer device yield. A passivation structure using low ɛ r methylsilsesquioxane SOG with an as-coated thickness of 6600 Å showed an approximately 50 % higher device pass rate than the passivation structure using conventional oxide/silicon nitride. No significant electrical degradations of the MOS transistors or the field isolations were observed when the low-ɛ r SOG was used for passivation. ACKNOWLEDGMENTS This research is supported by Korea Science and Engineering Foundation (KOSEF) under the Engineering Research Center (ERC) program through the Millimeterwave Innovation Technology Research Center at Dongguk University. One of authors, S. D. Kim, would like to

5 -390- Journal of the Korean Physical Society, Vol. 43, No. 3, September 2003 thank all of his former research colleagues at the Memory R&D division of Hynix semiconductor Inc., whose efforts and discussions were valuable to this work. The authors also would like to thank D. K. Choi in Allied Signal Korea for his providing the SOG chemicals. REFERENCES [1] D. H. Cho, Y. S. Eo, H. M. Seung, N. H. Kim, J. K. Wee, O. K. Kwon and H. S. Park, Proceedings of International Electron Devices Meeting (San Francisco, Dec., 1996), p [2] R. C. Liu, C. S. Pai and E. Martinez, Solid State Electr. 43, 1003 (1999). [3] K. Imai, K. Yamaguchi, T. Kudo, N. Kimizuka, H. Onishi, A. Ono, Y. Nakabara, Y Goto, K. Noda, S. Masuoka, S. Ito, K. Matsui, K. Ando, E. Hasegawa, T. Ohashi, N. Oda, K. Yokoyama, T. Takewaki, S. Sone and T. Horiuchi, Proceedings of International Electron Devices Meeting (San Francisco, Dec., 2000), p [4] K. W. Kim, K. S. Cho, J. I. Ryu, K. H. Yoo and J. Jang, IEEE Electr. Dev. Lett. 21, 301 (2000). [5] Y. Matsubara, K. Kishimoto, K. Endo, M. Iguchi, T. Tatsumi, H. Gomi, T. Horiuchi, E. Tzou, M. Xi, L. Y. Cheng, D. Tribula and F. Moghadam, Proceedings of International Electron Devices Meeting (San Francisco, Dec., 1998), p [6] K. M. Chang, M. H. Tseng, I. C. Deng, Y. P. Tsai and S. J. Yeh, Jpn. J. Appl. Phys. 40, 6663 (2001). [7] C. C. Tsan Y. L. Wang, C. Y. Fu, S. M. Jang, C. F. Lin, Sunway Chen, T. A. Yeh and Adam Chen, Proceedings of Fifth International Dielectrics for ULSI Multilevel Interconnection Conference (Santa Clara, Feb., 1999), p [8] P. T. Liu, T. C. Chang, H. Su, Y. S. Mor, Y. L. Yang, H. Chung, J. Hou and S. M. Sze, J. Electrochem. Soc. 148, F30 (2001). [9] A. Jain, S. Rogojevic, S. Ponoth, N. Agarwal, I. Matthew, W. N. Gill, P. Persans, M. Tomozawa, J. Plawsky and E. Simonyi, Thin Solid Films 398, 513 (2001). [10] J. Waterloos, H. Meynen, B. Coenegrachts, T. Gao, J. Grillaert and L. van den Hove, Proceedings of the Third International Dielectrics for ULSI Multilevel Interconnection Conference (Santa Clara, Sept., 1997), p [11] L. J. Chen, Proceedings of Twelfth International VLSI Multilevel Interconnection Conference (Santa Clara, Sept., 1995), p [12] M. M. Farahani and J. F. Buller, Proceedings of the Dielectric Material Integration for Microelectronics (San Diego, Spring, 1998), p. 67. [13] A. Vittal and M. Mareksadowska, IEEE Trans. Comp. Des. Int. Circ. & Sys. 16, 290 (1997). [14] T. Yamaha, Y. Inoue, O. Hanagasaki and T. Hotta, J. Electrochem. Soc. 142, 3132 (1995). [15] C. F. Lin, I. C. Tung and M. S. Feng, Jpn. J. Appl. Phys. 38, 6253 (1991). [16] J. H. Kim, Y. M. Moon, J. B. Choi, B. J. Shin, Ikgueon Choi, K. H. Park and S. I. Yang, J. Korean Phys. Soc. 39, 1103 (2001).