Investigation of Non Volatile AlGaN/GaN Flash Memory for High Temperature Operation

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1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.1, FEBRUARY, 2018 ISSN(Print) ISSN(Online) Investigation of Non Volatile AlGaN/GaN Flash Memory for High Temperature Operation Ikhyeon Kwon 1, M. Saif Islam 2, and Il Hwan Cho 1* Abstract A charge trap flash (CTF) memory based on AlGaN / GaN transistors has been proposed for memory development in high temperature environment. The proposed device is designed to have a positive threshold voltage for applying NAND or NOR arrays. In order to improve the electron storage ability at high temperature, various dielectrics have been applied. The height of the electron barrier inside the charge trap layer is the most important parameter in the high temperature memory operation and the dielectrics such as Ta 2 O 5 or SrTiO 3 shows excellent reliability at 500K. As the temperature increases, a change in threshold voltage occurs, and additional circuitry is needed to compensate for this. Through this paper, design guideline of memory operating in extreme high temperature environment is investigated. Index Terms High temperature operation, wide band gap semiconductor, charge trap flash, reliability, memory Manuscript received Jun. 29, 2017; accepted Jul. 19, Department of Electronic Engineering, Myongji University, Yongin, Gyeonggi 17058, Republic of Korea 2 Department of Electrical and Computer Engineering, University of California Davis, CA 95616, USA ihcho77@mju.ac.kr I. INTRODUCTION Since power plants and motor vehicles operate at high temperatures, semiconductor devices contained therein require high reliability at high temperatures. In a high temperature environment, semiconductor devices suffer from problems such as leakage current and current reduction [1]. However, the transistor was able to improve operating characteristics at high temperatures through wide bandgap materials such as GaN [2, 3]. However, in the case of nonvolatile memory devices, loss data problem occurs instead of leakage current problem. This phenomenon occurs because the stored electrons can escape beyond the surrounding energy barrier. These characteristics are the same in flash memories using floating gates and charge trap layers. Various techniques have been developed to improve memory operation at high temperatures, such as memory based on carbon nanotube (CNT). Although CNT based memory had shown better retention characteristics at high temperatures, its compatibility with conventional semiconductor fabrication process has not been reported yet [4]. LiNbO 3 /AlGaN/GaN based metal insulator semiconductor (MIS) structure memory had shown good retention characteristics at high temperatures but the memory operation characteristics with select transistor have not been introduced [5]. Nanowire memory based on GaN transistor also aimed a high temperature memory operation, charge storage layer had not been optimized in previous work [6]. As noted above, various types of memories have been developed for high-temperature operation, but no producible memories that have been stable to operate above 200 degrees have been proposed. Up to now, the memory operating at the highest temperature among the commercially available memories has been developed by TEXAS Instrument and can operate up to 125 degrees. When a memory capable of operating at a high temperature of 200 C or higher is developed, it can be used in various devices or systems operating under harsh environment.

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.1, FEBRUARY, Two techniques must be developed to ensure hightemperature operation of the memory. One of them is a technique for stably storing electrons at a high temperature, and the other is a technology for allowing a select transistor of a memory to operate stably at a high temperature. In this study, we propose a method to improve the high temperature operation characteristics of charge trap flash (CTF) memory. The proposed technology will be verified through device simulation and various optimization will provide guidelines for high temperature operation memory design. Table 1. Band gap, electron affinity, dielectric constant for the various insulators [19-25] Band gap (ev) Electron affinity (ev) Dielectric constant SiO AlN Si 3N HfO ZrO Ta 2O SrTiO II. DEVICE STRUCTURE Silicon has a bandgap of 1.1 ev and is hard to avoid a large leakage current at high temperature operation [7]. For this reason, the high temperature operation memory proposed in this study is based on a wide bandgap material. High electron mobility transistor (HEMT) using AlGaN and GaN has attracted much attention within various transistors using wide bandgap materials because of high electron saturation velocity and high 2 dimensional electron gas (2DEG) density [8-10]. In the case of transistors using AlGaN, process technologies have been introduced in many previous studies [11, 12]. In order to design a high-temperature operation memory using AlGaN/GaN HEMT, threshold voltage (V t ) and charge storage layer must be carefully considered. Conventional AlGaN/GaN HEMTs generally operate in the depletion mode because 2DEG is present in the AlGaN/GaN heterojunction [13]. However, a memory device must have a positive V t to be applied to a NOR or NAND array [14]. In order to obtain a positive V t, the memory device proposed in this study uses a high concentration p-type doped AlGaN layer and an n-type doping region formed in the source/drain region [15, 16]. In the previous work with AlGaN/GaN structure memory, electrons were stored in GaN layer between AlGaN and silicon dioxide layer [17]. In that structure, the program operation consists of tunneling electrons of the 2DEG formed in the AlGaN layer to an energy well formed in the GaN layer by the gate electric field. However, the lower barrier of electrons in previous structures has a negative effect on the reliability of memory, which is especially worse in high temperature operation. The results of previous study show that the Fig. 1. Schematic diagram of the suggested device with oxide/nitride/oxide storage layer. reliability of memory is affected by the energy band configuration of the charge storage layer [18]. In order to overcome the disadvantages of previous studies, we designed an electron storage layer using a material with a large energy bandgap. Table 1 shows the electrical properties of the dielectric layers used in this study, and each parameter has been introduced in previous studies. Fig. 1 shows the structure of the proposed memory. It is based on AlGaN/GaN HEMT for high temperature operation and has the same operating principle as charge trap flash memory. The device consists of GaN buffer layer, SiN passivation layer, 21 nm thick AlGaN barrier layer, 5 nm thick GaN cap layer, 130 nm gate length, and 3/3/4 nm thick oxide/nitride/oxide(ono) layers for storing charges. The doping concentration of GaN channel and AlGaN layer is 1ⅹ10 18 cm -3 and 1ⅹ10 18 cm -3, respectively. The device operation simulations are carried out in Synopsys Sentaurus TCAD using a thermode. Thermode can change the temperature of the device, so it can check the operating characteristics of the device with temperature. In addition the thermodynamic model extends the drift diffusion approach to account for electro thermal effects.

3 102 IKHYEON KWON et al : INVESTIGATION OF NON VOLATILE AlGaN/GaN FLASH MEMORY FOR HIGH TEMPERATURE Drain current (A/mm) Nomally on HEMT Nomally off HEMT Gate voltage (V) Fig. 2. I-V curve of the conventional AlGaN / GaN HEMT memory device and proposed memory device structures. (a) III. RESULTS AND DISCUSSION Fig. 2 compares the transfer curves of conventional AlGaN/GaN HEMT memories with the memory proposed in this study. As suggested in previous studies, a positive V t can be obtained in a HEMT device when a high-concentration p-type AlGaN layer and an n-type source/drain are used. The doping concentration of AlGaN layer and source/drain are 1ⅹ10 18 cm -3 and 5ⅹ10 20 cm -3, respectively. The fermi level of the p-type doped AlGaN layer is lowered toward the valence band, so that the fermi level between AlGaN and GaN is also directed toward the valence band, thereby preventing the formation of 2 DEG and enabling the normally off operation of the device. Fig. 3(a) shows the energy band at the A-A' cross section when the program operation is performed. As can be seen in Fig. 3(b), the inversion charge is formed on the AlGaN surface by the program voltage, and the inversion charges for tunneling to the nitride layer are gathered by the high electric field. Fig. 3(c) shows the trap charge density of the nitride layer. This result shows that enough electrons are trapped to obtain the V t shift. From the above results, we can notice that the program of the proposed memory occurs independently of the 2DEG formed between AlGaN and GaN. To study the reliability characteristics of memory, it is important to understand the four mechanisms of losing stored electrons. The four mechanisms are trap to band tunneling, trap to trap tunneling, thermal excitation, and band to trap tunneling [26]. In general, the retention (b) (c) Fig. 3. (a) Band diagram of proposed AlGaN / GaN HEMT memory from gate to GaN layer during program operation, (b) Electron density distribution and electric field profile from top oxide to GaN layer during program operation, (c) Trap charge density from top oxide to bottom oxide layer after program operation.

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.1, FEBRUARY, (a) (a) (b) Fig. 4. (a) Energy band diagram along the charge trap layers, (b) Retention characteristics of various charge trap layers at high temperatures. The inset is the electron barrier of the electron trapped in the trap layer. characteristics of memory devices operating in a room temperature environment are determined by the tunneling mechanism. However, if the operating environment of the memory device has a temperature of 450K or higher, the tunneling mechanism is small enough to be neglected, and the thermal excitation mechanism become dominant. [26, 27]. Therefore, the proposed device with 573K harsh environment is focused on the thermal emission mechanism when the retention characteristics are analyzed. Fig. 4(a) shows the energy band diagram of the charge trap layer formed by dielectrics with Table 1. It can be seen that the electron barrier is changed by electron affinity and bandgap, and as a result, the retention characteristic can be expected to change. To investigate the electrical characteristics of the (b) Fig. 5. (a) Energy band diagram along the charge trap layers, (b) Retention characteristics of AlN / Si 3 N 4 /AlN and SiO 2 / Si 3 N 4 / SiO 2 structures at various high temperatures. dielectric layer, we program the electrons with Fowler Nordheim (FN) program (Vg = 18 V, 2 ms) and then extract the charge loss ratio after 5000 s have passed. As can be seen in Fig. 4(b), the nitride used in the CTF memory generally reduces its ability to store charge over 400K. Storing charge at a temperature higher than 500K, the electron barrier of the electron trapped in the trap layer should be 2.0 ev or more as shown in inset of Fig. 4(b). This can be obtained by changing the electrical properties of the tunneling layer and the blocking layer in addition to the change of the trap layer. Fig. 5(a) shows the energy band diagrams of SiO 2 used as the tunneling layer and blocking layer of the CTF memory and of the AlN replaced material. As the electron barrier increases, the retention characteristics are improved as shown in

5 104 IKHYEON KWON et al : INVESTIGATION OF NON VOLATILE AlGaN/GaN FLASH MEMORY FOR HIGH TEMPERATURE operation temperature changes to a large range, a circuit for correcting the V t according to the operation temperature may be separately needed. This problem can be solved by designing a gate driver circuit that includes a charge pump, a gate current monitoring circuit, a desaturation detection circuit, and an enhanced voltage regulator, which are currently used in semiconductor devices with high temperature operating ranges [30-32]. IV. CONCLUSIONS Fig. 6. I-V characteristic curve for various temperature of memory with ONO storage layer. The inset shows the initial V t shift with temperature variation. Fig. 5(b). This means that it is possible to combine various charge trap layers when they are guaranteed to be applicable to a Semiconductor fabrication process. In addition to the concentration of electrons stored in the charge trap layer discussed above, changes in the V t due to temperature must be taken into account in high temperature memory operation. Fig. 6 shows the I-V curve and V t of the device proposed in this work. V t is shifted to negative region at high temperature since the 2DEG density is higher and the Schottky barrier height is decreasing with higher temperature [28]. The relationship between the Schottky barrier height and V t can be explained by V t equation in AlGaN/GaN HEMT [29]. where Φ B is the Schottky barrier height, ΔE C the conduction band offset between the gate oxide and the GaN buffer, Δ is the depth of the well in the conduction band below the Fermi level, σ pol,ox the polarization difference between the oxide and AlGaN barrier layers, C ox the oxide capacitance, σ pol,barrier the polarization difference between the barrier and buffer layers, and C B the barrier capacitance. Since the flash memory stores and reads data at the magnitude of the current according to the V t, a change in the V t may cause data distortion. However, if the (1) We proposed CTF memory technology with AlGaN / GaN transistor for high temperature operation. In order to apply the AlGaN / GaN transistor to the memory, the technique of increasing V t was applied. The charge storage layer of the charge trap layer was improved by applying dielectrics which make high electron energy barrier. Through the combination of these techniques, the possibility of a memory capable of operating at a high temperature of 500K or more is confirmed through simulation. Through the combination of these techniques, the possibility of a memory capable of operating at a high temperature of 500K or more is confirmed through simulation. In the case of CTF memories storing electrons, the electron energy barrier must be 2.0 ev or more to have a reliable electron storage capability at a high temperature of 500K or more. It is expected that the high temperature operation characteristics can be further improved through various materials. However, in order to solve the problem caused by the change of the V t according to the temperature, there is a circuit design technique, which can correct the V t change according to the temperature. Through this study, a design guide for developing high temperature operation memory was provided. V. ACKNOWLEDGEMENTS The research was supported by the ICT program of MSIP/IITP, Republic of Korea (#B ) and was also supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (No. 2016R1D1A1B ). This work was also supported by 2017 Research Fund of Myongji University.

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.1, FEBRUARY, REFERENCES [1] Yasuhisa Omura., Proposal of High-Temperature- Operation Tolerant SOI MOSFET and Preliminary Study on Device Performance Evaluation, Hindawi Publishing Corporation Active and Passive Electronic Components, vol. 2011, p.8, July., [2] B. N. Shashikala1 et al., High temperature performance of Wide Bandgap Semiconductors Devices for High Power Applications, International Journal of Engineering Science and Technology, Vol. 2, no. 12, pp , Dec., [3] Jinwook Burm et al., Wide Band-gap FETs for High Power Amplifiers, Journal of Semiconductor Technology And Science, vol. 6, no. 3, pp , Sept., [4] Dawid Janas et al., Carbon nanotube wires for high-temperature Performance, CARBON 64, pp , July., [5] L. Z. Hao, J. Zhu et al., Electron trap memory characteristics of LiNbO 3 film/algan/gan heterostructure Applied Physics Letters, vol. 96, Jan., [6] Ho-Young Cha et al., Gallium nitride nanowire nonvolatile memory device, J. Appl. Phys., vol. 100, July [7] P. L. Dreike et al., An Overview of High- Temperature Electronic Device Technologies and Potential Applications, IEEE Transactions On Components. Packaging, And Manufacturing Technology, vol. 17, no. 4, pp , Dec., [8] Do-Kywn Kim et al., Device Performances Related to Gate Leakage Current in Al 2 O 3 /AlGaN/ GaN MISHFETs, Journal of Semiconductor Technology And Science, vol. 14, no. 5, pp , Oct., [9] Han-Yin Liu et al., Investigation of Temperature- Dependent Characteristics of AlGaN/GaN MOS- HEMT by Using Hydrogen Peroxide Oxidation Technique, IEEE Transactions On Electron Devices, vol. 61, no. 8, pp , Aug., [10] Wataru Saito et al., High Breakdown Voltage AlGaN GaN Power-HEMT Design and High Current Density Switching Behavior, IEEE Transactions On Electron Devices, vol. 50, no. 12, pp , Dec., [11] Young-Woo Jo et al., AlGaN/GaN FinFET With Extremely Broad Transconductance by Side-Wall Wet Etch, IEEE Electron Device Letters, vol. 36, no. 10, pp , Oct., [12] Ki-Sik Im et al., Temperature-dependent characteristics of AlGaN/GaN FinFETs with sidewall MOS channel, Solid-State Electronics, vol. 120, pp , June., [13] Maojun Wang et al., 900 V/1.6 mω cm 2 Normally Off Al 2 O 3 /GaN MOSFET on Silicon Substrate, IEEE Transactions On Electron Devices, vol. 61, no. 6, pp , June., [14] Yihua Yan et al., Analysis of the TID Induced Failure Modes in NOR and NAND Flash Memories, IEEE Transactions On Nuclear Science, vol. 60, no. 1, pp , Feb., [15] Saleem Hamady et al., P-Doped Region below the AlGaN/GaN Interface for Normally-Off HEMT, Power Electronics and Applications (EPE'14- ECCE Europe), th European Conference on 2014, pp. 1-8, Aug., [16] S. Sugiura et al., Normally-off AlGaN/GaN MOSHFETs with HfO 2 gate oxide. Phys. Stat. Sol., vol. 5, no. 6, pp , Dec., [17] J.-G. Lee et al., Nonvolatile memory device based on SiO 2 /GaN/AlGaN/GaN heterostructure, ELECTRONICS LETTERS, vol. 49, no. 8, pp , June., [18] X. D. Huang et al., Fluorinated SrTiO 3 as Charge- Trapping Layer for Nonvolatile Memory Applications, IEEE Transactions On Electron Devices, vol. 58, no. 12, pp , Dec., [19] J. Robertson et al., Band offsets of high K gate oxides on III-V semiconductors, Journal of Applied Physics, vol. 100, pp , July., [20] S L Tripathi et al., Multi-gate MOSFET structures with high-k dielectric materials, Journal of Electron Devices, vol. 16, pp , Dec., [21] TV Rajesh, M Kumar et al., Zirconium Oxide Mixed Tantalum Oxide High-K Gate Dielectric Films for Metal-Oxide-Semiconductor (MOS) Devices, European Journal of Advances in

7 106 IKHYEON KWON et al : INVESTIGATION OF NON VOLATILE AlGaN/GaN FLASH MEMORY FOR HIGH TEMPERATURE Engineering and Technology, vol. 2, no.8, pp. 9-15, [22] J. Robertson, High dielectric constant oxides, Eur. Phys. J. Appl. Phys., vol. 28, pp , Dec., 2004 [23] Osman Pakma, Current Mechanism in HfO2- Gated Metal-Oxide-Semiconductor Devices, Hindawi Publishing Corporation International Journal of Photoenergy, vol. 2012, Apr., [24] Chun Zhao et al., Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm, Materials, vol. 7, no. 7, pp , July., [25] W. Miao et al., Optical and Electric Properties of Aligned-Growing Ta 2 O 5 Nanorods, Materials Transactions, vol. 49, no. 10, pp to 2291, Sept., [26] A. Arreghini et al., Long term charge retention dynamics of SONOS cells, Solid-State Electronics, vol. 52, pp , Sept., [27] Yang (Larr) Yang et al., Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures, Solid-State Electronics, vol. 44, pp , Jan [28] Yun-Hsiang Wang et al., Analytical Modelling of High Temperature Characteristics on the DC Responses for Schottky-Gate AIGaN/GaN HEMT Devices, ECCE Asia Downunder (ECCE Asia), pp , Aug [29] Po-Chun Yeh et al., Threshold voltage controlled by gate area and gate recess in inverted trapezoidal trigate AlGaN/GaN MOS high-electron-mobility transistors with photoenhanced chemical and plasma-enhanced atomic layer deposition oxides, Applied Physics Express, vol. 8, no. 8, pp , July [30] R.L. Greenwell et al., SOI-Based Integrated Circuits for High-Temperature Power Electronics Applications, 2011 Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp , April., [31] Mohammad A. Huque et al., A 200 C Universal Gate Driver Integrated Circuit for Extreme Environment Applications, IEEE Transactions On Electron Devices, vol. 27, no. 9, pp , Sept., [32] Feng Qi et al., Development of a High- Temperature Gate Drive and Protection Circuit Using Discrete Components, IEEE Transactions On Power Electronics, vol 32, no. 4, pp , Apr., Ikhyeon Kwon was born in Seoul, Korea, in He received the B.S. degree in Electronic Engineering from Myongji University, Yongin, Korea, in He is currently working towards a M.S. degree at the same university. His research interests include the MOSFETs for harsh environment application, and Flash memory device. M. Saif Islam received his B.Sc. Degree in Physics from Middle East Technical University (1994, Turkey), M.S. degree in Physics from Bilkent University (1996, Turkey) and Ph.D. degree in Electrical Engineering from UCLA in He worked for SDL Inc./JDS Uniphase Corporation, Gazillion Bits, Inc. and Hewlett-Packard Laboratories as a Staff Scientist, a Senior Scientist and a Postdoctoral Research Fellow. He joined University of California - Davis in 2004, where he is a Professor and the chair of the Electrical and Computer Engineering Department now. Prof. Islam s current research objectives include the development of massively parallel and mass-manufacturable synthesis and integration processes for zero-, one- and twodimensional nanostructures for potential applications in electronics, photonics, energy conversion and sensing. He has authored/co-authored more than 250 scientific papers, organized 25 conferences/ symposiums as a chair/co-chair; and holds 40 patents as an inventor/coinventor. He received NSF Faculty Early Career Award (2006), Outstanding Junior Faculty Award (2006) and Mid-Career Research Faculty Award (2012), IEEE Professor of the Year (2005 and 2009) and University of California - Davis Academic Senate Distinguished Teaching Award in He is an elected fellow of the National Academy of Inventors. Photo and biography will be added.

8 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.1, FEBRUARY, 2018 Il Hwan Cho received the B.S. in Electrical Engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejon, Korea, in 2000 and M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 2002, 2007, respectively. From March 2007 to February 2008, he was a Postdoctoral Fellow at Seoul National University, Seoul, Korea. In 2008, he joined the Department of Electronic Engineering at Myongji University, Yongin, where he is currently a Professor. His current research interests include improvement, characterization and measurement of non-volatile memory devices and nano scale transistors including tunneling field effect transistor. 107