Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

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1 ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu Webpage: 82 Lomb Memorial Drive Rochester, NY Department webpage: BulkMEMsFabricationDetails2017.ppt Page 1

2 OUTLINE Introduction Device Cross Section Maskmaking Stepper Jobs Fabrication Details Signal Processing Packaging Testing Summary References Homework Page 2

3 INTRODUCTION This document provides detailed information on RIT s Bulk micromachine process. This process is capable of making many different types of MEMS devices. This version is a simplified 4 or 5 photo level process to take advantage of 4 levels per plate maskmaking and to minimize the time to fabricate the devices. Page 3

4 GENERIC DEVICE CROSS SECTION n - type p - type 1 um BOX 10um 500um Diffusion (Green) Layer 1 Backside Hole (Purple Outline) Layer 4 Contact Cut (White) Layer 6 Metal (Blue) Layer 7 Outline (Yellow Outline) Layer 9 Outline is only for layout, drawing a 4.5mm by 4.5mm outline, the maximum area for individual device designs. Page 4

5 10 mm MEMS MULTICHIP PROJECT TEMPLATE Total 10 mm by 10 mm including 1 mm for sawing into 4 chips. Wafer sawing is easier if all chips are the same size R1 R3 R2 R4 Your Design 4.5mm by 4.5mm design space for each project 4 different projects 5 mm Page 5

6 10 mm 2017 BULK MEMS CHIP FINAL LAYOUT Total 10 mm by 10 mm including 1 mm for sawing into 4 4.5mm by 4.5 mm chips. Page 6

7 MASK ORDER FORM Dr Fuller RIT BULK-MEMS-2017-Final.gds 4 10mm x 10mm x X yes, 4 levels per plate Page 7

8 MASK ORDER FORM DETAILS Layer Reticle Name Design.gds Layer # s Boolean Function Dark/ Clear Comment 1 st Diffusion 1 1 Inverted Dark Mirror 2 nd Cut 6 6 Inverted Dark Mirror 3 rd Metal 7 None Clear Mirror 4 th Hole 4 4 Inverted Dark No mirror Hole pattern is put on the back side of the wafer so it does not get mirrored. All the other layers are mirrored. Design Layer 9 Out (outline) is not used. It is only for placement of projects on the multi-project reticle template. Page 8

9 LAYER 1 DIFFUSION AND LAYER 2 CUT DIFFUSION.gds #1 CUT.gds #6 Page 9

10 LAYER 3 METAL AND LAYER 4 BACKSIDE HOLE METAL.gds #7 BACKSIDE HOLE.gds #4 Page 10

11 BULK MEMS PROCESS FLOW 1. Starting wafer, 10um SOI 2. Grow 5000Å oxide, Recipe PH03 level 0, Marks 4. ET06 Wet Etch Alignment Marks 5. Strip resist and clean 6. Grow another 5000Å oxide, Recipe PH03 level 1 Diffusion + Hand Coat back of wafer with PR + oven bake 8. ET06 Wet Etch Oxide 9. ET07 Resist Strip, Solvent Strip 10. CL01- RCA Clean 11. IM01 - Implant 1E15, B11, Energy 80Kev 12. OX Å Dry Oxide, Anneal 13. PH03 level 2 Contact Cut + Hand coat back of wafer with PR + oven bake 14. ET29 Etch CC Oxide 15. ET07 - Resist Strip, Solvent Strip 16. CL01 RCA Clean two HF dips 17. Sputter metal 1um, 30min 18. PH03 level 3 Metal 19. ET55 Metal Etch wet 20. Strip Resist Solvent Strip 21. Sinter wafers 22. PH03 level 4 Back Hole +Hand Coat Front with PR +oven bake 23. Etch Oxide in Holes on Back Wet 24. STS Etch Silicon from Back 25. TE01 wafer level testing 26. SAW1 Saw wafers 27. Packaging and Testing 28. Documentation Page 11

12 GENERIC DEVICE CROSS SECTION n - type p - type 1 um BOX 10um 500um Diffusion (Green) Layer 1 Backside Hole (Purple Outline) Layer 4 Contact Cut (White) Layer 6 Metal (Blue) Layer 7 Outline (Yellow Outline) Layer 9 Outline is only for layout, drawing a 4.5mm by 4.5mm outline, the maximum area for individual device designs. Page 12

13 STARTING WAFER N-type, Phosphorous, (100), 10um+/-1um, 1-10 ohm-cm BOX Oxide 1um +/-5% Handle Wafer Thickness 500um +/- 10um 1-10 ohm-cm 150mm diameter SOI wafers, Polished both top and bottom Page 13

14 SSI COAT AND DEVELOP TRACK FOR 6 WAFERS Use Recipe: COAT.rcp and DEVELOP.rcp Page 14

15 RECIPES FOR RESIST COAT AND DEVELOP Level Level Name Resist Coat Recipe Develop Recipe Resist Thickness 0 Zero OIR-620 Coat Develop 1.0um 1 Diffusion OIR-620 Coat Develop 1.0um 2 CC OIR-620 Coat Develop 1.0um 3 Metal OIR-620 Coat Develop 1.0um 4 Hole OIR-620 Coat Develop 1.0um Hole will be placed on the back of the wafer. Alignment will be only from the flat finder on the ASML stepper. Level zero uses the ASML Combi Reticle. Page 15

16 PHOTORESIST PROCESSING DEHYDRATE BAKE/ HMDS PRIMING COAT.RCP SPIN COAT SOFT BAKE HMDS Vapor Prime 140 C, 60 sec. OIR Resist 3250rpm, 30 sec. 90 C 60 sec. POST EXPOSURE BAKE 110 C, 60 sec. DEVELOP.RCP DEVELOP DI Wet CD-26 Developer 48sec. Puddle, 30sec. Rinse, 30sec., 3750rpm Spin Dry HARD BAKE 120 C, 60 sec. Page 16

17 ASML 5500/200 NA = 0.48 to 0.60 variable = 0.35 to 0.85 variable With Variable Kohler, or Variable Annular illumination Resolution = K1 l/na = ~ 0.35µm for NA=0.6, =0.85 Depth of Focus = k 2 l/(na) 2 = 1.0 µm for NA = 0.6 i-line Stepper l = 365 nm 22 x 27 mm Field Size Page 17

18 STEPPER JOB Mask Barcode: Stepper Jobname: MCEE770-MEMS4X Level 0 (combi reticle) Level Clearout (combi reticle) Level 1 Diffusion Level 2 Cut Level 3 Metal Level 4 Hole Level MEMS-Test (no alignment) After photo prior to etch inspect the alignment marks. They have to be perfect. If not rework the photo step. Page 18

19 DRYTEK QUAD RIE TOOL Page 19

20 ZERO ETCH FOR ASML ALIGNMENT MARKS Recipe Name: ZEROETCH Chamber 3 Power 200W Pressure 100 mtorr Gas 1 CHF3 50 sccm Gas 2 CF4 25 sccm Gas 3 Ar 0 sccm Gas 4 O2 10 sccm Max Time = 120 seconds Silicon Etch Rate 650 Å/min 8.8 um L/S 8 um L/S Page 20

21 SCRIBE WAFER WITH ID NUMBER D1 Back Scribe on back of wafer near the wafer flat ID numbers D1, D2 etc. Front Wafer has alignment marks etched in two locations. Page 21

22 ASHER, SCRIBE, RCA CLEAN & SRD O2 + Energy = 2 O O is reactive and will combine with plastics, wood, carbon, photoresist, etc. Gassonics Asher Recipe FF RCA Clean Bench Page 22

23 RCA CLEAN APM NH 4 OH - 1part H 2 O 2-1parts H 2 O - 17parts 70 C, 15 min. DI water rinse, 5 min. DI water rinse, 5 min. HPM HCL - 1part H 2 O 2-1parts H 2 O - 17parts 70 C, 15 min. H HF sec. DI water rinse, 5 min. SPIN/RINSE DRY Page 23

24 USING EXCEL SPREADSHEET FOR OXIDE GROWTH CALCULATIONS These spreadsheets are available on Dr. Fullers webpage. Page 24

25 BRUCE FURNACE RECIPE 406 WET OXIDE 6,500Å Recipe # C Boat Out Boat In Boat Out Load Push Stabilize Ramp-Up Soak Anneal Ramp-Down Pull 800 C 800 C 800 C 25 C Interval 0 Interval 1 Interval 2 Interval 3 Interval 4 Interval 5 Interval 6 Interval 7 Interval 8 Any 0 lpm none 12 min 15 min 30 min 5 min 65 min 5 min 60 min 12 min 10 lpm 10 lpm 5 lpm 5 lpm 3.6/2 lpm 15 lpm 10 lpm 15 lpm N2 N2 N2 O2 O2/H2 N2 N2 N2 At the end of a run the furnace returns to Interval 0 which is set for boat out, 25 C and no gas flow. The furnace waits in that state until someone aborts the current recipe or loads a new recipe. Wet Oxide Growth, Target 6,500 Å, Tube 1 Page 25

26 BRUCE FURNACE Tube 1 Tube 2 Tube 3 Tube 1 Steam Oxides Tube 2 P-type Diffusion Tube 3 N-type Diffusion Tube 4 Dry Oxides and Gate Oxides Tube 4 Page 26

27 TENCORE FT-300 SPECROMAP Record: Mean Std Deviation Min Max No of Points Page 27

28 AFTER 6500Å OXIDE GROWTH 6500 Å Starting Wafer Page 28

29 SSI COAT AND DEVELOP TRACK FOR 6 WAFERS Use Recipe: Coat.rcp and Develop.rcp Page 29

30 RECIPES FOR RESIST COAT AND DEVELOP Level Level Name Resist Coat Recipe Develop Recipe Resist Thickness 0 Zero OIR-620 Coat Develop 1.0um 1 Diffusion OIR-620 Coat Develop 1.0um 2 CC OIR-620 Coat Develop 1.0um 3 Metal OIR-620 Coat Develop 1.0um 4 Hole OIR-620 Coat Develop 1.0um Hole will be placed on the back of the wafer. Alignment will be only from the flat finder on the ASML stepper. Level zero uses the ASML Combi Reticle. Page 30

31 ASML 5500/200 NA = 0.48 to 0.60 variable = 0.35 to 0.85 variable With Variable Kohler, or Variable Annular illumination Resolution = K1 l/na = ~ 0.35µm for NA=0.6, =0.85 Depth of Focus = k 2 l/(na) 2 = 1.0 µm for NA = 0.6 i-line Stepper l = 365 nm 22 x 27 mm Field Size Page 31

32 STEPPER JOB Mask Barcode: Stepper Jobname: MCEE770-MEMS4X Level 0 (combi reticle) Level Clearout (combi reticle) Level 1 Diffusion Level 2 CC Level 3 Metal Level 4 Hole Level Test1 (no alignment) Level Test2 (no alignment) Level Test3 (no alignment) Level Test4 (no alignment) Page 32

33 AFTER PHOTORESIST COAT, EXPOSE & DEVELOP Page 33

34 AFTER OXIDE ETCH Page 34

35 STRIP RESIST, RCA CLEAN Page 35

36 ION IMPLANT BORON Ion Implant B11 Dose = 1E15 cm-2 Energy = 100KeV Time ~10min at 100 µa Page 36

37 IMPLANT MASKING THICKNESS CALCULATOR Page 37

38 AFTER ION IMPLANT BORON Ion Implant B11 Dose = 1E15 cm-2 Energy = 100KeV Time ~10min at 100 µa Page 38

39 ANNEAL, DIFFUSION, OXIDE GROWTH Page 39

40 BRUCE FURNACE RECIPE 341 WET OXIDE 4,000Å Recipe # C Boat Out Boat In Boat Out Load Push Stabilize Ramp-Up Flood Soak Anneal Ramp-Down Pull 800 C 800 C 800 C 25 C Interval 0 Interval 1 Interval 2 Interval 3 Interval 4 Interval 5 Interval 6 Interval 7 Interval 8 Any 0 lpm none 12 min 15 min 20 min 5 min 20 min 5 min 40 min 12 min 10 lpm 10 lpm 5 lpm 5 lpm 10 lpm 15 lpm 10 lpm 15 lpm N2 N2 N2 O2 O2/H2 N2 N2 N2 At the end of a run the furnace returns to Interval 0 which is set for boat out, 25 C and no gas flow. The furnace waits in that state until someone aborts the current recipe or loads a new recipe. Wet Oxide Growth, Target 4000 Å Page 40

41 RECIPES FOR RESIST COAT AND DEVELOP Level Level Name Resist Coat Recipe Develop Recipe Resist Thickness 0 Zero OIR-620 Coat Develop 1.0um 1 Diffusion OIR-620 Coat Develop 1.0um 2 CC OIR-620 Coat Develop 1.0um 3 Metal OIR-620 Coat Develop 1.0um 4 Hole OIR-620 Coat Develop 1.0um Hole will be placed on the back of the wafer. Alignment will be only from the flat finder on the ASML stepper. Level zero uses the ASML Combi Reticle. Page 41

42 AFTER CONTACT CUT ETCH AND RESIST STRIP Page 42

43 PRE METAL HF DIP H HF sec. DI water rinse, 5 min. SPIN/RINSE DRY Page 43

44 AFTER METAL DEPOSITION CVC 601 Sputter Tool Pressure = 5mTorr Power = 2000 Watts Time = 30 min Thickness = ~ 1.0um Page 44

45 SPUTTER ALUMINUM CVC 601 Sputter Tool Pressure = 5mTorr Power = 2000 Watts Time = 30 min Thickness = ~ 1.0um Page 45

46 RECIPES FOR RESIST COAT AND DEVELOP Level Level Name Resist Coat Recipe Develop Recipe Resist Thickness 0 Zero OIR-620 Coat Develop 1.0um 1 Diffusion OIR-620 Coat Develop 1.0um 2 CC OIR-620 Coat Develop 1.0um 3 Metal OIR-620 Coat Develop 1.0um 4 Hole OIR-620 Coat Develop 1.0um Hole will be placed on the back of the wafer. Alignment will be only from the flat finder on the ASML stepper. Level zero uses the ASML Combi Reticle. Page 46

47 METAL PHOTO Page 47

48 AFTER METAL ETCH Page 48

49 RECIPES FOR RESIST COAT AND DEVELOP Level Level Name Resist Coat Recipe Develop Recipe Resist Thickness 0 Zero OIR-620 Coat Develop 1.0um 1 Diffusion OIR-620 Coat Develop 1.0um 2 CC OIR-620 Coat Develop 1.0um 3 Metal OIR-620 Coat Develop 1.0um 4 Hole OIR-620 Coat Develop 1.0um Hole will be placed on the back of the wafer. Alignment will be only from the flat finder on the ASML stepper. Level zero uses the ASML Combi Reticle. Page 49

50 HOLE PHOTO Page 50

51 BOSCH ICP (PLASMA THERM) Deep Reactive Ion Etch (DRIE) The Bosch process uses two chemistries, one to generate polymers and the other to etch silicon. The etch machine switches between the two every few seconds to ensure that the sidewalls are covered with polymer allowing fast, deep trench etching. (the substrate is on a chuck that is cooled by liquid nitrogen. 5µm spaces 200µm etch depth 40:1 aspect ratio 2µm/min Si etch rate >75:1 selectivity to photoresist Page 51

52 STS ETCH TOOL AT RIT Deep Reactive Ion Etch (DRIE) Page 52

53 AFTER HOLE ETCH Wet etch any oxide in holes on backside of wafer. STS info 1um each cycle Each cycle ~15 seconds ~4 um/min ~2 hours to go through 500um substrate. 9.8 Torr pressure differential SF6 and C4F8 1 to 10 um/min, Oxide, Nitride or Photoresist masks. Page 53

54 AFTER HOLE ETCH Page 54

55 TEST EQUIPMENT Manual Prober Page 55

56 K&S 780 WAFER SAW Page 56

57 AFTER SAWING AND REMOVAL OF GOOD CHIPS Wafer Sawing Movie Page 57

58 RIT PACKAGED PRESSURE SENSOR Page 58

59 ULTRASONIC ALUMINUM WIREBOND Bond 1, time=1, power=250 Bond 2, time=2, power=320 Orthodyne Electronics Model 20 Ultrasonic Wire Bonder Page 59

60 WIREBOND INTERCONNECT TO PCB Wire Bonding Movies Page 60

61 SUMMARY This project allows students to see the entire process for design, fabrication, packaging and testing of a MEMS based Microsystem. Page 61

62 1. Dr. Lynn Fuller s webpage 2. more REFERENCES Page 62

63 HOMEWORK BULK FABRICATION DETAILS 1. Draw a series of pictures that show the crossection of a pressure sensor after step 12, 16, 19 and 24. Page 63