IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 12, DECEMBER

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1 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 12, DECEMBER Modeling, Fabrication, and Characterization of Low-Cost and High-Performance Polycrystalline Panel-Based Silicon Interposer With Through Vias and Redistribution Layers Qiao Chen, Yuya Suzuki, Gokul Kumar, Venky Sundaram, and Rao R. Tummala, Fellow, IEEE Abstract Interconnections between integrated circuits and print circuit boards are primarily achieved currently with organic packages at high I/O pitch. Organic packages, however, are limited by poor thermal and dimension stabilities for them to act as fine pitch interposers. To address these challenges, silicon interposers are being developed. Current silicon interposers, based on through-silicon via (TSV) techniques, suffer from high production cost, because of expensive CMOS-grade silicon, expensive TSV process and smaller wafer sizes. They also suffer from high electrical loss in spite of thin SiO 2 interfacial layers. This paper, for the first time, demonstrates a lower cost and higher performance silicon interposer. It is based on panelbased polycrystalline silicon with through-package vias (TPVs) and redistribution layers, and a simple and double-side process with thick polymer liner inside the TPV. Electrical modeling was carried out that shows the better electrical performance of polycrystalline silicon interposer compared with traditional single-crystalline silicon interposer. The polycrystalline silicon interposer test vehicles with up to four metal layers were demonstrated and characterized. The measurement results showed good electrical performance and matched well with the simulations. Index Terms Double-side process, insertion loss characterization, polycrystalline silicon panel, silicon interposer. I. INTRODUCTION INTERPOSERS by definition connect two or more integrated circuits (ICs) with fine pitch I/Os, typically at or below 40-μm pitch on the top side and at larger pitch with flip-chip assembly on the bottom side [1] [4]. Organic substrates have not been developed into these fine pitch interposers due to their limitations in dimensional and thermal Manuscript received July 28, 2014; revised October 10, 2014; accepted October 19, Date of publication October 30, 2014; date of current version December 5, This work was supported by the Silicon and Glass Interposer Industry Consortium through the Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA. Recommended for publication by Associate Editor B. Dang upon evaluation of reviewers comments. Q. Chen, G. Kumar, and V. Sundaram are with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA USA ( qiaochen198411@gatech.edu; gokul.kumar@gatech.edu; vsunda@ece.gatech.edu). Y. Suzuki is with the School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA USA ( yuya.suzuki@ece.gatech.edu). R. R. Tummala is with the School of Electrical and Computer Engineering and the School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA USA ( rao.tummala@ece.gatech.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCPMT stabilities [5]. Interposers to date have been silicon interposers only, with through-silicon-vias (TSVs) processed in singlecrystalline silicon wafers. The requirement for through-via densities strongly depends on the applications. For example, high via densities are necessary for applications like 3-D ICs. While applications, such as 3-D wafer-level-packaging or microelectromechanical systems packaging, require significantly lower via densities [6], [7]. The silicon interposer in this paper intends to provide a low-cost solution for the latter applications and yet achieve high performance. The fabrication of traditional silicon interposers with TSV usually involves the well-known Bosch process [8], [9] to form blind vias in single-crystalline silicon wafers. Inside these TSVs, thin layers of SiO 2 are widely used as the liners to insulate the lossy silicon. There is also the need for diffusion control between copper inside TSV and silicon, which is typically accomplished using barriers such as Ti, TiN, and TaN [10], [11]. The Cu seed is then formed using sputtering process and the via is then filled with Cu by electrolytic plating. A chemical mechanical polishing (CMP) process is necessary to expose the Cu via. Although silicon interposers have been developed to address I/O pitch limitations of organic interposers, they have their own challenges. Since the number of interposers coming from 200- to 300-mm silicon wafers is low, particularly if the interposers are mm in size, serious cost concerns remain as the biggest barriers to adoption of silicon interposers. Additional challenge with silicon interposers is to do with electrical loss of silicon in spite of SiO 2 dielectric layer. This is always recognized as the second major concern with traditional silicon interposers. Tezcan et al. [12] developed a polymer-lined TSV involving etching an annular hole in silicon, filling it with polymer, and finally etching out the silicon core. Such a process, however, increases the number of steps to the already complex and expensive process to form silicon interposers. This paper addresses both the shortcomings of traditional silicon interposers by presenting an entirely different approach using polycrystalline silicon in large panel form and thick insulating polymer liners. Polycrystalline silicon in panel form is widely used in photovoltaic industry and has been extensively studied as a substrate for solar applications [13] [15]. However, it has never been studied as the electronic substrate material for the interposer applications. Polycrystalline silicon, IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 2036 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 12, DECEMBER 2014 Fig. 1. Polycrystalline silicon panel used in this paper. TABLE I THROUGH-VIA PROCESSES IN SINGLE-CRYSTALLINE SILICON INTERPOSER VERSUS POLYCRYSTALLINE SILICON INTERPOSER Fig. 2. Cross section schematic of polycrystalline silicon interposer with TPVs, wires and different ICs on both sides. as an interposer substrate, has a few advantages; simpler to fabricate than single-crystalline silicon and can be scaled to large panel sizes up to 700 mm. This large size will lower the cost of interposers by yielding more interposers. In this paper, small 150 mm 150 mm polycrystalline silicon panels (shown in Fig. 1) with thickness of 200 μm are used. These panels are fabricated using directional solidification technique, which forces the impurities to segregate into melt [16]. Due to its lower purity levels, polycrystalline silicon material presents a much lower resistivity than the traditional singlecrystalline silicon. The issue is proposed to be addressed by a low-cost and thick insulating polymer liner on the walls of through vias. Table I summarizes a comparison between the polycrystalline silicon interposer and traditional singlecrystalline silicon interposer. A cross section schematic of the polycrystalline silicon interposer with through-package-vias (TPVs) and assembly of multiple ICs is shown in Fig. 2. The double-side approach used in integrating the components on both sides will result in a reduced interposer size, leading to a miniaturized package with even lower cost. This paper presents a first, pioneering research to explore polycrystalline silicon in large panel form as a low-cost and high-performance interposer. It presents a combination of materials and processes to form TPVs and redistribution layers (RDLs). This paper has four sections. Sections I and II present the electrical modeling results, showing the performance comparison between TPVs in polycrystalline silicon interposers and TSVs in traditional silicon interposers. The detailed double-side fabrication process is Fig. 3. Schematic of (a) top view and (b) cross-sectional view of the Ground-Signal-Ground model. presented in Section III. Section IV summarizes the fabrication and electrical characterization of polycrystalline silicon interposer with up to four-metal RDL structures, including insertion loss in coplanar waveguide (CPW) lines and TPV structures. Finally, the conclusion is drawn in Section V. II. ELECTRICAL MODELING OF TPV IN POLYCRYSTALLINE SILICON INTERPOSER In this section, the electrical performance of polycrystalline silicon with TPV is simulated and compared to singlecrystalline silicon with TSV. The 3-D electromagnetic software High Frequency Structural Simulator was used to simulate the through-via structure, as shown in Fig. 3. The structure consists of two signal vias (marked as S) and four ground vias (marked as G).

3 CHEN et al.: LOW-COST AND HIGH-PERFORMANCE POLYCRYSTALLINE PANEL-BASED SILICON INTERPOSER 2037 Fig. 4. Plots of (a) insertion loss and (b) FEXT for TPV in polycrystalline silicon interposer and TSV in single-crystalline wafer silicon interpose. Fig. 5. Plots of (a) insertion loss and (b) FEXT for TPVs in polycrystalline silicon interposer with surface liners of different thickness. A typical 10 -cm silicon material with 1-μm SiO 2 liner was used as an example for single-crystalline silicon interposer; while a much lower, 0.5 -cm silicon, with a 3-μm thick, low loss polymer liner (tan δ = 0.002) was used in the polycrystalline silicon interposer. The via diameter, via pitch and silicon thickness were all the same for two different cases. Both silicon interposers were 200 μm in thickness. The diameter and pitch of these Cu-filled vias were 30 and 60 μm, respectively. Fig. 4 compares the insertion loss and far-end crosstalk (FEXT) between the two different silicon interposers. The TPV in polycrystalline silicon interposer shows a lower insertion loss and crosstalk up to 10 GHz. The superior electrical performance of such interposer is due to the thick polymer liner on both surfaces and via side-wall. This helps reduce the substrate loss and coupling in the silicon substrate. Parametric studies of electrical performance on TPV in polycrystalline silicon interposer were also carried out. Both the effects of in-via polymer liner thickness and TPV diameter have been simulated. Detailed geometry and material information can be found in [17]. These results show that the insertion loss and crosstalk can be reduced using a thicker sidewall liner. On the other hand, the electrical performance in the TPVs can also be improved by decreasing the via diameter since smaller TPVs have smaller sidewall capacitance (due to smaller diameter) and smaller substrate conductance (due to larger spacing between the TPVs). This helps in reducing the loss and their crosstalk is lower compared with the larger TPVs because of the greater spacing between the smaller TPVs. The effects of the thickness of surface liner (3, 20, and 40 μm) on insertion loss and FEXT were also simulated and the results for up to 10 GHz are summarized in Fig. 5. The silicon substrate was 200 μm in thickness with a resistivity of 0.5 -cm. The vias had a diameter of 30 μm with a pitch of 60 μm. The in-via liner was 3-μm thick. Fig. 5 shows that a thicker surface liner can result in lower insertion loss and FEXT. III. PROCESS FLOW The process flow used to fabricate polycrystalline silicon interposer, with up to four metal layers, is summarized in Fig. 6. It is consisted of four steps: 1) TPV formation; 2) TPV liner formation; 3) TPV metallization; and 4) RDL fabrication. Compared to the published TSV processes, the approach used in this paper includes: 1) unique double-side TPV process, including: a) laser ablation for via formation; b) thick polymer liner fabrication; c) dry film lithography, electro-less plated seed, and through-via filling, without any CMP process; 2) double-side process for RDLs.

4 2038 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 12, DECEMBER 2014 TABLE II VIA FORMATION IN POLYCRYSTALLINE SILICON SUBSTRATE BY LASER ABLATION Fig. 7. Top view of laser drilled via in polycrystalline silicon. substrate with excimer laser technique. But, this technology suffers from high production cost. The 355-nm picosecond lasers can further reduce the heat generated during the laser ablation process. Vias from 10- to 50-μm diameters were formed by picosecond lasers. However, this method is currently limited by slow processing speed. Considering both the throughput and cost, UV laser, operating at a wavelength of 355 nm, was chosen for TPV formation with vias of 80-μm diameter. The top view of the laser drilled viasisshowninfig.7. Fig. 6. Process flow for fabricating polycrystalline silicon interposers with TPVs and RDLs. A. TPV Formation Laser ablation is a feasible technique to form vias in polycrystalline substrates and it can be scaled to large panels [18]. Three different laser technologies (UV, excimer, and picosecond laser) were explored for via formation. All the through-vias were formed in the 200-μm-thick polycrystalline silicon panels as shown in Table II, which compares the output differences among the three laser technologies. Both small and large vias were formed by UV laser, operating at 355 nm. The ArF-based excimer laser processing with a wavelength of 193 nm was found to be more effective, resulting in less thermal damages. Smaller vias without any taper were achieved in 200-μm-thick polycrystalline silicon B. TPV Liner Formation The technical approach for the liner formation involves polymer filling in TPVs, followed by laser ablation to form an inner via, leading to in-via thick polymer liners with controlled thickness. The polymer liner serves to replace both the SiO 2 and diffusion barrier in traditional TSVs. The laser drilled silicon samples were first cleaned using plasma treatment. The silicon surface was treated with silane solution (3-aminopropyltrimethoxy silane), which leads to the formation of covalent bonds at the interface between silicon and polymer to improve adhesion. The polymer film was laminated to fill the TPVs. The lamination process can also form polymer layers on top and bottom sides of the silicon panel for insulation purposes. Two methods, with roll lamination and vacuum lamination, were used and evaluated for polymer filling. Fig. 8 shows a comparison between the single-side and double-side lamination processes. The single-side roll lamination process was first studied. However, voids were observed between polymers after filling. These voids create potential problems for the following laser ablation step. The new polymer filling method using vacuum laminator was then carried out. Both sides of the silicon substrate were laminated at the same time, leading to a faster, void-free filling process for the 200-μm-thick silicon substrate with through vias of 80-μm diameter. Adhesion between

5 CHEN et al.: LOW-COST AND HIGH-PERFORMANCE POLYCRYSTALLINE PANEL-BASED SILICON INTERPOSER 2039 Fig. 9. Top view of fabricated polycrystalline silicon interposer test vehicle. Fig. 8. Comparison between roll and vacuum lamination process. polymer and silicon was measured qualitatively by tape test for peel strength and the samples showed good adhesion. The inner vias with a diameter of 40 μm were then fabricated by UV laser ablation as shown in Fig. 6, resulting in a 20-μm-thick polymer liner. The thickness of the polymer on substrate surfaces was 40 μm. C. TPV Metallization The metallization process consists of three steps: 1) Cu seed layer formation; 2) Cu electroplating; and 3) pad formation. The polycrystalline silicon sample with polymer liner was first cleaned using plasma to remove any impurities on the surface. A low cost, double-side electroless plating process (20 min) then was used to fabricate a 1-μm-thick Cu seed layer. A void-free double-side Cu electroplating was performed in the plating tank to fill the through vias. A current density of 4A/cm 2 was used in this process for 2 h. The Cu overburdens on the surfaces were thinned down to 12 μm by a double-side chemical etching process. Dry film polymers were laminated on both surfaces of the sample followed by a lithography process to pattern the traces. The Cu was then etched by dilute CuCl 2 solution and photoresist was stripped by potassium hydroxide to finally form the Cu pads. D. RDL Fabrication To fabricate the RDLs, another two build-up polymer dielectric layers were formed on the surface by double-side vacuum lamination processes. Then, 355-nm UV laser ablation was used to form blind microvias in the cured polymer. The microvias and build-up layers were covered by 1-μm-thick Cu seed layer with electroless plating, followed by semiadditive plating with double-side dry film photoresist lamination and lithography process. The final steps included the Cu seed etching by CuCl 2 solution and photoresist stripping. IV. TEST VEHICLE FABRICATION AND CHARACTERIZATION By integrating the processes presented in Section III, the polycrystalline silicon interposer test vehicles were Fig. 10. Cross section picture of polymer-lined TPV with four metal layers. successfully fabricated. Fig. 9 shows the top view of the completed 150-mm 150-mm size polycrystalline silicon panel with TPVs and RDLs on both sides. The mask design involves transmission lines with different lengths as well as CPW-TPV transitions. The microsection photograph of the four-metal layer interposer is shown in Fig. 10. The insertion loss of CPW traces was measured and the results were compared with the simulation results for correlation. 160-μm wide transmission lines with a gap of 36.5 μm between the signal and ground were fabricated. The vector network analyzer measurements were performed up to 10 GHz, after calibrations. Fig. 11 shows the simulation and insertion loss measurements for both 6.2- and 11.2-mm CPW traces without vias. Fig. 11 shows that the 6.2- and 11.2-mm transmission lines had <1.5 and 2.5 db insertion loss, respectively at 10 GHz. This translates to a loss of 0.24 and 0.22 db/mm at 10 GHz, respectively. The low insertion loss in CPW trace matched the simulation results very well. However, longer traces followed the trend of increased insertion loss rapidly. This decreased the overall signal quality. The insertion loss of CPW-TPV transition in the two-metal layer structure is shown in Fig. 12 with signal lines of different lengths. The impact of transmission line length on the insertion loss was studied. The results show that the insertion loss increased with larger signal length but the total impact of length increase on the insertion loss at lower frequencies was negligible. Thus, local routing can be performed in the

6 2040 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 4, NO. 12, DECEMBER 2014 Fig. 13. Measurements of insertion loss in CPW lines, TPVs, and blind via transitions in structures with different numbers of metal layers. Fig. 11. Simulations and measurements of insertion loss in CPW lines (without TPV) with different lengths. V. CONCLUSION This paper presents, for the first time, the modeling, fabrication, and characterization of polycrystalline panel-based silicon interposer as a low-cost and high-performance solution for packaging next generation ICs. These interposers were fabricated with lower cost, and lower resistivity polycrystalline silicon, compared with higher cost and higher resistivity single-crystalline silicon. Through via formation in these interposers was achieved using 355-nm UV laser. Thick polymer liner, that is, proposed to reduce the silicon loss, was formed with a low cost, double-side process. The polycrystalline silicon interposer test vehicle with metallized TPVs and RDLs were successfully demonstrated. Both electrical modeling and characterization results indicate that polycrystalline silicon interposer can achieve high performance. Fig. 12. Simulations and measurements of insertion loss in CPW-TPV structures with different line lengths. interposer between signal TPVs without significant impact on the signal quality. The model-to-measurement correlation was also conducted and a good model to hardware correlation was observed. Electrical performance of CPW lines and via transitions in structures with up to four-metal layers was also characterized and insertion loss results were compared in Fig. 13. The length of the CPW line was fixed at 1 mm. As shown in Fig. 13, the one-metal layer structure consisted of only the transmission line on the top metal layer, while the two-metal layer structure included blind vias, which can transfer signals to the second metal layer. Both the three-metal layer and four-metal layer structures included TPVs to connect the lines to the metal layers on bottom side. These measurements show that the insertion loss increased with the frequency. The loss also increased with the number of metal layers. This is due to the added loss, coming from via transitions. The overall loss was low and remained below 0.9 db at 2.4 GHz for the four-metal layer structure. This result indicates that multiple signal layer escape routing is possible due to the good isolation of the thick polymers to achieve low loss silicon interposers. ACKNOWLEDGMENT The authors would like to thank the full members and supply chain partners for their funding and intellectual support. They would like to thank T. Iga and M. Tada from Zeon Corporation for polymer process guidance, and Micron Laser for their support. REFERENCES [1] R. R. Tummala, Introduction to System-on-Package (SOP): Miniaturization of the Entire System. New York, NY, USA: McGraw-Hill, May [2] R.R.Tummalaet al., Trend from ICs to 3D ICs to 3D systems, in Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, USA, Sep. 2009, pp [3] E. Klink, B. Garben, A. Huber, D. Kaller, S. Grivet-Talocia, and G. A. Katopis, Evolution of organic chip packaging technology for high speed applications, IEEE Trans. Adv. Packag., vol. 27, no. 1, pp. 4 9, Feb [4] B. Garben, A. Huber, D. Kaller, and E. Klink, Organic chip packaging technology for high speed processor applications, in Proc. 6th IEEE Workshop Signal Propag. Interconnects, Pisa, Italy, May 2002, pp [5] P. M. Raj et al., Fundamental limits of organic packages and boards and the need for novel ceramic boards for next generation electronic packaging, J. Electroceram., vol. 13, nos. 1 3, pp , [6] J. Lannon et al., Fabrication and testing of a TSV-enabled Si interposer with Cu- and polymer-based multilevel metallization, IEEE Compon., Packag., Manuf. Technol., vol. 4, no. 1, pp , Jan [7] P. A. Thadesar and M. S. Bakir, Novel photo-defined polymer-enhanced through-silicon vias for silicon interposers, IEEE Compon., Packag., Manuf. Technol., vol. 3, no. 7, pp , Jul

7 CHEN et al.: LOW-COST AND HIGH-PERFORMANCE POLYCRYSTALLINE PANEL-BASED SILICON INTERPOSER 2041 [8] R. Knizikevičius, Simulation of anisotropic etching of silicon in SF 6 +O 2 plasma, Sens. Actuators A, Phys., vol. 132, no. 2, pp , [9] I. U. Abhulimen, S. Polamreddy, S. Burkett, L. Cai, and L. Schaper, Effect of process parameters on via formation in Si using deep reactive ion etching, J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct., vol. 25, no. 6, pp , Nov [10] M. Takeyama, A. Noya, K. Sakanishi, H. Seki, and K. Sasaki, Solid-phase reactions of diffusion barriers of Ti and TiN to copper layers on SiO 2, Jpn. J. Appl. Phys., vol. 35, no. 7, pp , [11] Y. K. Lee, K. M. Latta, K. Jaehyunga, and K. Lee, Study of diffusion barrier properties of ionized metal plasma (IMP) deposited TaN between Cu and SiO 2, Mater. Sci. Semicond. Process., vol. 3, no. 3, pp , [12] D. S. Tezcan, F. Duval, H. Philipsen, O. Luhn, P. Soussan, and B. Swinnen, Scalable through silicon via with polymer deep trench isolation for 3D wafer level packaging, in Proc. 59th Electron. Compon. Technol. Conf. (ECTC), San Diego, CA, USA, May 2009, pp [13] A. F. B. Braga, S. P. Moreira, P. R. Zampieri, J. M. G. Bacchin, and P. R. Mei, New processes for the production of solar-grade polycrystalline silicon: A review, Solar Energy Mater. Solar Cells, vol. 92, no. 4, pp , [14] J. Degoulange, I. Périchaud, C. Trassy, and S. Martinuzzi, Multicrystalline silicon wafers prepared from upgraded metallurgical feedstock, Solar Energy Mater. Solar Cells, vol. 92, no. 10, pp , [15] S. Pizzini, Towards solar grade silicon: Challenges and benefits for low cost photovoltaics, Solar Energy Mater. Solar Cells, vol. 94, no. 9, pp , [16] A. A. Istratov, T. Buonassisi, M. D. Pickett, M. Heuer, and E. R. Weber, Control of metal impurities in dirty multicrystalline silicon for solar cells, Mater. Sci. Eng., B, vol. 134, nos. 2 3, pp , [17] Q. Chen et al., Design and demonstration of low cost, panel-based polycrystalline silicon interposer with through-package-vias (TPVs), in Proc. IEEE 61st Electron. Compon. Technol. Conf. (ECTC), Lake Buena Vista, FL, USA, May/Jun. 2011, pp [18] H. Booth, Laser processing in industrial solar module manufacturing, J. Laser Micro/Nanoeng., vol. 5, no. 3, pp , Gokul Kumar received the B.E. degree in electronics and communications engineering from Anna University, Chennai, India, in 2007, and the M.S. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2010, where he is currently pursuing the Ph.D. degree with the 3-D Systems Packaging Research Center. He was with Qualcomm MEMS Technology, Inc., San Jose, CA, USA, in 2012, as an Interim Engineering Intern. His current research interests include electrical modeling and design of glass, silicon, and organic interposers for 3-D system integration. Venky Sundaram received the B.S. degree from IIT Mumbai, Mumbai, India, and the M.S. and Ph.D. degrees in materials science and engineering from the Georgia Institute of Technology, Atlanta, GA, USA. He is currently the Director of Research and Industry Relations with the 3-D Systems Packaging Research Center, Georgia Institute of Technology. He is also the Program Director of the Low-Cost Interposer and Packages Industry Consortium with over 25 active global industry members. He is a globally recognized expert in packaging technology, the Co-Founder of Jacket Micro Devices, Livonia, MI, USA, and an RF/Wireless Engineer of AVX Corporation, Fountain Inn, SC, USA. He has authored over 15 patents and 100 publications. His current research interests include system-on-package technology, 3-D packaging and integration, ultrahigh-density interposers, embedded components, and systems integration research. Dr. Sundaram received several best paper awards. He is the Co-Chairman of the IEEE Components, Packaging, and Manufacturing Technology Society Technical Committee on High-Density Substrates and the Director of Education Programs with the Executive Council of International Microelectronics and Packaging Society. Qiao Chen received the B.S. and M.S. degrees in materials science and engineering from Tsinghua University, Beijing, China, in 2006 and 2008, respectively. He is currently pursuing the Ph.D. degree in electrical and computer engineering with the 3-D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA. His current research interests include the modeling, design, demonstration, and characterization of through-silicon-via and silicon interposers for 3-D integration. Yuya Suzuki received the B.S. and M.S. degrees in applied chemistry from the University of Tokyo, Tokyo, Japan, in 2005 and 2007, respectively. He is currently pursuing the Ph.D. degree with the Department of Materials Science and Engineering, 3-D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA. He joined Zeon Corporation, Tokyo, in 2007, as a Research Engineer. He is currently with the 3-D Packaging Research Center, Georgia Institute of Technology. His recent research is development of glass interposer and passive embedded RF module using low-loss polymer material. His current research interests include polymer synthesis, polymer processing, and organic-inorganic hybrid materials. Rao R. Tummala (F 93) received the B.S. degree from the Indian Institute of Science (IIS), Bangalore, India, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, Champaign, IL, USA. He was a fellow of IBM Corporation, Armonk, NY, USA, pioneering the first plasma display and multichip electronics for mainframes and servers. He is currently the Distinguished and Endowed Chair Professor, and the Founding Director of the National Science Foundation s Engineering Research Center, Georgia Institute of Technology, Atlanta, GA, USA, pioneering Moore s law for system integration. He has published over 500 technical papers and holds 74 patents and inventions, and has authored the first modern book entitled Microelectronics Packaging Handbook, the first undergrad textbook entitled Fundamentals of Microsystems Packaging, and the first book introducing the system-on-package technology. Prof. Tummala is a member of the National Academy of Engineering and the President of the IEEE Components, Packaging, and Manufacturing Technology Society, and the International Microelectronics and Packaging Society. He has received many industry, academic, and professional society awards, including the Industry Week s Award for improving the U.S. competitiveness, the IEEE David Sarnoff Award, the International Microelectronics and Packaging Society Dan Hughes Award, the Engineering Materials Award from ASM, the Total Excellence in Manufacturing Award from the Society of Manufacturing Engineers, and the Distinguished Alumni Awards from the University of Illinois at Urbana-Champaign, IIS, and the Georgia Institute of Technology. He was a recipient of the Technovisionary Award from the Indian Semiconductor Association and the IEEE Field Award for contributions in electronics systems integration and cross-disciplinary education in 2011.