Super Thin Flip Chip Assemblies on Flex Substrates - Adhesive Bonding and Soldering Technology Reliability Investigations and Applications

Transcription

1 Super Thin Flip Chip Assemblies on Flex Substrates - Adhesive Bonding and Soldering Technology Reliability Investigations and Applications Julian Haberland, Barbara Pahl, Christine Kallmayer*, Rolf Aschenbrenner*, Herbert Reichl* Technical University of Berlin, Research Center of Microperipheric Technologies *Fraunhofer Institute for Reliability and Microintegration Gustav-Meyer-Allee 25, D Berlin, Germany julian.haberland@izm.fraunhofer.de, phone : +(49) , fax : +(49) barbara.pahl@izm.fraunhofer.de, phone : +(49) , fax : +(49) Abstract Thinned silicon chips with very thin bumps (5-7µm) mounted on flexible substrates open up new dimensions in packaging technologies. The use of flexible substrates enables a large variety of geometric possibilities including folding and bending. Conventional flip chip technology using pick&place and standard reflow processes is not suitable for the assembly of ultra thin components. This is based upon different technological reasons, as e.g. excessive bending of components (critical coplanarity) as well as wetting concerns and intermetallic phase formation of small solder volumes. According assemblies may be achieved using thermode bonding processes that allow for different solder and adhesive bonding technologies. If necessary, both types may fulfill lead free requirements. The work is focused on the comparison of the reliability between flip chip modules of less than 150 µm overall thickness bonded with solder and adhesive flip chip technologies. Assemblies with thin electroplated CuSn bumps bonded on flexible substrates with Cu metallization are compared with identical chip components with thin Ni bumps bonded with ACA (Anisotropic Conductive Adhesive). For the investigations in this study a test chip layout with 100µm pitch was used. Samples have been subjected to thermal cycling conditions, high temperature storage and temperature humidity test. Electrical measurements of Four-Point-Kelvin (4PK) resistances gave results on degradation of ultra thin flip chip contacts. SEM and EDX analysis have been performed to inspect intermetallic phase formation in ultra thin solder layers. As a successful application for ultra thin flip chip assemblies on flex, functional modules, assembled within a nationally funded project (funded by BMBF) are demonstrated. Key Words: thin, flex, Flip Chip, adhesive, solder, reliability Introduction Miniaturization is a key issue to achieve advanced performance of electronic devices and to decrease the overall cost of an electronic package. In this respect the Flip Chip technology provides excellent capabilities to meet the demands of recent and future products. Trends are going towards thin and lightweight products which make the use of flexible substrates and ultrathin chips with very thin bumps very attractive (Figure 1c)-d)). Furthermore, such combination has great potential under geometric considerations, ranging from super thin two dimensional arrangements up to three-dimensional folded or stacked modules. The former may be interesting for applications such as security tags, identification labels, medical implantable devices, chip in paper etc. Here, the direct flip chip interconnection of ultrathin IC s and subsequent high reliability demands is a matter of great concern. Embedding technologies as Chip-in- Substrate-Package [1] give large opportunities for 3D packaging using die bonded thinned chips and build up technologies on organic substrates. Another development has been seen by embedding of flip chip bonded chips and lamination of flexible substrate layers to manufacture smart flexible PCB s [2]. 3D-packaging concepts may be used for todays memory modules and common multi chip modules as well as for the design of future products, such as self-sustaining microsystems in sensor networks. An according overview is given in [3], where a paper collection is reporting concepts and applications, various system integration technologies (e.g. ultra thin flip chip interconnects) energy and antenna concepts as well as about software aspects. Key technologies for ultra thin Flip-Chip-On- Flex (FCOF) are either solder or adhesive joining

2 processes. Both may fulfil lead free requirements. Solder joining is still the most common technology but due to the trend to low cost substrates with limited thermal stability (and lead free requirements), adhesive based processes attract more and more interest. To achieve minimal asssembly heights the substrate-sided metallization thickness has been reduced to 5-8 µm. Polyimide substrates have been used. Close to standard test methods, samples of soldered and adhesive bonded modules were tested in thermal cycles, temperature / humidity and thermal ageing chambers. 1. Technologies As wafer thinning is now commecially available to 10 µm thickness, wafer preparation, mounting and integration technologies for thin and ultra thin chips are more and more important. Figure 1: miniaturization potential of ultra thin flip chip assemblies The reliability is one of the key tasks to be investigated as, among other effects, a partially technologically driven but intended reduction of the interconnection gap (Figure 1c), 1d)) may lead to an aggravated stress-strain- relationship in the interconnection. In terms of very small solder joints this becomes even more critical as the intermetallic compound layer tend to occupy a large fraction of the solder volume or even the whole solder contact is converted in intermetallics after the bonding process. The solder joints may become more brittle when excessive intermetallics are formed at the interfaces [4]. The most promising lead free solder systems for smallest solder volumes are Sn-based systems like SnAgCu und SnCu solder. Otherwise large experience has been gained out with AuSneutectic solder bumps. In the current study samples with electroplated CuSn bumps have been investigated. Most challenging are the smallest bump heights of about 5 µm on chip side. From the three common adhesive bonding technologies (Anisotropic conductive Adhesive, Non Conductive Adhesive, Isotropic Conductive Adhesive) the focus has been set on Anisotropic Conductive Adhesive (ACA), as this technology has the greatest potential with regard to gap minimization, fine pitch capability and reliability prospectively [5]. Bump thickness has been reduced from common 20 µm to 3µm. 1.1 Cu/Sn solder Wafer Bumping Wafer thinning technologies have been applied after bumping processes using bump protection layers. Smooth thinning technologies with respect to the integrity of the bumps after thinning are necessary. The lead free CuSn bumping metallurgy was chosen. Very thin layers of tin were plated on top of Cu sockets. Uniformity of the thin layers during electroplating is most important to ensure consistent quality of flip chip bonded assemblies. Bump height deviations of 3% have been achieved using diffuser plating rings in the cup plater. All bumps have been used in the as plated condition without prior reflow process. The topography of a CuSn-bump as plated can be seen in figure 2. Figure 2: electroplated CuSn bump on testchip, bump height 6µm, chip thickness 30µm, as plated condition On top of a Cu socket the rough surface of the thin Sn-layer is to be mentioned. Further experiments using reflowed chips for flip chip mounting showed excessive phase formation right after the reflow. So a second reflow process during mounting was not possible.

3 Thermode bonding The thermode bonding technology is based on fast reflow soldering by pulse heating. The fast process allows the use of low cost materials with low temperature resistance for flip chip soldering at high temperatures without damage of the flex. It is even possible to apply the underfill material before the placement of the die and perform underfilling and bonding in one step. The preapplication of noflow underfiller can either be done by stencil printing or by dispensing. The use of noflow underfiller today is limited by soldering temperatures. In case of eutectic SnCu solder noflow underfiller was successfully established. 1.2 ACA Wafer bumping Common bumps for ACA technology are either made by mechanical stud bump bonding [6] or various chemical deposition technologies, ranging from evaporation to plating processes. Here, electroless nickel deposition has been used, as it benefits from its low cost potential [7, 8]. The standard electroless nickel UBM for high reliability has a thickness of 5 µm but only a minimum of 1 µm is necessary to have a closed and void free nickel layer [9]. The used test chips had a final Ni(Au) thickness of 3 µm (Figure 3). Figure 3: 3µm Ni(Au) bump ACA bonding The ACA bonding process requires a certain pressure to trap electrically conductive particles between the chip bumps and the substrate metallization to form an electrical contact. Applied heat on the bonding tool and chuck is needed to cure the adhesive, which is usually an epoxy based material. Adhesives are of paste or film form either. Here, an adhesive film has been used for the tests. 2. Experimentals 2.1 Layouts Following test layouts have been used: Substrate: - Polyimide (Espanex), - 50µm thickness - adhesiveless copper metallization, 6µm thickness Chips: - Silicon, 5x5mm², - teststructures for electrical measurements of 4 Daisy-Chain and 8 Four-Point-Kelvin-Structures, I/Os total, - chip thickness 50µm - pitch 100µm - solder bump metallurgy CuSn, Cu socket height 5µm, Sn cap height 2µm, bump diameter 45µm, - bump metallurgy for ACA 3 µm Ni(Au) 2.2 Materials Noflow Underfiller As the gap between substrate and chip is very low, capilary flow underfiller is not able to flow into it. Noflow underfiller are composed for conventional reflow cycles, not for fast thermode bonding processes. The bonding profile was adapted to garanty good soldering results and fully cured underfill material after a post curing process. ACF A commercially available ACF (Anisotropic Conductive Film) has been chosen. Application is such that after the tape is prebonded under low temperature, a coverlayer is manually released and the main bonding under pressure and temperature is finally performed. Table 1 summarizes the main material properties of both materials. Table 1: properties of the material selection NoFlow ACF Underfill Tg [ C] CTE [ppm/ C] 75, T<125 C 55 ( C) 550 ( C) E-modulus [GPa] 2,7 1,4 Filler n.a 3 µm Polymer/Au 2.3 Assembly For assembling a high precision Toray 2400 Flip Chip Bonding machine has been used. For both, soldering and adhesive bonding technologies, a two step bonding process has been applied. After dispensing noflow underfill, respectively prebonding of ACF, the chip is first alligned and placed under low pressure. Before the main bonding step, a thin teflon tape is automatically picked from another tray, the tool is then roughly alligned and finally pressure and heat is applied to chip and substrate. A non-wetting tool surface is necessary due to hardly

4 controllable volumes of noflow underfill and adhesive tape that squeezes out of the small gap of approximately 10 µm. Cu/Sn soldering The maximum bonding temperature is about 40K higher than the melting point of the eutectic CuSn solder. Bonding force has to be applied, as free reflow is not feasible. This is based on oxidation of bumps and substrate metallization as well as the high demands on planarity due to the small bump heights. Bonding force has to be optimized with respect to optimal soldering results and carefulness in the manner to avoid breaking of the thin chips. The substrate was heated up to 80 C to prevent massive heat flow in the bonding table. Cross sections have been made in initial state after bonding (Figure 4). Table 2: reliability test conditions Cu / Sn ACF Thermal Cycles [ C] -55/ /+125 Thermal Ageing [ C] Temp./Humidity [ C/%RH] 85/85 85/85 Figure 5: Cross section of ultra thin ACF interconnction in initial state after bonding Figure 4: Cross section of ultra thin CuSn interconnction in Initial state after bonding Here, wetting and melting behaviour as well as alignment accuracy have been investigated. In most cases small voids inbetween the solder layer and the copper tracks have been observed. Voids at the interface between Cu and solder have been reported by Mei [10] and will be further investigated on their effects on reliability. ACA bonding Multi partition substrates of 4x4 assemblies were automatically assembled. The substrate was heated up to 70 C to allow good wetting and to prevent voiding. Cross sections have been made in initial state after bonding (Figure 5). 3. Reliability Investigations Table 2 shows the reliability test conditions chosen for both technologies. The thermal cycles have been performed in a Voetsch VT7012 S3 three chamber oven. The total time of one cycle is 30 min -55 C, 25 C, 12min@+125 C). Temperature/Humidity tests have been done in a TEC Thermotec Temperature&Humidity Chamber PL-2K and thermal ageing has been done in an Voetsch hot storage oven. All electrical measurements have been made offline. As failure criterion an increase of the 4PK-resistances over 50 mohm or open daisy chain contacts have be defined. The graphics in Figure 6 summarize the reliability results. In initial state all 4PK-resistances have relatively low values compared with flip chip solder or ACA contacts with thicker contact metallizations. Cu/Sn soldered interconnects have values of around 3 mohm with very small deviations (± 1 mohm), ACF bonded initial contacts are only slightly higher (4,5 mohm), but with larger deviations (± 4 mohm). Smaller contact areas and remaining oxide layers may have been the cause. Up to 2000 cycles Cu/Sn soldered modules have not failed and no increase of resistivity has been observed. ACF bonded samples have not failed up to 2750 cycles. The standard deviation have only slightly increased up to the end after 5000 cycles. The samples reach similar high reliability in thermal ageing. Attention should be paid to the fact that the Cu/Sn modules have been exposed to 150 C whereas ACF samples have been put into 125 C. First failures of Cu/Sn soldered modules can be observed after 2500 h, the 4PK-values remain quite constant within the total testing time (5000 h). ACF samples have not shown any failure up to 3500 h in 125 C, the standard deviations remain relatively constant.

5 Cu/Sn samples ACF samples Figure 6: mean value of 4P-Kelvin resistance and failures of Cu/Sn soldered and ACF bonded samples in thermal cycling, thermal ageing and temperature/humidity, failure criteria: R > 50 mohm Both technologies have not shown such high reliability in the temperature / humidity test (85 C/85%RH) considering a failure threshold of R>50mOhm. The resistance values of soldered contacts steadily increase from averaged 3 to 12 mohm. The deviations show strong increase. After 1000 h about 3% failure have occurred. First ACF bonded devices have failed very early. The final failure rate of 20 % has been reached after 300 h, then it stays constant. The averaged resistance only slightly increase with rising standard deviations. Both technologies have revealed high reliability in thermal cycling conditions. Actually, fatigue crack, brittle fracture and interfacial delamintaion are the most common thermomechanically induced failures. They result from stresses and strains due to thermal loading and different CTEs of the package

6 materials. Normally, a thin interconnection height evidently leads to an aggravated stress-strain relationship until the assembly does not bend or warp. Obviously, the fact of a certain flexibility of the assembly due to the use of thin chips and flexible substrates, cares for the necessary stress relief on ultrathin interconnects in thermal cycling conditions. Additionally, a reduction of critical stresses may have been achieved by the use of low profile components. In this respect, it is less surprising, that a steady temperature load of 150 C, respectively 125 C, is alike harmless. Nevertheless, the used noflow underfill and ACF materials show extraordinary temperature stability. Evidently, the presence of humidity and temperature and its consequences seriously affects the ultra thin interconnection of soldered and ACF bonded devices. Supposingly, the moisture absorption of the polyimide substrate as well as of the noflow underfill and ACF materials are the cause for failures (R>50mOhm) and increasing resistivities. Following effects may have occurred. Cu/Sn solder Corrosion effects have been detected in soldered assemblies. Cu 6 Sn 5 -IMC is very unstable in moisture environment whereas Cu 3 Sn shows a stable behaviour. This can be seen in figure 7. Here, a crack in the silicon chip has effected delamination of underfiller layer and IMC corrosion. IMC phase formation in thermal cycling samples has been investigated. At the substrate side interface the formation and growing of the intermetallics is not as uniformly as at the chip side interface. Here, a lot of voids have been detected, even the mechanical and electrical contact is very well (Figure 9). The wetting of the solder on the substrate metallization is suboptimal, which can be related to the limited substrate temperature during bonding. Figure 8: Cu/Sn interconnection after 1000 hours thermal cycling (-55 C / +125 C) For process control during bonding comparable to results from temperature/humidity testing the growing of Cu3Sn has to be optimized to reach a thermodynamic stable status after bonding. The assumption is that if the stable IMC Cu3Sn is fully grown through inside the bumps from chip to substrate there will not be further influences on reliability. The ingress of moisture has to be inhibited by fully cured and well attached underfiller to chip and substrate. Figure 7: Cu/Sn interconnection after 3000 hours temperature / humidity test (85 C/85%RH) A cross section after 1000 thermal cycles is shown in figure 8. Here, between the Cu bump from chip side and the Cu track from substrate side a fully converted Cu 3 Sn can be observed. Only in the border areas of the bump, small zones of Cu 6 Sn 5 are to be seen. Figure 9: cross section after 3000 thermal cycles (- 55 C/+125 C) ACF The averaged rising 4PK-resistances (figure 6)may have been caused by corrosion of Cu due to moisture absorption combined with a decrease of contact area due to swelling and relaxation. Obvious and visible failure mechanisms that cause the failures (R>50mOhm) have not been detected. Figure 10

7 shows a cross section of one representative contact of a failed 4PK-structure. So far, no apparent difference, such as a delamination or crack, to the initial appearance of such contacts (figure 5) could be found. Here, it has to be pointed out that total loss of the electrical contacts between chip and substrates have rarely been measured. Figure 11: unfolded prototypes of sensor knots based on standard flex technology Pi/Cu(NiAu)(top) and waferlevel thinfilm technology Pi/Cu(NiAu) (bottom) before removing programming connector Figure 10: cross section of ACF sample after 1000 h temperature / humidity (85 C/85%RH), R 1Ohm 4. Applications Due to the large variety of different electronic products, there is a wide application range for the above described thin chip integration technologies. A first step with a verification of the technology, using functional microcontrollers and RF chips, has been made within the project AVM, funded by the German Federal Ministry for Education and Research (BMBF). Its goal was the development of autarkic sensor networks, based on so-called electronic grains e-grains [11]. Based on a high number of knots, as small as possible and autonomous, this concept is supposed to serve as a technical basis for ubiquitous computing in various fields, as e.g. medical applications, RF-ID (logistics) and consumer applications. One of several possible technical approaches is making use of ultrathin polymeric foils, serving as carriers for different active and passive components, including sensors, antennas and energy supply. Waferlevel thin film technology attracts interest because of its multi-layer, three-dimensional wiring options, integration potential of passive components within a certain range and mechanical flexibility for optional folding operations. Unfolded prototypes of assembled sensor knots with an initial socket for programming issues are depicted in figure 11. ACP and ACF flip chip assembly has been performed after pick & place and reflow of SMT devices (0201 minimum). Single dimensions of an ultrathin ACP flip chip contact on a PI thin film carrier of appx. 20 µm thickness are depicted in figure 12. Figure 12: ultrathin ACP contact, Si chip with 3 µm electroless Ni(Au) bump, 20 µm PI thin film substrate with Cu(NiAu) metallization 5. Conclusions A comparison with respect to the reliability in thermal cycles, temperature/humidity and thermal ageing conditions between ultrathin CuSn soldered and ACF bonded thin flip chip devices has been drawn. The samples have been assembled with thermode bonding processes. The used chips (Si) and substrates (Pi/Cu) had a thickness of 50 µm, the contact height (gap) was reduced to appx. 10 µm. Very low initial contact resistances below 10 mohm have been achieved. ACF bonded devices have shown larger deviations, probably due to varying contact areas and possibly remaining oxide layers. The modules of both flip chip technologies have shown excellent reliability and no failure in thermal cycles up to 2000 thermal cycles (Au/Sn) respectively 2500 (ACF). Similar high reliability

8 have been reached in 85 C thermal ageing conditions. Here, ACF bonded samples have not failed up to the final testing time of 3500 h. Cu/Sn soldered modules first failed after 2500 h. The samples have shown poorer reliability in 85 C / 85 % RH climate chambers under consideration of a maximum 4PK-resistance of 50 mohm as failure criterion. With regard to Cu/Sn some possible degradation mechanisms, as corrosion of Cu 6 Sn 5 - IMC, were detected. Supposed failure mechanisms of ACF contacts, as corrosion or loss of contact, due to water absorption and relaxation, could not have been backed up with present analytics as optical or scanning electron microscopy. Within the nationally funded project AVM (funded by BMBF) a first successful implementation of ultrathin flip chip contacts in combination with polyimide thin film substrates has been demonstrated. Here, functional semiconductors, as microcontrollers and RF chips (passive components, antenna and energy supply), has been assembled to form a network of autarkic sensorknots. Montage, ISHM Conference 1996, Munich, Oct , Mei, Zequn., Kirkendall Voids at Cu/Solder Interface and their Effects on Solder Joint Reliability, Proc 55 th Electronic Components and Technology Conf, Orlando, FL, June. 2005, pp References 1. Chen, Yu-Hua., Chip-in-Substrate, CiSP, Technology, Proc 6 th Electronic Packaging Technology Conference 2004, Singapur, pp Loeher, T., Smart PCBs manufacturing Technologies, Proc 6 th Conference on Electronic Packaging Technology 2005, Shenzen, China, pp. 3. Frequenz, Journal of Telecommunications, vol. 3-4 / 2004, 4. Pahl, B., Kallmayer, Ch., Aschenbrenner, R., Reichl, H., Ultrathin Assemblies on Flexible Substrates, Proc 7 th Electronics Packaging Technology Conference 2005, Singapore, pp Haberland, J., Kallmayer, Ch., Ultra Thin Flip Chip Interconnects, Frequenz, Journal of Telecommunications, vol. 3-4 / 2004, pp Klein, M., Oppermann, H., Aschenbrenner, R., Reichl, H. Single Chip Bumping, Proc. IMAPS 98, San Diego, Ca, Nov. 1 4, 1998, pp Ostmann, A., Klöser, J., Aschenbrenner, R., Reichl, H., Strategies For Low Cost Flip Chip Assembly, 10th International Conf. On Flip Chip Ball Grid Arrays and Advanced Packaging (ITAP 98), San Jose, Ca, Feb , 1998, 8. Ostmann, A., Klöser, J., Reichl, H., Implementation Of A Chemical Wafer Bumping Process, Proc. IEPS, San Diego, Ca, Ostmann, A., Motulla, G., Stromlose Wafermetallisierung für die kostengünstige Flip Chip