Development of Underfilling Method for Flip Chip Mounted VCSEL

Transcription

1 Oda et al.: Development of Underfilling Method for Flip Chip Mounted VCSEL (1/7) [Technical Paper] Development of Underfilling Method for Flip Chip Mounted VCSEL Takuya Oda*, Takayuki Tanaka**, and Teijiro Ori* *Optics and Electronics Laboratory, Fujikura Ltd., 14 Mutsuzaki, Sakura, Chiba , Japan **Cloud Communications Business Development Division, Fujikura Ltd., 14 Mutsuzaki, Sakura, Chiba , Japan (Received August, 13; accepted November 8, 13) Abstract We developed the reliable flip chip mounting structure of VCSELs without hermetic sealing to realize 14 Gbps transmission modules. Underfill resin is sometimes used to protect VCSELs when hermetic sealing is not applied. However, it was shown that cracks occur inside VCSELs if Young s modulus of underfill resin is high. The cracks can be prevented if we avoid the arrangement of underfill resin of high Young s modulus on the mesa parts of VCSELs. We considered two mounting methods to prevent this failure. The first method is to use underfill resin of low Young s modulus. The other uses a structure where the air caps cover the mesa parts. We evaluated these methods and confirmed that the cracks do not occur in either case. Keywords: Interconnection, Flip Chip, VCSEL, Underfill Resin, Thermal Stress 1. Introduction Scales of high performance computing (HPC) systems and data centers (DCs) are expanding rapidly every year, and their performances are improving drastically.[1, 2, 3] Interconnection cables for HPC systems and DCs require higher speed and longer distance transmissions. Copper cables are being used for interconnection cables, but they will not meet these requirements.[4] On the other hand, active optical cables (AOCs) are attracting much attention due to their superior performances.[1, 2, 4] They convert an electrical signal into an optical signal by electric-optic (EO) convertor, transmit it by optical fiber, and finally the optical signal is converted into the electrical signal by optic-electric (OE) convertor. The EO-OE modules are called optical engines, in which VCSEL, PD and control ICs are mounted on one substrate.[5] The flip chip mounting technique is suitable because it is superior in terms of high speed transmission or space saving. Since VCSELs are compound semiconductor devices, their reliabilities are sensitive to the outer environment. Therefore, they are often used with hermetic sealing. Although miniaturization and low cost are important, it is difficult to meet these requirements by hermetic sealing. When VCSELs are not packaged hermetically, they need to be protected from the outer environment, especially moisture and/or dusts. The moisture is dealt with by the improvement of the passivation of VCSELs. However, it is not easy to protect the light path from the dust. Although filling with transparent underfill resin is a possible solution, it was reported that the reliability of VCSELs will get worse by underfill resin.[6] This paper describes the method which enables the reliable flip chip mounting structure of VCSELs without hermetic sealing. It is realized by avoiding the arrangement of underfill resin of high Young s modulus on the mesa parts of VCSELs. We prepared the samples based on this idea and confirmed their high reliability. 2. Structure of Materials and Evaluation Methods 2.1 Structure of optical devices in optical engines Figure 1 shows the mounting structure of optical devices in optical engine. 4-channel VCSEL array and PD array are supplied as bare chips and they are bonded face down by solder bumps on a glass substrate. Optical devices will be contaminated by the flux residue, so soldering using flux is not suitable. AuSn (8 wt%-au, wt%-sn) solder is used for fluxless bonding.[7] As mentioned Underfill resin Solder bump PD array VCSEL array Glass substrate Light path Light path Fig. 1 Mounting structure of optical devices in optical engine. Copyright The Japan Institute of Electronics Packaging 63

2 Transactions of The Japan Institute of Electronics Packaging Vol. 6, No. 1, 13 above, the gap between optical devices and a substrate is filled with transparent underfill resin to prevent the dust. Figure 2 shows the schematic illustration of the mesa type VCSEL used in this study. The mesa part consists of active layer, distributed Bragg reflector (DBR) layers, current constriction layer, polyimide passivation, and the electrode. The current flows from the electrode through p-dbr layers into the active layer, while it is restricted at the current constriction layer. The current constriction layer is made from Al 2 O 3 (alumina). They are fabricated by selective oxidation of Al layer so that the current goes through an imperceptible portion efficiently. 2.2 Experimental and simulation methods We confirmed the reliability of VCSELs by high temperature bias (HTB) test at the conditions shown in Table 1. This condition is used for detecting and screening out early life failures of VCSELs. The damage to VCSEL is shown by the variation of the light-current (L-I) characteristic before and after HTB test. We set the pass criterion that the variation of optical output power (Pf) was less than % with 8 ma. This criterion was determined by the experiment that Pf which changed less than % after HTB test did not get worse even after hours. We investigated cross-sections of VCSELs in order to observe the variation of the internal structure. The cross-sections were prepared by adopting Ar ion milling system to reduce the mechanical damage during polishing. In addition, we performed simulation for the thermal stress analysis by ANSYS.[8] The simulation model and analysis parameters will be described later. The thermal distribution was modeled on the biased VCSEL. Since VCSELs produce heat with the bias current, the actual temperature of their active area exceeds ambient temperature. We estimated that the rise in heat is about C at the HTB test condition from the temperature dependence of the wavelength of VCSELs. 3. Results and Discussions 3.1 Mechanism investigation of cracks in VCSELs Figure 3 shows the histogram of reduction rate of Pf after HTB test when no underfill resin was used, where the broken line shows a criterion value. All the reduction rate of Pf was less than %. Figure 3 is the cross-section of the mesa part of VCSEL after HTB test. The picture on the left is the overall view of the mesa part and the picture on the right is the enlarged view of the alumina layer. There were no failures in VCSELs. On the other hand, Fig. 4 shows the reduction rate of Pf when epoxy resin was used. There were some VCSELs which showed the reduction rate more than %. The crack was observed above the alumina layer in the cross-section of VCSEL which Pf reduced more than % as shown in Fig. 4. Furthermore, there was a small crack generation even when the reduction rate was less than % as shown in Fig. 4 (c). It is clear that cracks occur inside VCSELs by the influence of epoxy resin. The reduction of Pf probably occurred due to the crack, which will cause an unusual laser oscillation. Figure 4 (c) indicates that the crack may be originated from the boundary between the alumina layer and DBR layers. The stress tends to concentrate on the boundary of materials due to coefficient of thermal expansion Light output Electrode Polyimide passivation p-dbr layer n-dbr layer Current flow Currentconstriction layer (Alumina) Active layer substrate Fig. 2 Structure of mesa-type VCSEL. Alumina layer Parameter (unit) Table 1 HTB test condition. Temperature (ºC) Current (ma) Duration (hour) typ Fig. 3 Results of HTB test of VCSELs without underfill resin. Histogram of reduction rate of Pf. Cross-sectional SEM image of mesa part of VCSEL. 64

3 Oda et al.: Development of Underfilling Method for Flip Chip Mounted VCSEL (3/7) Crack (CTE) mismatch. We analyzed the thermal stress distributions of VCSELs in HTB condition. We shall focus on the thermal stress at the boundary between alumina and DBR layers for the above reason. Figure 5 shows our simulation model, and Fig. 5 is the enlarged view of the mesa part. The left end has the rotation symmetry. We set the material of DBR layers to only. And as mentioned in section 2.2, we set the temperature of the current flow area (diagonal lines in Fig. 5) as C in this simulation model. Table 2 is the list of simulation conditions and results. Condition A is underfill-less model, and condition B is epoxy resin model. Details of condition C and D are described later. Table 3 shows analysis parameters. Figure 6 and Crack (c) Fig. 4 Results of HTB test of VCSELs using epoxy resin. Histogram of reduction rate of Pf. Cross-sectional SEM image of VCSELs with Pf reduction rate more than %. (c) Cross-sectional SEM image of VCSELs with Pf reduction rate less than %. Underfill resin Glass AuSn Fig. 5 2D simulation model. Heating area (ºC) Underfill resin Gold Polyimide Alumina Overview image of the simulation model. Enlarged view of the mesa part of VCSEL in Fig. 5. Table 2 Simulation conditions and results. The values of the thermal stress show those at the white circle parts in each thermal stress distribution. Condition Type of underfill resin Simulation Thermal stress Thermal stress model distribution ( 7 Pa) A No underfill Fig. 5 Fig B Epoxy Fig. 5 Fig C Silicone Fig. 5 Fig D Epoxy (with air cap) Fig. 11 Fig Material Young s modulus (GPa) Table 3 Analysis parameters. Poisson s ratio CTE (ppm/k) Thermal conductivity (W/m K) Alumina Glass AuSn Gold Polyimide Epoxy resin Silicone resin

4 Transactions of The Japan Institute of Electronics Packaging Vol. 6, No. 1, 13 Alumina Alumina Fig. 6 Thermal stress distributions by simulation. Underfill-less model. Epoxy resin model. show the thermal stress distributions which were derived by simulation analysis. These figures are the enlarged views of the tip of alumina layer, where the thermal stresses were concentrated. We estimated the thermal stress values at the boundaries between and alumina, white circles in each figure. They are shown in Table 2. The thermal stress of condition B was 2.2 times higher than that of condition A. From these simulation results, it was found that the thermal stress to the alumina layer is enhanced by epoxy resin. The point of stress concentration in simulation agrees very well with the point of crack generation in experiment. The brittleness of material seems to affect the failure mechanism. It is reported that yield stress σ y decreases rapidly depending on temperature.[9] Although σ y is 1.6 GPa at room temperature, it decreases to.4 GPa at HTB condition. From these facts, the failure mechanism can be explained as follows. Step 1: Thermal stress at the tip of alumina layer is enhanced by underfill resin. Step 2: σ y of DBR layers decreases greatly. Step 3: Cracks occur in DBR layers. Although the failure mechanism can be described qualitatively from the above discussion, the consistency of simulation results and experimental results has to be ensured for fully understanding of the failure mechanism. The simulation model will be reconsidered to improve the accuracy of the simulation result. 3.2 Consideration of new mounting methods In this section, we describe the mounting methods which can prevent the cracks. From the above results, the stress to the mesa part will increase as the Young s modulus of underfill resin gets higher. Therefore the thermal stress can be suppressed if underfill resin of high Young s modulus does not make contact with the mesa part. We considered two mounting methods based on this idea. The first method is to use a resin of low Young s modulus. The second method is to use a structure where air caps cover the mesa parts so that underfill resin cannot make contact Fig. 7 Results of HTB test of VCSELs using silicone resin. Histogram of reduction rate of Pf. Cross-sectional SEM image. Fig. 8 Thermal stress distributions of silicone resin model. with them. We adopted silicone resin to the first method because its Young s modulus is much smaller compared with epoxy resin as shown in Table 3. Figure 7 shows the histogram of the reduction rate of Pf after HTB test in this method, and it met the criteria. Figure 7 is the crosssectional image, and there were no failures such as cracks. The simulation was conducted at condition C in Table 2. The thermal stress distribution is shown in Fig. 8, which was almost the same as that of the underfill-less model shown in Fig. 6. The stress at the tip of alumina layer was equivalent to that of the underfill-less model as shown in Table 2. The second method is to form air caps around the mesa parts of VCSELs so that resin cannot make contact with them. Figure 9 shows the cross-section of the mounting structure of this method. The air caps make contact with the mesa parts and the light paths, and the other area is surrounded by epoxy resin. Figure and show the results of HTB test in this method, where no failures were observed. The simulation model of the air cap method is 66

5 Oda et al.: Development of Underfilling Method for Flip Chip Mounted VCSEL (5/7) Mesa part VCSELarray Air cap Epoxy resin Air cap Glass Fig. 9 Cross-sectional image of the air cap method Fig. Results of HTB test of VCSELs using epoxy resin with air caps. Histogram of reduction rate of Pf. Cross-sectional SEM image. Air cap Glass AuSn Underfill resin Fig. 11 2D simulation model of the air cap method. shown in Fig. 11. The white-painted area above the mesa part of VCSEL is the air cap where we set no materials. The thermal stress distribution derived by simulation is shown in Fig. 12, and the thermal stress value at the tip of alumina layer is shown in condition D of Table 2. Their simulation results were almost the same as those of the underfill-less model and the silicone resin model. The results of HTB test in both mounting methods were equivalent to those in the structure without underfill resin. Fig. 12 Thermal stress distributions of the air cap model. This means that the cracks can be prevented in both cases. This fact shows that the increase of the thermal stress can be suppressed by avoiding the arrangement of resin of high Young s modulus on the mesa parts of VCSELs. We regarded the protection of the light path as most important to decide the mounting structure of optical devices in optical engines. That is because we were most concerned about the loss of light. Thereby it is necessary to protect the light path from dust and moisture. Although the dust problem is dealt with by the two methods, the moisture condensation might be a problem in the air cap method. The optical output power would decrease if the moisture in the air cap is condensed. On the other hand, there are no worries about moisture condensation in silicone resin method because the light path is filled up by resin. So we thought the silicone resin method to be better, and adapted it to the mounting structure of optical devices in optical engines. The air cap method is superior in bonding strength since resin of high Young s modulus such as epoxy resin can be used. The remaining problem in this method is to find the way to prevent the loss of light due to the moisture condensation. 3.3 Reliability evaluation of optical engines We performed a series of environmental tests for optical engines which silicone resin was used. The test items, conditions, criteria and results are shown in Table 4. We assumed the pass criterion that the Pf change of VCSEL in optical engine was less than.5 db in these tests. The high temperature operation test was the most important in these tests. samples were evaluated and passed the test. In addition, temperature cycling test, damp heat storage test and damp heat powered test were also performed. All the samples passed these tests. We also evaluated high frequency characteristics of VCSELs in optical engines at 14 Gbps. Figure 13 shows the optical output waveform of the transmitter before and after high temperature operation test. The sufficient eye opening was obtained even after the test for 1, hours. And the mask margin was 67

6 Transactions of The Japan Institute of Electronics Packaging Vol. 6, No. 1, 13 Fig. 13 Comparison of optical output waveforms of optical engines at 14 Gbps before and after high temperature operating test. Before the test. The mask margin is 25%. After 1, hours. The mask margin is 27%. Table 4 Results of environmental tests for optical engines. Test item Condition Sample size Pass criteria Result High temperature operation +7ºC, 8 ma, 1,h Pass Temperature cycling -ºC/+85ºC, 5 cyc Variation of Pass optical output Damp heat storage +85ºC/+85%RH, 1, h 5 Pass power <.5 db Damp heat powered +85ºC/+85%RH, Ibias = Ith 1.2, 1, h Pass more than %. From these results, we confirmed that the optical engines using silicone resin have high reliability. 4. Conclusion We studied the thermal stress of the flip chip mounted VCSELs. It was clarified that cracks occur at the tip of alumina layer due to the thermal stress enhanced by underfill resin of high Young s modulus. We evaluated two mounting methods and confirmed that the cracks can be prevented in both cases. The first method uses silicone as a resin of low Young s modulus and the other uses a structure where the air caps cover the mesa parts of VCSELs. We believe the silicone resin method to be better because it is free from the moisture condensation in the light path. High reliability was confirmed in optical engines using silicone resin. References [1] M. A. Taubenblatt, Optical Interconnects for High- Performance Computing, J. Lightwave Technology, Vol., No. 4, pp , 12. [2] Optcom, No. 249, pp. 35, December, 9. [3] C. Kachris and I. Tomkos, A Survey on Optical Interconnects for Data Centers, IEEE Commun. Surveys Tuts., Vol. 14, No. 4, 12. [4] P. Pepeljugoski, J. Kash, F. Doany, D. Kuchta, L. Schares, C. Schow, M. Taubenblatt, B. J. Offrein, and A. Benner, Low Power and High Density Optical Interconnects for Future Supercomputers, Proc. of OFC Conference and Exhibit, OThX2,. [5] K. Tanaka, S. Ide, Y. Tsunoda, T. Shiraishi, T. Yagisawa, T. Ikeuchi, T. Yamamoto, and T. Ishihara, High-Bandwidth Optical Interconnect Technologies for Next-Generation Server Systems, IEEE Computer Society, pp. 6 13, 13. [6] D. Gwyer, P. Misselbrook, D. Philpott, C. Bailey, P. P. Conway, and K. Williams, Thermal, Mechanical and Optical Modelling of VCSEL Packaging, Proc. of Thermal and Thermomechanical Phenomena in Electronic Systems, Vol. 2, pp. 5 4, 4. [7] E. Zakel, J. Gwiasda, J. Kloeser, J. Eldring, G. Engelmann, and H. Reichl, Fluxless Flip Chip Assembly on Rigid and Flexible Polymer Substrates Using the Au-Sn Metallurgy, IEEE/CPMT International Electronics Manufacturing Technology Symposium, Vol. 1, pp , [8] ANSYS, ANSYS Japan K.K, [9] T. Suzuki, T. Tokuoka, I. Yonenaga, and H. O. K. 68

7 Oda et al.: Development of Underfilling Method for Flip Chip Mounted VCSEL (7/7) Kirchner, Inverse brittle-to-ductile transition in Gallium-Arsenide Under Hydrostatic Pressure, Scripta mater., Vol. 43, p. 645,. Takuya Oda was born in Gifu, Japan, in He received the B. S. and M. S. degrees in physics from Nagoya University, Japan in 9 and 11, respectively. In 11, he joined Optics and Electronics Laboratories, Fujikura Ltd., Chiba, Japan. He is currently engaged in developmental research on optoelectronic packaging technology. Teijiro Ori was born in Nagano, Japan, in He received the B. S. degrees in physics from Shinshu University in In 1988, he joined Oki Electric Industry, where he was engaged in developmental research on advanced packaging technology. In 6, he joined Fujikura Ltd., where he is currently engaged in research on optoelectronics. Takayuki Tanaka was born in Ishikawa, Japan, in He received the B. E. and M. E. degrees in physics from Tokyo University of Science, Japan, in 1996 and 1998, respectively. He is currently working in Fujikura Ltd., where he is engaged in development of Optical Engine and Active Optical Cables. 69