9/4/2008 GMU, ECE 680 Physical VLSI Design

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1 ECE680: Physical VLSI Design Chapter II CMOS Manufacturing Process 1

2 Dual-Well Trench-Isolated CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 p-well poly n-well SiO 2 n+ p-epi p+ p+ 2

3 Schematic Layout View V DD V DD DD M2 M4 V in V out V out2 M1 M3 3

4 Photo Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development spin, rinse, dry acid etch 4

5 CMOS Fabrication Process Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers 5

6 Define Active Area: Patterning of SiO 2 Si-substrate (a) Silicon base material Si-substrate Photoresist SiO 2 (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure UV-light Patterned optical mask Exposed resist Si-substrate Chemical or plasma etch Hardened resist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 Si-substrate (e) After etching Si-substrate Hardened resist SiO 2 SiO 2 (f) Final result after removal of resist 6

7 CMOS Process Walk Through p epi p+ p epi p+ SiN 3 4 SiO 2 (a) Base material: p+ substrate with p epi layer (b) After deposition of gate oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 7

8 CMOS Process Walk Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n well and V Tp adjust implants p (f) After p well and V Tn adjust implants 8

9 CMOS Process Walk Through poly(silicon) (g) After Poly Si deposition and etch n+ p+ (h) After n+ source/drain and P+ source/drain implants. At the same time these step also dope the Poly Si SiO 2 (i) After deposition of SiO 2 Insulator and contact hole etch

10 CMOS Process Walk Through Al (j) After deposition and patterning of first Al layer. M2 M1 M3 Al SiO 2 (k) After deposition of SiO insulator, etching of via s vias, deposition and patterning of second layer of Al. 10

11 Advanced Metallization SEM image of a real circuit whose oxide was etched 11

12 Design Rules 12

13 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) 13

14 CMOS Process Layers Layer Color Representation Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Yellow Green Green Red Blue Magenta Black Black Black 14

15 Layers in 0.25 μm CMOS process 15

16 Intra Layer Design Rules Well Active Select Same Potential 10 0 or 6 3 Different Potential 9 Polysilicon Metal1 Contact or Via 2 3 Hole Metal

17 Transistor Layout Transistor

18 Vias and Contacts 2 1 Via Metal to Active Contact 1 Metal to Poly Contact

19 Select Layer Select Substrate Well 19

20 CMOS Inverter Layout GND In V DD A A Out (a) Layout A A p-substrate n Field Oxide n + (b) Cross-Section along A-A p + 20

21 Layout Editor 21

22 Packaging Electrical: l Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap 22

23 Bonding Techniques Wire Bonding Substrate Die Pad Lead Frame 23

24 Package Types 9/4/2008 GMU, ECE 680 Physical VLSI Design 24

25 Package Parameters 25

26 Multi Chip Modules 26