IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY 1

Transcription

1 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY 1 Design, Modeling, Fabrication and Characterization of 2 5-μm Redistribution Layer Traces by Advanced Semiadditive Processes on Low-Cost Panel-Based Glass Interposers Hao Lu, Ryuta Furuya, Brett M. D. Sawyer, Chandrasekharan Nair, Fuhan Liu, Venky Sundaram, and Rao R. Tummala, Fellow, IEEE Abstract This paper presents the latest advances in extending semiadditive process (SAP) methods to 2 5 µm lines and spaces, achieved using dry film photoresists on thin glass substrates, toward meeting the routing requirements for 20-µm bump pitch interposers. High-density chip-to-chip interconnections on 2.5-D interposers are a key enabler to meet the high logic to memory bandwidth needs of next-generation electronic systems. Such 2.5-D interposers require ultrafine redistribution layer (RDL) traces with line widths and spacing below 5 µm. This paper reports on the extension of panel scale and lower cost SAPs to achieve less than 5 µm lines and spaces, based on the ultrasmooth surface and improved dimensional stability of thin glass panels. A modified low-cost SAP method with newly developed differential seed layer etching was employed to fabricate the fine line and space patterns and coplanar waveguide (CPW) transmission on thin glass panels. Fine lines down to 2-µm lines and spaces and CPW lines with signal lengths up to 5 mm and ground-to-signal gaps down to 5.5 µm at 15-µm signal widths were successfully fabricated on ultra-thin glass panels. For comparison, the same processes were also applied to a silicon wafer. The signal insertion losses of CPW lines on the glass were db/mm better at 15 GHz than those on the silicon, as confirmed by simulations as well as VNA measurements. The measured insertion loss of 5-mm long CPW lines on glass interposer was 0.7 db at 10 GHz and matched well to the simulated values. Index Terms 2.5-D interposer, glass interposer, redistribution layer (RDL), semiadditive process (SAP). I. INTRODUCTION -D INTERPOSERS integrate logic and memory 2.5devices at close proximity and achieve high bandwidths by increasing the density of chip-to-chip interconnections. The 2.5-D architecture has become a compelling alternative to 3-D IC stacking for the scaling of Manuscript received December 29, 2015; revised March 26, 2016; accepted April 3, Recommended for publication by Associate Editor B. Dang upon evaluation of reviewers comments. The authors are with the Georgia Institute of Technology, Atlanta, GA USA ( hlv6@gatech.edu; rfuruya3@mail.gatech.edu; bsawyer@gatech.edu; cnair3@gatech.edu; fuhan.liu@ece.gatech.edu; vs24@mail.gatech.edu; rao.tummala@ece.gatech.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCPMT smart mobile and cloud computing systems. Traditional 2-D packaging of individual devices and connecting them at board level cannot achieve high bandwidths due to the limited pitch scaling of board-level interconnections. The current approaches for high-density 2.5-D interposers are based on either incrementally extending organic substrates or silicon carriers with through-silicon vias (TSVs), which utilize back-end of line (BEOL) tools and processes to form multiple redistribution layers (RDLs) at ultrafine pitch. Organic substrates are limited in scaling to fine pitch by the large via capture pads due to higher dimensional instability and also by lithographic accuracy due to their nonplanar and rough surface. Recent advances in thin-film wiring processes have pushed the limits of SAP processes on organic interposers to less than 10 μm lines and spaces. Kyocera has demonstrated 6-μm lines and spaces wiring on low coefficient of thermal expansion (CTE) organic substrates at a 50-μm bump pitch [1]. Organic substrates, however, are ultimately limited by their low modulus and high warpage that decreases chip-level interconnect reliability at decreased bump pitch. To achieve higher wiring density, silicon interposers have been developed. Compared with organic substrates, silicon has excellent dimensional and thermal stability, as well as low surface roughness for submicrometer wiring. Xilinx used a 65-nm node BEOL processes to demonstrate the first 2.5-D silicon interposers with a 45-μm interconnection bump pitch [2], [3]. Shinko has developed a thin-film process technology using liquid dielectrics, sputtered metal layer, and chemical mechanical polish (CMP) processes for fine copper wiring on silicon interposers, to achieve 1.6-μm pitch Cu traces using the SAP method [4]. Shinko also applied silicon wafer processes such as chemical mechanical polishing and thin film wiring formation to achieve 2-μm lines and spaces on thick organic laminate substrates [5]. The main challenges associated with such wafer-based interposers are the high cost due to small wafer size ( mm) and RDL fabrication costs. Silicon interposers also suffer from high electrical signal loss due to the lower resistivity of silicon. Panel-based glass interposers have been demonstrated as a lower cost and higher performance alternative to address IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 2 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY Fig. 1. Cross section of a typical 2.5-D glass interposer (not drawn to scale). TABLE I COMPARISON OF INTERPOSER OPTIONS the aforementioned challenges with organic and silicon interposers [6], [7]. The schematic drawing of a typical 2.5-D glass interposer is shown in Fig. 1. Glass combines the material advantages of silicon and organic. The high modulus and tailorable CTE of glass increases its dimensional stability comparable with those of organic cores. Furthermore, its high coplanarity and low surface roughness enable fine pitch RDL trace formation. The high-resistivity of glass improves electrical performance, while the scalability to large panel processing offers potentially lower cost compared with silicon wafers [6] [8]. Table I summarizes the comparison of 2.5-D interposer options by the RDL technology and costs to achieve die-to-die interconnect density suitable for 2.5-D integration. Electrical modeling, design, and fabrication of ultrathin glass interposers with fine pitch through-package vias (TPVs) were successfully demonstrated [6] [9], showing the superior electrical performance of glass over silicon interposers, especially for the TPVs and RF modules. There are two primary approaches to forming ultrafine RDL lines and spaces. The first approach is the semiadditive process (SAP), which uses a thin metal seed layer on the surface of the dielectric layer, followed by lithographic patterning of photoresists and electroplating of copper traces through the resist pattern, and concludes with the removal of the photoresist and etching of the metal seed layer. This is the main process flow used for organic substrates and interposers, and faces scaling challenges in the lithography and seed layer etching steps. The second approach is a damascene process, which forms trench structures etched into the dielectric layer, followed by metal filling of the trenches, and finally chemical mechanical planarization (CMP) to polish the surface and remove the plated copper overburden. This approach has also been adapted to organic substrates using the Via 2 method [10]. Although this approach is effective in achieving feature sizes of less than 5 μm lines and spaces for 2.5-D interposers, it suffers from high cost and complexity. This paper addresses the fundamental challenges of SAP processes and demonstrates the extension of advanced SAP processes for less than 5 μm redistribution layer (RDL) lines and spaces on thin glass interposers. The electrical performance of glass interposer RDL was established by the electrical modeling and design of coplanar waveguide (CPW) transmission lines to achieve a 50- characteristic impedance, and insertion loss simulations for these transmission lines were carried out. An improved low-cost SAP with novel differential seed layer etching was employed to fabricate the fine line and space patterns and CPW transmission on thin glass panels [11]. A two-port vector network analyzer (VNA) was used to measure the fabricated sample for the validation of finite-element method (FEM) simulation results up to 15 GHz. This paper is organized as follows. Section II describes the SAP method that has been modified and optimized for fine line fabrication on glass. Section III describes the simulation of CPW transmission lines on the glass interposer using HFSS simulation software. The CPW lines on a silicon interposer with similar configurations were simulated and compared with a glass interposer. Section IV analyzes the high frequency response of the fabricated CPW lines on the glass interposer and on the silicon interposer for comparison. Section V concludes this paper. II. GLASS INTERPOSER FABRICATION A. Glass Substrate Preparation Ultra-thin glass panels are brittle and can be broken without an optimized handling procedure during the fabrication process, thus decreasing the yield. The authors have previously reported on an innovative approach for thin glass handling by using polymer buildup layer on both sides of thin glass panels [7]. The laminated polymer layer acts as a stress buffer between the copper metal layer and glass core, enhancing glass panel stiffness for better handling during fabrication. Furthermore, this polymer layer has good adhesion strength to both the glass surface and copper layer with proper surface treatments. The applied polymer material is under development and is compatible with existing electroless copper seed layer plating. The advantage of this polymer is its smooth surface, which enables higher photolithography resolution than a traditional rough polymer. Before polymer lamination, a silane surface treatment process was applied to the glass panel to increase adhesion between the polymer and glass, preventing delamination during subsequent wet processes and enhancing the interposer reliability. The polymer lamination was proceeded in a vacuum laminator, followed by a hot-press process to enhance the polymer surface planarity. Then the polymer was thermally cured in an oven for 1 h at 180 C. The copper seed layer on the polymer for SAP was formed by electroless plating, which is a low cost and low temperature wet process compared with PVD, and scalable to large panels and double side processing. For comparison of the electric performance of RDL on glass to silicon, the same polymer dielectric was laminated on a single-crystalline silicon wafer and similar SAP conditions were used to form RDL on glass and silicon substrates. B. High-Resolution Lithography Photolithography is the commonly used process method to fabricate ultrasmall features such as transistors and fine

3 LU et al.: DESIGN, MODELING, FABRICATION, AND CHARACTERIZATION OF 2 5-μm RDL TRACES 3 Fig. 2. High-resolution lithography process flow chart. Fig. 3. SEM image of patterned DFR trenches from the 2-μm line and space to the 5-μm line and space. line wiring on transistor wafers and on interposers and package substrates. Most of the current package substrate processes utilize I-line UV lithography in large field size exposure mode or in stepper mode for higher resolution but lower throughput. The resolution of the lithography process is one of the key aspects that limit the minimum feature size of the SAP. This resolution is limited by two types of factors: 1) photoresist materials, the adhesion strength of the photoresist to the substrate, and the lithography tools, and 2) substrate properties such as the planarity and roughness of the substrate core. A rough and nonplanar surface will negatively impact the lithography resolution. Organic substrates have larger thickness variation and a rougher surface compared with glass substrates, due to the glass fabric woven inside the organic core. Therefore, lithography on glass is expected to have better yields than on organic substrates at 2 5-μm feature sizes for the same lithography process conditions. Two forms of photoresist are commonly used for lithography, namely, liquid photoresists, and dry film resists (DFR). In general, DFRs have lower cost and is better suited for double-side processing on large panels than liquid photoresists. High-resolution DFRs with thickness of 7, 10, and 15 μm provided by Hitachi Chemical [12] were used in this study. To enhance the adhesion between DFR and the copper seed layer surface, an adhesion promoter treatment called Novalink from Atotech was applied. This surface treatment process has been proved to significantly increase the lithography process yield at the 5-μm feature size [11], and enables higher lithography resolution below 5 μm. A glass photomask consisting of comb structures, escape routing structures, and CPW lines was applied in the lithography process. The lithography process flow is summarized in Fig. 2. Fine line patterns with a feature size of 2 5 μm were achieved with the appropriate lithography tool, high-resolution DFR, and adhesion promoter treatment. Ushio s new advanced projection lithography tool Ushio UX [13] was set up at Georgia Tech PRC. This machine along with a high-resolution DFR and proper surface treatment can support the lithography resolution down to 2 μm. The DFR applied in this experiment is 7 μm and the exposure dose is 180 mj/cm 2. The development was done in a spray developing tool with spray nozzles located on both sides of the conveyer. The development chemistry is the sodium carbonate solution, and the conveyer speed for DFR development was set to 40 inch/min. The SEM image of developed DFR structures with the 2-μm line and space pattern is shown in Fig. 3. Fig. 3 also shows the limitation of the lithography process shown in Fig. 2, as the 1.5 μm trench structure did not yield. For 7-μm-thick DFR, the aspect ratio of 1.5-μm line and space pattern is 4.67, and the stiffness of this DFR is not high enough to support such a high aspect ratio structure. To further improve the lithography resolution, the thickness of the DFR needs to be reduced or the stiffness needs to be increased. C. Fine Line Metallization The copper RDL structures for glass interposer were metallized by electrolytic plating. The samples were subjected to a 10-min plasma etching by CF4 and O2 gases with a flow ratio of 1:4, removing any DFR residue in the trench and improving the wettability of copper surface for better plating quality. The plating tank chemistry is from Atotech, called Cupracid TP [14]. It contains Electropure copper sulfate solution, sulfuric acid, sodium chloride, Cupracid TP Leveller, Cupracid Brightener, and Cupracid Starter. To maintain a good copper thickness uniformity and smooth surface, the ratio of inorganic and organic additives in the plating tank needs to be controlled at an optimal value which Atotech recommended. The copper layer thickness was determined by the electrolytic plating time and current density, which can be calculated theoretically using the following equation: T = M w It 2FAρ where T is the copper deposit thickness in centimeters, Mw is the copper moler mass ( g/mol), I is the plating current (A), t is the deposit time (s), F is the Faraday constant ( c/mol), A is the area of the deposit in cm 2,andρ is the copper density (8.96 g/cm 3 ). The current

4 4 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY Fig. 4. Standard immersion seed layer wet etching. Etching speed independent of direction and copper type. Fig. 6. Spray etching with differential etchants. Etching speed dependent on direction and copper type. Fig. 5. Standard spray seed layer wet etching. Etching speed dependent on direction. applied for fine line metallization was 1.5 or A/cm 2, which is I/A in the above equation. It is worth noting that in practice, the deposited copper thickness is around 75% 80% of the theoretical value or even lower. A stripping solvent was used to remove the DFR following the electrolytic copper plating process. The copper seed layer etching was the last step to obtain the designed one metal layer RDL patterns. This critical process determines the limitation and the yield of the SAP method for the fine line RDL. The standard immersion wet etching process is isotropic, which is not ideal for the fine line SAP, as depicted in Fig. 4. For a single line structure, the copper trace side wall and top are etched at the same rate as the seed layer, resulting in narrower and lower line profiles as well as undercut. In practice, particularly for 2.5-D interposers, high-density multiline structures are required. For line and space patterns below 8 μm, the ability of the etching solution to penetrate the narrow and high aspect ratio trenches between copper traces becomes a challenging aspect. As a result, the etching speed of the copper traces is faster than the seed layer, causing over etch and undercut of copper traces. This leads to trapezoidal shaped lines, rough copper surface, and even delamination of ultrafine copper traces. Therefore, this etching method is suitable for large copper patterns, but not for fine line interposer fabrication. A seed layer etching process with adequate selectivity is required to fabricate 2 μm features and enable line densities required for 2.5-D integration. A spray etching method increases the selectivity of etching direction, causing higher vertical etching speed than lateral etching speed (Fig. 5). Similar to the immersion seed layer etching process, the copper surface is attacked by the etchant, resulting in a Fig. 7. Cross-sectional image of the 5 μm line and space pattern after immerge seed layer etching (top) and differential etching (bottom). rough copper surface. To further improve the anisotropy of the seed layer etching process, differential etchant chemistries have been developed by Atotech called CupraEtch DE [15]. Such chemistries have special additives that passivate the electroplated copper sidewall during etching, and also create a differential etch rate with the copper seed layer etching at twice the rate of the electrolytic plated copper, driven by the different grain structures. This etchant also yields smoother copper surfaces after seed layer removal. By combining the spray etching method with the differential etchant, a novel high selectivity etching approach was developed for fine line RDL fabrication as shown in Fig. 6. All three different etching methods were tested and compared. Fig. 7 shows the 5 μm line and space pattern after immersion seed layer etching and Atotech differential etching. The copper traces were badly deformed after immersion seed layer etching. Using differential etching, however, the line shape integrity was improved. Fig. 8 shows the comparison between the two copper etchants. The copper surface became rougher and matte after applying a standard copper etchant, but the differential etchant was capable of yielding a shiny and smooth copper surface due to the increased etched selectivity between electroless and electrolytic plated copper. For the glass interposer fabrication, the differential etch method was selected and optimized to obtain high quality RDL traces with improved yield. Fig. 9 shows the escape routing test pattern with 5 μm line and space on glass interposerbefore seed layer etching and after DFR strip, and Fig. 10 shows the same structure after differential seed layer etching. No seed layer residue is observed from the image, and the etching process did not deform or alter the line shape significantly. Following SAP, open/short tests of this escape routing pattern confirmed that the improved seed layer etch process resulted

5 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. LU et al.: DESIGN, MODELING, FABRICATION, AND CHARACTERIZATION OF 2 5-μm RDL TRACES 5 Fig. 8. CPW transmission line on the glass interposer etched by standard spray etch (top) and differential etch (bottom). Fig. 10. Optical microscope and SEM image of the 5-μm line and space escape routing test patterns after copper seed layer etching. Fig. 9. Optical microscope and SEM image of the 5-μm line and space escape routing test patterns before copper seed layer etching. in no seed layer residues. Test structures with 2 μm line and space escape routing patterns at 40 μm pad pitch were also fabricated on glass substrates using the same process, as shown in Fig. 11. Optical inspection of this structure revealed approximately 0.5 μm side wall etch, resulting in 1 μm line width reduction. This demonstrates the limitation of etch selectivity of the improved SAP process at 2 μm line and space and must be considered during interposer design to improve process yield. The actual line and space for 2 μm designed pattern was 0.8 μm line and 3.2 μm space. (Fig. 11) The cause of the side wall is discussed in the following paragraph. Optimizing electroless copper plating and seed layer etch conditions can improve fine line yield using the proposed Fig. 11. SEM image of the 3-μm line and space (top) and the 2-μm line and space (bottom) escape routing patterns at a 40-μm pad pitch. Fig. 12. AFM image of dielectric polymer surface before (left) and after (right) desmear process. SAP method. The copper seed layer was electroless plated on the polymer surface. Strong adhesion is required to ensure that the fine copper traces do not delaminate from the polymer. Therefore, a desmear process was applied on the polymer

6 6 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY Fig. 13. Copper traces side wall etch due to roughened polymer surface. surface before electroless copper plating. This process etches the polymer surface, increasing the surface roughness. Thus, the copper seed layer can be anchored on the polymer surface with strong mechanical adhesion and electrolytic plated fine copper traces do not delaminate after seed layer etch process. The surface roughness of polymer before and after desmear process is shown in Fig. 12. The increased R z,however,is critical for the copper seed layer etch process. The copper seed on larger R z surface has stronger adhesion but suffers from a relatively lower copper etch rate. The seed layer etch on the roughened polymer surface is shown in Fig. 13. The initial seed layer etch rate is fast and independent of the polymer roughness. However, it is difficult to fully etch the copper seed layer residue that is embedded in the rough polymer subsurface, thus requiring extended etching times. This causes a decrease in the overall seed layer etch rate and increases the amount of copper trace side wall lateral etch, resulting in lower yield of the fine copper traces. Therefore, proper optimization of copper to polymer adhesion using desmear and mask design compensation are needed to improve fine line yield. Fig. 14. CPW on glass interposer, CPW on silicon with polymer dielectric, and CPW on silicon interposer with silicon dioxide as insulator. III. ELECTRICAL SIMULATION OF RDL TRACES FOR GLASS AND SILICON INTERPOSER This section describes the electrical modeling of CPW test structures as RDL traces for glass interposers and silicon interposer for comparison. For minimum insertion loss, the transmission lines were designed to achieve a 50- characteristic impedance. Ansoft HFSS, a 3-D FEM solver for electromagnetic structures, was used to simulate the transmission lines on glass and silicon interposers. CPW transmission lines require only one metal layer, reducing fabrication complexity by not including vias. Furthermore, the impedance of a CPW line can be matched to 50 with the dielectric layer of any thickness. The crosssections of one CPW line on glass interposer and silicon interposer for comparison are shown in Fig. 14. Ideally, the dielectric layer thickness is infinite. In practice, the dielectric should be thick enough such that the electromagnetic field is insignificant through the interposer. A polymer, which has smooth surface to enable a fine line SAP, was applied as the dielectric material. For performance comparison between glass and silicon, the polymer dielectric material and thickness were maintained the same, while the core material Fig. 15. CPW model with lumped ports in HFSS (top) and simulated insertion loss on glass interposer and silicon interposer (bottom). The effective length, signal line width, and gap of CPW are 5 mm, 10.5 μm, and 5.7 μm, respectively, and the dielectric layer is 17.5-μm polymer and 2-μm silicon dioxide. was varied. Depending on the signal-ground gap and the dielectric thickness, the electromagnetic fields may penetrate through the top dielectric layer to the core material of the interposer. Silicon is an electrically lossy material compared with glass. As a result, the CPW performance is dependent on the electrical properties of the polymer dielectric and the core. The simulated insertion losses of CPW on glass and silicon interposers are shown in Fig. 15. The effective length, signal line width, and gap of CPW was 5 mm, 10.5 μm, and 5.7 μm, respectively. The dielectric material was a 17.5-μm-thick polymer with a dielectric constant of 3 and a loss tangent of 0.005, for both glass and silicon

7 LU et al.: DESIGN, MODELING, FABRICATION, AND CHARACTERIZATION OF 2 5-μm RDL TRACES 7 Fig. 16. Cross-sectional image of VNA measured CPW line (top) and the cross-sectional image of the modified CPW model in HFSS with wave ports (bottom). Fig. 17. Simulated and measured insertion losses of CPW on glass interposer with tapered line width and gap, 5 mm in length. substrate, and 2-μm-thick silicon dioxide for the traditional silicon interposer. The dielectric constant of the glass substrate was 5.3, and the silicon substrate had a dielectric constant of 11.9, with an electrical conductivity of 10 S/m. To match the CPW characteristic impedance to 50, the thickness of the copper was adjusted for different configurations. The CPW on the traditional silicon interposer is thinner than on glass interposer because of the high dielectric constant of silicon. The simulation results showed that the insertion loss of CPW traces on the polymer laminated silicon interposer was higher than on glass interposer, and the thinner CPW on the traditional silicon interposer has much higher insertion loss than the other two. This is consistent with the fact that silicon has higher electrical loss than glass. The higher conductivity of silicon causes the observed higher loss of the electromagnetic wave energy in the simulation results. IV. ELECTRICAL CHARACTERIZATION OF RDL TRACES ON GLASS AND SILICON INTERPOSER In this section, the model-to-hardware correlation of CPW on glass interposer is demonstrated. The 17.5-μm polymer dielectric is vacuum laminated on both sides of the glass core. Using the improved SAP described above, a 9-μm copper metal layer was fabricated. The measured line width and gap of CPW are slightly different than designed due to overexposure in lithography and limitations in seed layer etch selectivity. A VNA with GSG probe was utilized for the S-parameter CPW measurement. The cross-sectional image of measured CPW line is shown in Fig. 16. A 5-μm-thick nickel layer was deposited on the CPW surface to protect the copper trace during microsection polishing. According to the fabricated transmission line dimensions, the CPW model in HFSS was modified to reflect the inclined copper trace sidewall (Fig. 16). The measured and simulated insertion losses of the CPW on glass with the line width of 13.6 μm on top, 15.1 μm on bottom, 6.6-μm gap on top, 5.5-μm gap on bottom, and 5-mm length are shown in Fig. 17. The two results correlate well with only around 0.1 db differential, hereby validates performance metrics obtained using the 3-D EM HFSS model. The main Fig. 18. Insertion loss of CPW on glass and on silicon, with a 13.6-μm line width, a 6.6-μm gap, and a 5-mm length. reason for this discrepancy is the copper transmission line surface roughness, which is present in the real world but not effectively captured in the HFSS model. At high frequency, the electrical current tends to flow near the surface of the conductor. The surface roughness increases the resistance of high-frequency signal. Therefore, the measured insertion loss is higher than the simulation result. To compare the glass interposer performance with silicon, the CPW transmission lines with same designs and build-up layers were also fabricated on a silicon wafer with polymer dielectric instead of thin silicon dioxide and measured with the VNA. The insertion loss of CPW on silicon is close to that on glass interposer at low frequency, and the discrepancy becomes larger at high frequency, as shown in Fig. 18. The silicon interposer requires thicker dielectric layer than the glass interposer to achieve same insertion loss, which leads to larger total thickness of silicon interposer. Therefore, glass, as an interposer material, is a superior alternative to silicon to improve electrical performance. V. CONCLUSION This paper reported the design and fabrication of the RDL for a thin glass interposer. The advanced SAP method was modified to reduce the cost and improve the minimum feature size. High-resolution lithography using DFR combined

8 8 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY with differential copper seed layer etching advances the limit of SAP method to 2 μm while maintaining low cost. Assisted by a novel differential seed layer etching method, this advanced SAP for panel-based ultrathin glass interposer fabrication has a great potential for low-cost applications that require high I/O density comparable to conventional silicon interposers with wafer-level process. The simulated CPW line frequency response in HFSS shows that the electrical performance of the glass interposer has lower insertion loss compared with that of the silicon interposer. This was validated by the VNA measurement up to 20 GHz. Further improvements to the SAP process on glass as well as multilayer RDL processes with ultrafine wiring for 2.5-D glass interposer packages will be reported in the future. REFERENCES [1] M. Ishida, APX (advanced package X) Advanced organic technology for 2.5D interposer, in Proc. CPMT Seminar, Latest Adv. Organic Interposers (ECTC), Lake Buena Vista, FL, USA, May [Online]. Available: %20M.%20Ishida,%20Kyocera%20WEB%20UP.pdf [2] P. Dorsey, Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency, Xilinx, San Jose, CA, USA, White Paper Virtex-7 FPGAs, WP380 (v1.2), Dec [3] B. Banijamali, S. Ramalingam, H. Liu, and M. Kim, Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps, in Proc. 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, pp [4] M. Sunohara, A. Shiraishi, Y. Taguchi, K. Murayama, M. Higashi, and M. Shimizu, Development of silicon module with TSVs and global wiring (L/S = 0.8/0.8 μm), in Proc. 59th Electron. Compon. Technol. Conf., May 2009, pp [5] K. Oi et al., Development of new 2.5D package with novel integrated organic interposer substrate with ultra-fine wiring and high density bumps, in Proc. IEEE 64th Electron. Compon. Technol. Conf., May 2014, pp [6] V. Sukumaran et al., Through-package-via formation and metallization of glass interposers, in Proc. 61st Electron. Compon. Technol. Conf. (ECTC), Jun. 2011, pp [7] V. Sukumaran, T. Bandyopadhyay, V. Sundaram, and R. Tummala, Low-cost thin glass interposers as a superior alternative to silicon and organic interposers for packaging of 3-D ICs, IEEE Trans. Compon., Packag., Manuf. Technol., vol. 2, no. 9, pp , Sep [8] V. Sridharan et al., Design and fabrication of bandpass filters in glass interposer with through-package-vias (TPV), in Proc. 60th Electron. Compon. Technol. Conf. (ECTC), Jun. 2010, pp [9] V. Sukumaran et al., Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias, in Proc. IEEE 61st Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2011, pp [10] Atotech Inc. Via 2 Technology Copper Trench Filling for Ultra Fine Lines. accessed on [Online]. Available: com/products/electronics/panel-pattern-plating/horizontal-systems/via2- technology.html [11] H. Lu et al., Demonstration of 3 5 μm RDL line lithography on panel-based glass interposers, in Proc. IEEE 64th Electron. Compon. Technol. Conf., May 2014, pp [12] Hitachi Chemical Co., Ltd. (2013). RY Series for PKG Board. [Online]. Available: [13] USHIO Inc. (2013). Lighting Edge Technologies. [Online]. Available: [14] Atotech Inc. (2004). Cupracid TP, accessed on [Online]. Available: [15] N. Lützow, G. Schmidt, Ö. Erdogan, and W. Wong, CupraEtch DE Recyclable anisotropic etchant for advanced flip chip manufacturing, in Proc. 7th Int. Microsyst., Packag., Assembly Circuits Technol. Conf. (IMPACT), 2012, pp [Online]. Available: anisotropic_etchant_for_advanced_flip_chip_manufacturing.pdf Hao Lu received the B.S. and M.S. degrees in mechanical engineering from the Huazhong University of Science and Technology, Wuhan, China. He is currently pursuing the Ph.D. degree with the School of Electrical and Computer Engineering, Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA. He is also a Graduate Research Assistant with the 3-D Systems Packaging Research Center, Georgia Tech. His current research interests include the multilayer redistribution layer design, fabrication, and signal integrity analysis for cost driven panel-based glass interposer. systems package. Ryuta Furuya received the B.S. and M.S. degrees in physics from the University of Tokyo, Tokyo, Japan, in 2010 and 2012, respectively. He joined USHIO Inc., Tokyo, Japan, in He is currently with the 3-D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA, as a Visiting Engineer. His recent research is the development of high density panel-based 2.5-D glass interposer and photonic package. His current research interests include functional device, energy harvesting, and microelectromechanical Brett M. D. Sawyer received the B.S. degree in electrical engineering from Old Dominion University, Norfolk, VA, USA, in 2011, and the M.S. degree in electrical engineering from the Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA, in 2014, where he is currently pursuing the Ph.D. degree in electrical engineering. He joined the 3-D Systems Packaging Research Center, Georgia Tech, in His current research interests include the design and demonstration of a 2.5-D glass interposer package to achieve Tb/s die-to-die and 400 Gb/s off-interposer bandwidths. Chandrasekharan Nair received the bachelor s degree in polymer engineering and technology with a minor in chemical engineering from the Institute of Chemical Technology, Mumbai, India, in He is currently pursuing the Ph.D. degree in materials science and engineering with the 3-D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA, under the guidance of Prof. R. Tummala. His recent research is the reliability evaluation of novel polymer dielectric materials and processes to build next generation redistribution layer for panel scale interposers/high density packages as a Graduate Research Assistant in the Low Cost Glass Interposer Program. His current research interests include polymer-metal interfaces, package substrate reliability studies, and polymer characterization.

9 LU et al.: DESIGN, MODELING, FABRICATION, AND CHARACTERIZATION OF 2 5-μm RDL TRACES 9 Fuhan Liu Graduated from the Department of Physics, Fudan University, Shanghai, China. He is currently a Program Manager of 3-D Glass Photonics and Next Generation Redistribution Layer (RDL) with the 3-D Systems Packaging Research Center, Georgia Institute of Technology, Atlanta, GA, USA. He is focused on research and development of system-on-package, integration of high density and high speed optoelectronics, single mode/multimode fiber to waveguide and photonic IC integration, ultrahigh-density RDL with extended semi-additive process, and embedded trench approaches. He has developed a novel via-in-trench RDL configuration with 2/2/2/20 μm (line/space/via/pitch) on thin glass panel for μm ultrafine pitch 2.5-D interposers and fan-out packages. He developed and demonstrated 1-2 layer ultralow cost thin organic package for I/Os >500 flip chip, chip-last embedded ICs in high performance organic package for GHz multiband applications, GB high speed optical interconnect integration systems, and multispectral imaging CMOS imager with mosaic filter for bioapplication. He has been involved in the packaging research for more than 20 years. He has authored or co-authored over 100 papers. Venky Sundaram received the B.S. degree from IIT Mumbai, Mumbai, India, and the M.S. and Ph.D. degrees in materials science and engineering from the Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA. He is currently the Director of Research and Industry Relations with the 3-D Systems Packaging Research Center, Georgia Tech. He is the Program Director of the Low-Cost Interposer and Packages Industry Consortium with over 25 active global industry members. He is a Globally Recognized Expert in packaging technology, and the Co-Founder of Jacket Micro Devices, Livonia, MI, USA, and a RF/wireless startup acquired by AVX Corporation, Fountain Inn, SC, USA. He has authored over 100 publications and holds 15 patents. His current research interests include system-on-package technology, 3-D packaging and integration, ultrahigh-density interposers, embedded components, and systems integration research. Dr. Sundaram has received several best paper awards. He is the Co-Chairman of the IEEE Components, Packaging and Manufacturing Technology Technical Committee on High Density Substrates and the Director of Education Programs with the Executive Council of the International Microelectronics and Packaging Society. Rao R. Tummala (F 93) received the B.S. degree from the Indian Institute of Science (IIS), Bangalore, India, and the Ph.D. degree from the University of Illinois at Urbana Champaign, Champaign, IL, USA. He was an IBM Fellow, pioneering the first plasma display and multichip electronics for mainframes and servers. He is currently a Distinguished and Endowed Chair Professor and the Founding Director of the National Science Foundation s Engineering Research Center with the Georgia Institute of Technology (Georgia Tech), Atlanta, GA, USA, pioneering Moore s law for system integration. He has authored over 500 technical papers, the first modern book entitled Microelectronics Packaging Handbook, the first undergrad textbook entitled Fundamentals of Microsystems Packaging, and the first book introducing the system-on-package technology, and holds 74 patents and inventions. Prof. Tummala is a member of the National Academy of Engineering. He has received many industry, academic, and professional society awards, including the Industry Week s Award for improving the U.S. competitiveness, the IEEE David Sarnoff and Dan Hughes Awards from the International Microelectronics and Packaging Society, the Engineering Materials Award from ASM, and the Total Excellence in Manufacturing Award from the Society of Manufacturing Engineers. He was a recipient of the Distinguished Alumni Awards from the University of Illinois at Urbana Champaign, IIS, and Georgia Tech, the Technovisionary Award from the Indian Semiconductor Association, and the IEEE Field Award for his contributions in electronics systems integration and cross-disciplinary education in He was the President of the IEEE Components, Packaging and Manufacturing Technology and the International Microelectronics and Packaging Society.