thermal oxides 2nd poly SiO2 p p -substrate (lightly doped) p-substrate 1st poly MOS Capacitor

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1 N.CHEUNG EE143, S 2009 Homework Assignment # 10 (Due Aril 13, 8am) Reading Assignment 1)EE143 Lecture Notes on Process Integration 2) Jaeger, on CMOS integration OPTIONAL Reading : EE143 Reader, John Chen, Chater 5, CMOS Process Technology. This Chater describes rocessing of more advanced MOS structures. In this homework assignment, we will ractice designing rocess flows based on lanar technology. You have to draw cross-sections of the devices at major rocessing stes. Problem 1 Double Poly DRAM Design a rocess flow for the following double oly-si NMOS dynamic random access memory (DRAM) element. Note that 1 st oly and 2 nd oly are searated a very thin layer of thermal oxide. A standard NMOS rocess is used with LOCOS to form the field oxide. Enter the rocess descrition under the first column and a sketch of the cross-section after critical rocess stes under the Second column. CVD 2nd oly Al thermal oxides 1st oly -substrate (lightly doed) (Field Oxide) Channel sto Al (wordline) 2nd oly -substrate 1st oly Si (bitline) NMOS FET MOS Caacitor Problem 2 Generic NMOS Process Flow Draw the cross-sections of the NMOS device along the lines (i) A-A and (ii) B-B after (a) The silicon nitride CVD deosition ste (b) The field oxide growth ste (c) RIE oly-si gate ste (d) RIE of intermediate oxide and thermal oxide ste (e) Hydrogen annealing ste. B A A B

2 Problem 2 rocess flow descrition Substrate Boron doed (100)Si Resistivity= 20 W-cm Thermal Oxidation ~100Å ad oxide CVD Si 3 N 4 ~ 0.1 um Pattern Field Oxide Regions RIE removal of Nitride and ad oxide Channel Sto Imlant: 3x10 12 B/cm 2 60keV to grow 0.45um oxide Wet Etch Nitrdie and ad oxide Ion Imlant for Threshold Voltage control 8x10 11 B/cm 2 35keV To grow 250Å gate oxide LPCVD ~ 0.35um Doe to with Phoshorus Diffusion source Gate attern RIE gate Source /Drain Imlantation ~ As/cm 2 80keV Grow ~0.1um oxide on oly-si And source/drian LPCVD ~0.35um Contact Window attern RIE removal of CVD oxide and thermal oxide Sutter Deosit Al metal ~0.7um Al interconnect attern RIE etch of Al metallization Sintering at ~400 o C in H2 ambient to imrove contact resistance and to reduce oxide interface charge

3 Problem 3 Self-aligned Al Gate MOSFET After aluminum deosition, the rocessing Al (level 1) Al (level 2) temerature cannot higher than 650 C because the aluminum will melt. For examle, the 900 C annealing CVD ste required to activate the imlanted doants for source/drain imlants cannot be erformed after aluminum deosition. With this constraint in mind, design a rocess flow for this self-aligned imlanted - substrate source/drain MOSFET using Al as the gate material [shown as Al(level 1) in figure]. A schematic cross-section of the device is illustrated below. Self-aligned Al-Gate MOSFET Describe the rocess flow and show the cross-sections at major rocessing stes. [Hint: Use a high-temerature comatible material to form a dummy gate. After S/D formation, selectively remove the dummy gate and relace it with Al ] Problem 4 Pin Joint Process Sequence (a) Using surface micromachining, a in joint can be fabricated with the cross-section and to view shown below. The in joint has a stationary in (the anchor) on the wafer surface and a free sinning rotor which slides on to of the wafer surface. Note that the to of the stationary in has a dimension larger than that of the rotor inner hole to kee the rotor in lace. 2 nd level oly-si stationary in 1st level oly-si (the rotor) slides on the Si substrate surface and can rotate freely around the stationary in (2 nd level oly-si ) s t a t i o n a r y f r e e ( 2 n d o l y ) s i n n i n g ( 1 s t o l y ) Si substrate You find the following brief descrition of the rocess flow in the notebook of a former EE143 student. Sketch the cross-sections and to views at the highlighted rocessing stes (marked by bold font). Process Descrition Cross-Sections To Views Starting Material Pure Si wafer Si substrate Deosit 1st level Phoshosilicate glass (PSG) by CVD Deosit of 1 st level by CVD Pattern 1st level oly-si and PSG-1(Mask #1) Deosit 2 nd level PSG Pattern oening for stationary in (Mask #2) Deosit 2 nd level oly-si by CVD Pattern 2 nd level oly-si (Mask#3) Selectively etch away 1 st level and 2 nd level PSG using HF acid. (b) The following qualitative questions are related to the rocess flow in art (a). No artial credit will be given without an exlanation or discussion.

4 (I ) To reduce the inertia of the rotor, some former EE143 students roosed to relace the 1 st level oly-si with hotoresis as the rotor material. Will this relacement be comatible with the rocess sequence? (II) Instead of deositing the 2 nd level PSG by CVD, can we use thermal oxidation to form the 2 nd level oxide? Discuss why or why not? (III) The rocess flow in art (a) uses two searate oly-si deosition. Can we fabricate the device with only one layer of oly-si? Exlain why or why not? Problem 5 Sub-50nm MOSFET Process Flow Otical lithograhy can only define features larger than 50nm. To fabricate MOSFETs with channel length less than 50nm, the following rocess descrition is found in a ublication: (1) Fabricate oxide trench for device isolation (2) Form silicon nitride on ad-oxide films. (3) Pattern nitride/ad-oxide to smallest feature by otical lithograhy (4) S/D imlant (5) Angle imlant (tilted ~ ±45 degrees ) to form ockets. (6) Form TiSi 2 on S/D regions (7) Deosit CVD oxide and lanarize surface by CMP (8) Selectively remove nitride dummy gate (9) Deosit CVD oxide and form oxide sacer by RIE (10) Grow gate oxide by thermal oxidation (11) gate deosition by CVD (12) Pattern gate The final device cross-section is illustrated below. Oxide sacer Smallest feature rintable by otical lithograhy oly-si gate Normal S/D imlant CVD oxide CVD oxide Angled Thermal Imlant gate oxide ocket Let us start with a structure with oxide trench isolation already fabricated. Continue the rocess descrition with your interretation of the rocess flow. Show the cross-sections at major rocessing stes. Process Descrition Cross-section

5 1) Starting structure ( oxide trench isolation) -Si