Fabrication of Cu interconnects of 50 nm linewidth by electron-beam lithography and high-density plasma etching

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1 Fabrication of Cu interconnects of 50 nm linewidth by electron-beam lithography and high-density plasma etching Y. Hsu, T. E. F. M. Standaert, G. S. Oehrlein, and T. S. Kuan a) Department of Physics, University at Albany, SUNY, Albany, New York E. Sayre and K. Rose Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, New York K. Y. Lee b) and S. M. Rossnagel IBM Thomas J. Watson Research Center, Yorktown Heights, New York Received 29 May 1998; accepted 16 September 1998 The feasibility of building Cu interconnects with a linewidth as small as 50 nm embedded in insulating SiO 2 has been explored using the damascene process. Fine line test structures, designed for evaluating effects of small linewidth on metal line electric resistivity, were written on a poly methylmethacrylate resist layer and then transferred to the underlying SiO 2 layer by high-density plasma etching. Using a CHF 3 etching gas and an inductive power of 400 W, we were able to produce 50-nm-wide and 150-nm-deep trenches in SiO 2. These trenches were then filled with a thin 5 10 nm TaSiN or TaN liner and a thick Cu layer by the ionized physical vapor deposition technique. The field Cu was removed by a chemical-mechanical polishing process, leaving narrow damascene Cu in the oxide trenches. Direct current resistance measurements have indicated a wide distribution of resistivity in these fine lines. The low end of the distribution is close to the effective resistivity of a perfect Cu line. The high values are indicative of severe necking or other imperfections induced during the fabrication process American Vacuum Society. S X I. INTRODUCTION a Electronic mail: kuan@cnsibm.albany.edu b Current address: Etec Systems, Inc., Corporate Ave., Hayward, CA As the transistor size continues to decrease and the circuit count continues to increase, the on-chip interconnect linewidth will eventually be reduced to 0.1 m or less. 1 To realize such small linewidths, one needs to explore whether existing fabrication processes can be extended to such small feature sizes. It is also important to investigate whether acceptable performance, e.g., resistivity, maximum current, reliability, etc., can possibly be delivered by such narrow metal lines. For the upcoming generation interconnect technology, damascene copper has emerged to be the material/process of choice. 2,3 The goal of this study, therefore, is to explore whether the damascene process can be extended to building Cu interconnects with linewidth smaller than 0.1 m and to test the performance limits of these ultrafine Cu lines. For Cu metallurgy, a thin liner is required to provide a diffusion barrier and to enhance adhesion with the insulator. As the linewidth shrinks below 0.1 m, the resistivity may increase drastically if the highly resistive liner is not shrunk proportionally. 4 In a damascene process, an insulator film is patterned with recesses, which are then filled with metal and planarized. 5 To extend this process to sub 0.1 m size regime, we have to use electron-beam lithography and high-density plasma etching for patterning. The use of chemical-mechanical polishing for planarization may pose critical concerns of defect generation and corrosion. Resistivity measurements would provide quantitative assessments on the manufacturability of these fine lines. II. TEST STRUCTURE FABRICATION A. Test structure patterning Three different test structures were designed for evaluating the manufacturability and electrical resistivity of fine metal lines. The first structure Fig. 1 a has six contact pads, which allow four-probe measurements to be performed on different line segments. The second structure Fig. 1 b has four contact pads connecting to a fine line. The third Fig. 1 c van der Pauw structure was originally intended for sheet resistance measurements. These test structures and a parallel line pattern for scanning electron microscopy SEM and transmission electron microscopy TEM analysis of line cross sections were written onto a 200-nm-thick 950 poly methylmethacrylate PMMA resist layer in a JEOL JSM-848 SEM using the Nabity s Nanometer Pattern Generation System. 6 A two-step-writing scheme was adopted in which the fine line was written at 1000 magnification for precision and contact pads were written at 100 for speed. The image shift between two writing steps was electronically adjusted to within 50 nm. Using 40 kv electrons, a line dose of nc/cm was found to produce a linewidth of nm in PMMA. A transformer coupled plasma TCP reactor, which can achieve a high degree of ionization (10 2 ) at low pressure, 7,8 was used to transfer the test patterns in the resist layer to the 3344 J. Vac. Sci. Technol. B 16 6, Nov/Dec X/98/16 6 /3344/5/$ American Vacuum Society 3344

2 3345 Hsu et al.: Fabrication of Cu interconnects of 50 nm linewidth 3345 FIG. 2. a. Narrow 50 nm trenches etched in SiO 2 by high-density plasma. The line pattern was written on a 200-nm-thick PMMA resist using 40 kv electrons at 3 nc/cm line dose. The etching gas was 40 sccm CHF 3 at 5.3 mtorr pressure. An inductive power of 400 W and a rf bias power of 25 W were used for the 60 s etch. The remaining PMMA ( 80 nm) has been removed. b Even narrower 20 nm trenches were etched in SiO 2 by using ac 3 F 6 etching gas with a 400 W inductive power and a 33 W rf bias power for 120 s. The remaining PMMA ( 30 nm) has been removed. underlying 500-nm-thick SiO 2 layer. A relatively low inductive power of 400 W MHz was used to minimize plasma induced modifications of the PMMA. At higher inductive powers ( 1 kw) the test patterns would be destroyed. The plasma was fed with 40 sccm CHF 3 and maintained at a pressure of 5.3 mtorr. The average ion energy at the wafer was increased to approximately 125 ev by applying 25 W 3 MHz rf bias power to the wafer. Under this etching condition, the SiO 2 etch rate remained constant at FIG. 1. Three test structures designed for four-probe measurements of resistivity in ultrafine metal lines. FIG. 3. TEM cross-sectional image of a narrow trench with an average width of 60 nm filled with a 15-nm-thick TaN liner on the sidewall and a 250-nm-thick Cu layer on top. The upper part of the Cu film was milled away in the sample preparation process. JVST B - Microelectronics and Nanometer Structures

3 3346 Hsu et al.: Fabrication of Cu interconnects of 50 nm linewidth 3346 FIG. 5. a 16 na supply and b the 100 na supply for the ultrafine metal line resistance measurements. plasma-resist interactions also affect the etching profile. For instance, a C 3 F 6 discharge was found to produce even narrower trenches 20 nm wide and 200 nm deep with a 10 aspect ratio Fig. 2 b. In our process of fabricating ultrafine Cu interconnect test structures, CHF 3 etching gas was used. The average trench width was 40 nm in the sixcontact-pad structure and was 60 nm in the four-contactpad and the van der Pauw structures. FIG. 4. a Six-contact-pad test structure after removal of field Cu by the chemical-mechanical polishing process. b Four-contact-pad test structure after removal of field Cu by the chemical-mechanical polishing process. Left on the oxide surface are small alumina slurry particles. c van der Pauw test structure after removal of field Cu by the chemical-mechanical polishing process. Left on the wafer surface are small alumina slurry particles nm/min while the PMMA etch rate decreased from an initial 150 to 100 nm/min in 60 s. The average SiO 2 /PMMA selectivity was thus about 1.3. As shown in Fig. 2 a, trenches in SiO 2, 150 nm deep and 50 nm wide ( 60 nm on top and tapered to 30 nm at the bottom, due to plasma and resist and oxide surface interactions, 7 were achieved after a 60 s etch. The plasma interacts strongly with the PMMA resist as is demonstrated in Fig. 2 b where the patterning was performed using 40 sccm C 3 F 6. Here the plasma was found to penetrate through the thin resist and roughen the underlying oxide surface. Surface roughening of the underlying oxide can be minimized by stopping the etch process as the resist thickness approaches 50 nm. The B. Liner deposition and Cu trench fill The trenches were lined with Ta-based films, which functioned as both a diffusion barrier and also as an adhesion layer for the Cu primary conductor. The Ta films used were nitrides of TaSi and Ta. The liner films were deposited with conventional physical vapor deposition PVD using large area, rotating magnet magnetron sputter sources. In the Ta- SiN case, the films were deposited at 1 mtorr with an 80:20 Ar:N 2 ratio and a magnetron power of 2 kw for 15 s for a 15 nm field coverage. In the TaN case, the Ar:N 2 ratio was slightly lower and the total pressure was 1.5 mtorr. The cathode power was 2.5 kw and the deposition time was 30 s for a 30 nm field deposition. The expected in-trench thickness was 5 nm for the TaSiN case and 10 nm for the TaN case. The liner could be thicker on tapered sidewalls. The Cu deposition was carried out immediately after liner deposition in an adjacent chamber. The Cu was deposited using ionized magnetron sputtering in which the sputtered Cu atoms are ionized in-flight and deposited at the wafer as Cu ions. 9 The ionized physical vapor deposition I-PVD technique is used to project the depositing metal ions deep into the trench structures to provide a more dense film than conventional PVD, which generally results in void formation at aspect ratio greater than 1:1. The I-PVD Cu deposition was carried out at 45 mtorr in Ar with 600 W dc applied to the magnetron and 1200 W rf applied to an inductively coupled antenna located within the deposition chamber. The wafer samples were kept at ground potential, which leads to a net deposition kinetic energy for the Cu of about 15 ev.

4 3347 Hsu et al.: Fabrication of Cu interconnects of 50 nm linewidth 3347 TABLE I. Electrical resistivity of Cu fine lines. Sample Source current na Device voltage V Line resistance k Line length m Resistance/ m / m Effective resistivity a cm Six-contact-pad structure EL4-11, TaSiN liner Pad 2 Pad Pad 3 Pad Pad 3 Pad Four-contact-pad structure TaN liner EL6-4A EL6-6A EL6-4C EL6-6C Van der Pauw structure TaN liner EL6-4a south west north west north south north south west EL6-4b north west EL6-6c south west east west south east south west east a Calculated assuming a 2500 nm 2 line cross section for the EL4 samples and 5000 nm 2 for the EL6 samples. The samples were clamped to a water-cooled chuck maintained at 20 C and the wafer temperature increase during the 3 min depositions was expected to be no more than 25. After the Cu deposition, the samples remained in vacuum for 15 min and then were vented with N 2. TEM and SEM observations indicated a conformal liner, good Cu film, and an average Cu grain size of greater than 50 nm. Figure 3 shows a cross-sectional TEM image of a trench lined with a 15-nm-thick TaN film and filled with I-PVD Cu. The I-PVD was able to fill the 170-nm-deep trench with a width tapered from 65 top to 30 nm bottom. C. Metal planarization To complete the fine line test structure, the field Cu was removed by the chemical-mechanical polishing CMP technique. A 6-in. diam Buehler Ecomet III desk-top polisher and a slurry containing 50-nm-sized alumina (ph 3.7) were used at 5 psi polishing pressure. The polishing pad was conditioned before each polish. For a polishing speed of about 50 rpm, no visual scratches in the device area were found under optical and SEM examinations. The CMP step used was able to remove the 15 nm field TaSiN at the risk of over-polishing Cu but not able to polish away the 30 nm field TaN. The TaN layer was removed by a plasma etching step in the TCP reactor Sec. II A using 40 sccm CF 4 at 6 mtorr pressure, 1 kw inductive power MHz, and 100 W bias power 3 MHz for 20 s. SEM observations have shown that 50-nm-wide damascene Cu lines were left in the oxide trenches after the polishing and plasma processes as shown in Fig. 4. III. ELECTRICAL MEASUREMENTS The testing of a nanolinewidth structure requires very low current densities, due to the small cross sectional area of the structure. A conservative limit of the current density in an Al Si metallization structure is in the 10 5 A/cm 2 range, yielding a 20-year lifetime. 10 Cu interconnects have been seen to be reliable up to two orders of magnitude longer than Al Cu with maximum current densities in the 10 7 A/cm 2 range. 11 Based on the dimensions of the Cu fine line fabricated in this study cross-section area 2500 nm 2 ) the maximum current that can flow without damaging a perfect device is 25 A. Since these devices cannot be assumed to yield the exact drawn dimensions, the applied current must be significantly reduced to a level that will give us meaningful results. In this case the current was reduced to the two supply values of 100 and 16 na, giving a current density of and A/cm 2, respectively. These low currents enable the measurement of lines that are necked down or partially nonconductive without burning them out. Figure 5 a shows the Thevenin equivalent supply for the 16 na source using a 1.6 V battery with resistors for voltage division and current limiting. The supply current was measured by observing the voltage drop, V sc, across a known JVST B - Microelectronics and Nanometer Structures

5 3348 Hsu et al.: Fabrication of Cu interconnects of 50 nm linewidth 3348 resistor, R s. The voltage measured across the device under test DUT is labeled V device : R DUT V device R s /V sc. The1M resistor shunting the DUT introduces a negligible error for the DUTs measured. For the 100 na source, the voltage division resistors were removed and replaced by R s 16 M as shown in Fig. 5 b. Conduction was established during the probing of the DUT by noticing a rise in V sc due to the increased current flow through the fine line test structure. Errors in the measurements due to the geometry of the structure s layout in Figs. 1 b and 1 c were found to introduce four squares to an approximately 200 square line a 2% negligible error. The measurement of the test structures was performed using a HP34401A multimeter, to measure the source current, and a HP34420A nanovolt/micro ohm meter, to measure the device voltage. For the voltages measured, the rated voltage error was about 1.8% 3.5 V for the HP34401A and about 25 nv 3% for the HP34420A. The DUT was probed in a shielded box. Twisted pair wire was used wherever possible to minimize inductive pickup, and conductor changes in the V device path were kept symmetrical to minimize thermal voltages. Turning off nearby computers and building services significantly reduced pickup levels of noise. In practice, V device had a significant dc offset of hundreds of nanovolts and a slow drift, which was nulled out before each measurement. The measurement results from three types of test structures are listed in Table I. In a six contact pad structure with a TaSiN liner, three line segments were found to exhibit resistivity from as low as 3 cm to an order of magnitude higher. The low value is close to a 2.5 cm resistivity value measured from a 0.5- m-wide Cu line with a 20-nmthick Ta liner, 4 suggesting that drastic increase in line resistivity would not occur when the liner is shrunk proportionally with metal linewidth. The high resistivities 24 and 59 cm manifested in the same test structure, however, demonstrate that process-induced irregularities would become a serious concern in the sub-0.1 m linewidth regime. The four contact pad and the van der Pauw structures, which contain thicker TaN liners, also show a wide distribution of resistivity values ranging from 40 cm to more than 30 higher. In the van der Pauw structure, combinations of two branches in the cross structure e.g., south and west branches were measured and contribution from each branch was calculated. As listed in Table I, large variations between neighboring branches were observed, indicating the local nature of the cause for high resistivity. It is believed that small scratches, dishing, necking, missing grains, corrosions at grain boundaries, and at liner interfaces and other irregularities induced during the CMP process are the most likely sources of large resistivity increases. IV. CONCLUSIONS We have demonstrated the feasibility of building 50-nmwide Cu interconnects embedded in insulating SiO 2 and wrapped in a TaSiN or TaN ultrathin liner using the damascene approach. By electron-beam lithography and highdensity plasma etching we were able to produce 50-nm-wide trenches in SiO 2 with aspect ratio 3. Using these narrow trenches and ionized PVD and CMP processes we have fabricated three different test structures suitable for four-probe resistivity measurements. It was found that only a small number of lines exhibit an effective resistivity of the same order of magnitude as the bulk value. Most of the lines have resistivity values that fall in a wide distribution ranging from 3 to more than 1000 cm. It is believed that CMP-induced irregularities in the line such as scratches, necking, and local corrosions are the most likely sources of drastic increase in resistivity. Our results suggest that if thin ( 5 nm) liners are used and the CMP-induced defects can be prevented or eliminated, a resistivity of the order of 10 cm should be achievable in a 50-nm-wide Cu line. Whether a 5-nm-thick liner can be an effective diffusion barrier remains to be investigated. ACKNOWLEDGMENTS This research was partially funded by the SRC Center for Advanced Interconnect Science and Technology, Task ID: We are grateful to JEOL USA, Inc. for donating the JSM-IC848 scanning electron microscope, without which this work would not have been possible. 1 The National Technology Roadmap for Semiconductors Semiconductor Industry Association, San Jose, CA, Mater. Res. Bull. 19, IBM J. Res. Dev. 30, J. Paraszczak, D. Edelstein, S. Cohen, E. Babich, and J. Hummel, Tech. Dig. Int. Electron Devices Meet. 93, T. J. Licata, E. G. Colgan, J. M. E. Harper, and S. E. Luce, IBM J. Res. Dev. 30, J. C. Nabity and M. N. Wybourne, Rev. Sci. Instrum. 60, ; For current version contact: JC Nabity Lithography Systems, P.O. Box 5354, Bozeman, MT G. S. Oehrlein, in Plasma Processing of Semiconductors, edited by P. F. Williams Kluwer, Dordrecht, 1997, p N. R. Rueger, J. J. Beulens, M. Schaepkens, M. F. Doemling, J. M. Mirza, T. E. F. M. Standaert, and G. S. Oehrlein, J. Vac. Sci. Technol. A 15, S. M. Rossnagel, Thin Solid Films 263, The Science and Engineering of Microelectronic Fabrication, edited by Stephen Campbell Oxford University Press, New York, D. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lustig, P. Roper, T. McDevitt, W. Motsiff, A. Simon, J. Dukovic, R. Wachnik, H. Rathore, R. Schulz, L. Su, S. Luce, and J. Slattery, Tech. Dig. Int. Electron Devices Meet. 97,