Integrated Circuit Engineering Corporation EPROM

Transcription

1 EPROM There was lots of discussion and many technical papers covering the promises of EPROM (typically Flash) at the IEDM conference last December, but here as in the other memory areas, not much in the way of actual product change was observed. In fact, the most aggressive technology seen was used by the one-time programable types. It appeared to be generally agreed at an IEDM panel discussion that even if EPROM can be successfully developed to store more than one bit (don t hold your breath), DRAM will not likely roll over and die since the markets and production capacity for the two technologies vary so greatly. 3-1

2 HORIZONTAL DIMENSIONS (DESIGN RULES) EPROM XICOR XC28C010 1Mb EEPROM 9443 HITACHI HN58C1001P-12 1Mb EEPROM ATMEL AT27C Mb EPROM 9428 ISSI IS27HC010 1Mb EPROM Die size 5.7 x 8.9 mm (51 mm 2 ) 6.1 x 8.2 mm (50 mm 2 ) 3.4 x 4.3 mm (14.6 mm 2 ) 4 x 4.5 mm (18 mm 2 ) Min M2 width 2.5µm NA NA NA Min M1 width 1.3µm 1.0µm 1.2µm 1.0µm Min M2 space 1.7µm NA NA NA Min M1 space 1.5µm 1.0µm 1.0µm 1.0µm Min via (M2 to M1) 1.7µm NA NA NA Min cntct (to Si) 1.0µm 1.0µm 0.9µm + 0.8µm + Min Poly 2 2.1µm 0.6µm * 0.4µm * 0.7µm * Min Poly 1 1.3µm 0.75µm 0.6µm 0.7µm Min gate - (N) 1.3µm 0.6µm 0.6µm 0.7µm Min gate - (P) 1.5µm 0.6µm 1.4µm 0.85µm Cell pitch 2.6 x 8.1µm 4.25 x 5.3µm 2.1 x 2.1µm 2.5 x 2.7µm Cell area 21µm µm 2 4.4µm 2 6.8µm 2 *Polycide Physical gate length TABLE Plugs

3 VERTICAL DIMENSIONS EPROM XICOR XC28C010 1Mb EEPROM 9443 HITACHI HN58C1001P-12 1Mb EEPROM ATMEL AT27C Mb EPROM 9428 ISSI IS27HC010 1Mb EPROM Final passivation 1.1µm 1.25µm 1.25µm 1.7µm Metal 2 1.2µm NA NA NA Metal µm 0.85µm 0.9µm 1.0µm Intermetal dielectric 1.0µm NA NA NA Poly 2 0.2µm 0.3µm 0.35µm * 0.4µm * Poly 1 0.2µm 0.12µm 0.2µm 0.15µm Recessed oxide 0.5µm 0.55µm 0.7µm 0.45µm N-well 4µm 3.5µm 6.5µm 5.5µm P-well 3.5µm 3.5µm? None Epi 11µm (P) None None None * Polycide Could not delineate Trench TABLE 3-2

4 DIE MATERIALS EPROM XICOR XC28C010 1Mb EEPROM 9443 HITACHI HN58C1001P-12 1Mb EEPROM ATMEL AT27C Mb EPROM 9428 ISSI IS27HC010 1Mb EPROM Final passivation Glass Nitride on glass Glass on glass Glass on glass Metal 2 Aluminum NA NA NA Contact Plugs NA NA Tungsten Tungsten Intermetal dielectric Glass NA NA NA Metal 1 Molybdenum Titanium-tungsten Polysilicon Aluminum Polysilicon Aluminum Titanium-nitride Titanium Aluminum Titanium-nitride Titanium Interpoly dielectric ONO NA Oxide ONO Reflow glass BPSG BPSG BPSG BPSG Polycide metal NA Tungsten Titanium Tungsten TABLE 3-3

5 TECHNOLOGY DESCRIPTION XICOR X28C010J-20 1 Mbit EEPROM Introduction Ref. report SCA These parts were packaged in 32-pin, J-lead, Plastic Leaded Chip Carrier packages (PLCCs) date coded The devices were fully functional production parts. They operate from a 5V supply voltage. See tables for specific dimensions and materials identification and see figures for examples of physical structures. Unusual/Unique Features - Deep trench nitride/oxide isolation. - Molybdenum metal 1 interconnect. - Unique cell design. Quality Quality of process implementation was normal except for cracks in metal 1 at the bottom perimeter of contacts. In the area of layer patterning, etch definition was good and etch control was normal except at contacts. 3-2

6 Alignment/registration was good. Technology These devices were made by a twin-well CMOS process, employing a P-epi on a P substrate. Two levels of metal and two levels of poly (no polycides) were used. A deep nitride and oxide filled trench isolation was employed. The final passivation consisted of a substantial layer of phosphorus doped glass that was not planarized. Metal 2 consisted of aluminum defined by a dry etch technique and had no cap or barrier layer. Metal 1 was a layer of molybdenum on a barrier of titanium-tungsten. No plugs were used at contacts to silicon or at intermetal vias, both making use of the standard design instead. As mentioned, overetching of the contacts caused cracking of the M1 barrier at contact perimeters. No buried contacts were used. Metal 2 contacted metal 1, and metal 1 contacted diffusions and poly 1. Planarization of the intermetal dielectric was by two layers of deposited glass and some minor planarizing etch. A spin-on-glass (SOG) was not used. The dielectric under metal 1 was planarized by a reflow process. Standard implants were employed for the source/drain diffusions. No LDD techniques were employed and no salicide source/drain treatment was present. There were at least two different gate oxides present plus two different interpoly dielectrics. 3-3

7 The most unique feature of these products was the deep, nitride filled trench isolation. We have not seen this used by any other manufactrer. In fact, it is a combination of a deep trench combined with a normal recessed oxide. It appears to be formed by etching deep narrow trenches at the perimeter of all diffusion areas, then filling these (and probably covering the areas that will become diffusions) with a substantial layer of silicon-nitride. This then appears to be followed by a fairly normal oxidation cycle which provides the oxide (LOCOS) in all the field areas. Use of the molybdenum on titanium-tungsten is also unique. Overall minimum feature measured anywhere on these dice was the 1.3 micron poly 1 width and the 1.0 micron contact diameter. Minimum gate lengths measured were 1.3 micron for N- channel and 1.5 micron for P- channel gates. Memory Cell Structures The EEPROM memory cells consisted of metal 2 piggyback word lines, metal 1 bit lines, poly 2 word lines/select gates and poly 1 floating gate/program lines. Programming is achieved through an ultra-thin (tunnel) oxide inter-poly dielectric. A cell of 21 microns 2 results. No trench isolation was present in the cell array. Packaging/Assembly As mentioned, devices were packaged in 32-pin Plastic Leaded Chip Carriers (PLCCs) within J-leads. A dimpled paddle was used for added strength. Standard gold wire provided the internal connections. No evidence of a die coat was found. 3-4

8 Xicor X28C010J-20 Whole die photograph of Xicor 128K x 8 EEPROM. Mag. 26x.

9 Xicor X28C010J-20 glass etch silicon etch SEM section views illustrating general structure. Mag. 10,000x.

10 Xicor X28C010J-20 POLY 1 PROGRAM LINE Mag. 10,000x Mag. 10,000x BIT LINE Mag. 20,000x Detailed views of the EEPROM cell design.

11 Xicor X28C010J-20 DEEP TRENCH Mag. 4000x, 60 Mag. 30,000x Perspective SEM views of poly 1 gates and trench isolation.

12 TECHNOLOGY DESCRIPTION HITACHI HN58C1001P-12 1 Mbit EEPROM Introduction Ref. report SCA These parts were packaged in 32-pin, metal lid ceramic DIPs. No date code was present, but we believe late 1994 to early 1995 probable. Memory organization was 128K x 8 bits. The devices were fully functional parts. They operate from a 5V supply voltage. See tables for specific dimensions and materials identification and see figures for examples of physical structures. Unusual/Unique Features - Polyimide die coat. - Polysilicon cap and barrier layers on aluminum. - MNOS memory technology. Quality Quality of process implementation was normal although very large silicon nodules were present in the aluminum interconnect. In the area of layer patterning, both etch definition and control (depth) was normal. Alignment/registration was good. 3-5

13 Technology These devices were made by a twin-well CMOS process, employing an N substrate (no epi). One level of metal and two levels of poly (one polycide) were used. A standard local oxide isolation was employed. The memory array made use of MNOS transistors for program gates. The final passivation consisted of a thick layer of silicon-nitride over a thin layer of phosphorus doped glass. No attempt was made to planarize this layer, but dice did employ a spun-on polyimide die coat, presumably to protect against alpha particle radiation induced leakage effects. Metal consisted of aluminum defined by a dry etch technique and had a polysilicon cap and barrier layer. This is considered quite unusual. We have no clear recollection of having seen a polysilicon cap layers and we have not seen polysilicon used for a barrier in many years. No plugs were used at contacts to silicon, standard contacts being used instead. No buried contacts were used and no salicide treatment of the source/drain diffusions was employed. The dielectric under metal 1 was planarized by a standard reflow process. Apparently, the old method of performing reflow after contact cuts was used. This improves ease of covering contact steps with metal. Standard implants were employed for the source/drain diffusions. All transistors used LDD techniques making use of oxide sidewall spacers on the gates. Two different gate dielectrics were present. The standard gate oxide was used for all normal transistors which used polycide gates. A thin nitride on oxide gate dielectric (MNOS) was used for the program gates (which used simple polysilicon not polycide gate electrodes). 3-6

14 This and the poly caps and barriers were the most unique features of this product. Overall minimum feature measured anywhere on these dice was the 0.6 micron polycide width. Minimum gate lengths measured were 0.6 micron for both N- channel and P-channel gates. Program MNOS gates were 0.75 micron. Memory Cell Structures The EEPROM memory cells consisted of metal bit lines, polycide word lines/select gates and poly program lines. As mentioned, the programable gates were of the MNOS type in which charge is trapped in the nitride dielectric by hot electron tunneling. The result is a large but fairly simple cell, measuring 22.5 microns 2. Packaging/Assembly As mentioned, devices were packaged in 32-pin, metal lid ceramic dual-in-line packages (DIPs). Ultrasonic wirebonding (done backwards) using aluminum wire was used. No problems or unusual conditions were noted except for the fact that a thin even, patterned, polyimide die coat was present on the dice. Silver glass die attach was employed. 3-7

15 Hitachi MN58C1001P-12 Whole die photograph of the Hitachi 1M EEPROM. Mag. 25x.

16 Hitachi MN58C1001P-12 PASSIVATION METAL LOCAL OXIDE POLYCIDE INTERMEDIATE GLASS glass etch, Mag. 10,000x PASSIVATION 2 PASSIVATION 1 Si METAL Si P+ P+ POLYCIDE silicon etch, Mag. 13,000x SEM section views illustrating general device structure.

17 Hitachi MN58C1001P-12 BIT 1 BIT 0 POLY PROGRAM LINE POLYCIDE SELECT LINE Topological SEM views of the MNOS EEPROM array. Mag. 3000x, 0.

18 Hitachi MN58C1001P-12 METAL POLYCIDE POLY Mag. 26,000x METAL SIDEWALL SPACER INTERMEDIATE GLASS Mag. 40,000x POLY N+ S/D SILICON-NITRIDE SIDEWALL SPACER POLYCIDE Mag. 40,000x N+ S/D GATE OXIDE SEM section views of the EEPROM cell.

19 TECHNOLOGY DESCRIPTION ATMEL AT27C Mbit EPROM Introduction Ref. report SCA This part was packaged in a 32-pin, CERDIP package date coded The device was a fully functional production part. These parts operate from a 5V supply voltage. See tables for specific dimensions and materials identification and see figures for examples of physical structures. Unusual/Unique Features - Salicide process. - Tungsten plugs. - Short gates (0.5µm N-channel). - Planarized passivation. - Poly gates on gate oxide over guardband diffusions. Quality Quality of process implementation was good. We found no areas of concern. In the area of layer patterning, etch definition and control were good. 3-8

20 Alignment/registration was also good. Technology These devices were made by a twin-well CMOS process, on a P substrate (no epi). One level of metal and two levels of poly (one polycide) were used. Contacts used tungsten plugs, and a standard local oxide isolation was employed. Diffusions were silicided (salicide process) and memory cells used the stacked gate design. These modern and rather advanced process features are unusual on a rather ordinary part type like this. The final passivation consisted of two substantial layers of glass the first of which was planarized by RIE etching. Metal consisted of aluminum defined by a dry etch technique and had no cap. A barrier of titanium-nitride on a titanium adhesion layer was employed. Tungsten plugs were used at all contacts and the titanium-nitride barrier and titanium adhesion layers were present underneath. Control of plug shape and height was good. No buried contacts were used. Standard implanted diffusions were employed for the source/drain diffusions. An LDD technique was employed using oxide sidewall spacers on the poly gates. As mentioned, a salicide source/drain treatment was present. Unusual (unique) poly/diffusion structures were also present at some guardbands. Although sample limitations prevented us from checking in more detail, it appeared that for one polarity of the guardbands, polycide was allowed to cross on gate oxide (no field oxide) while for the other polarity a field oxide was present over the guardband diffusion. The reason for doing this is not clear since as a minimum detriment significant capacitance is added by doing this. 3-9

21 At least three different thin oxides were present, two in the memory array and one in the periphery. Overall minimum feature measured anywhere on these dice was the 0.4 micron poly 2 width (polycide). Minimum gate lengths measured were 0.6 micron for N- channel in the array, 0.9 micron N-channel and 1.4 micron for P-channel gates in the periphery. Memory Cell Structures The EPROM memory cells used a fairly standard 2 poly stacked gate design. Poly 2 (polycide) formed the word lines/select gates and poly 1 the floating gates. Interpoly dielectric was thin oxide only (no nitride). Cell pitch was 2.1 x 2.1 microns resulting in a quite small 4.4 microns 2 area. Packaging/Assembly As mentioned, the device was packaged in a 32-pin CERDIP package. Silver glass die attach and ultrasonic wirebonding used aluminum wire. A bonding post in the package cavity was used to allow wirebond connection from die surface to die substrate. This is also unusual for a CMOS die. No evidence of a die coat was found. 3-10

22 Atmel AT27C PIN 1 Whole die photograph of the Atmel 1Mb EPROM. Mag. 48x.

23 Atmel AT27C PLUG glass etch, Mag. 13,500x PASSIVATION 2 METAL silicon etch, Mag. 15,000x SEM section views illustrating general device structure.

24 Atmel AT27C Mag. 3000x Mag. 20,000x Mag. 20,000x Perspective SEM views of polycide gate structures. 60.

25 Atmel AT27C METAL BIT LINE POLYCIDE Mag. 13,500x Mag. 18,000x SEM section views of EPROM cells.

26 TECHNOLOGY DESCRIPTION ISSI IS27HC Mbit EPROM Introduction Ref. report SCA This part was packaged in a 32-pin, CERDIP package. The date code was not identifiable, but is believed to be early The device was a fully functional production part. This is a one time programable memory design. These parts operate from a 5V supply voltage. See tables for specific dimensions and materials identification and see figures for examples of physical structures. Unusual/Unique Features - Tungsten plugs at contacts. - Modern EPROM process. Quality Quality of process implementation was good. We found no areas of concern. In the area of layer patterning, etch definition and etch control (depth) were both good. Alignment/registration was also good. 3-11

27 Technology These devices were made by an N-well CMOS process on a P substrate, employing one level of metal and two levels of poly (one polycide). Standard local oxide isolation was used but bridsbeaks were kept short. Memory cells used on ONO interpoly dielectric. The final passivation consisted of two thick layers of glass that were not planarized. Metal consisted of aluminum defined by a dry etch technique and had no cap but did employ a barrier of titanium-nitride on a titanium adhesion layer. The barrier and adhesion layer were also present under the tungsten contact plugs. The plugs were noticeably well controlled being very straight, with excellent height control and no sign of contact overetch. Poly 2 (polycide) provided all gates in the peripheral circuitry and the program gates in the cell array. All gates used oxide sidewall spacers that were left in place. Poly 1 was only used for floating gates in the cell array. Planarization of the intermediate oxide was by a standard reflow glass. No spin-on-glass (SOG) was used. Standard implants were employed for the source/drain diffusions. The LDD technique used oxide sidewall spacers that were left in place at the sides of the gates. No buried contacts were used, and no salicide source/drain treatment was present. At least three different thin oxides were present. One for poly 1 in the memory array, one for the interpoly dielectric (ONO) and one for peripheral gates. The most unique feature of these products was the modern process used for this rather mature device type. 3-12

28 Overall minimum feature measured anywhere on these dice was the 0.7 micron poly 1 and polycide widths. Minimum gate lengths measured were 0.7 micron for N- channel and 0.85 micron for P-channel gates. Floating gates in the cell array were also 0.7 micron. Memory Cell Structures The EPROM memory cells used a standard stacked dual gate design employing poly 1 floating gates and polycide (poly 2) word lines. Metal provided the bit lines. As mentioned, the interpoly dielectric was an oxide-nitride-oxide (ONO). Cell size was 2.5 x 2.7 microns (6.8µm 2 ). Packaging/Assembly The assembly was not evaluated separately but appeared perfectly normal from casual observation. No evidence of a die coat was found. 3-13

29 ISSI IS27HC010 Whole die photograph of the ISSI 1 Mbit EPROM. Mag. 36x.

30 ISSI IS27HC010 glass etch, Mag. 12,000x silicon etch, Mag. 13,000x SEM section views illustrating general device structure.

31 ISSI IS27HC010 Y-direction, Mag. 13,500x X-direction, Mag. 13,000x X-direction, glass etch, Mag. 55,000x SEM section views of the EPROM cells.