45nm Reliability Issues. Glenn Alers Integration Group Novellus Systems

Transcription

1 45nm Reliability Issues Glenn Alers Integration Group Novellus Systems 1

2 Integration Challenges for Interconnects Maintain low RC with reduced line widths No sacrifice in reliability Reduced Cu line width Increased copper resistivity Decreased electromigration Reduced barrier thickness Greater conformality of barriers required Contamination control (Cu and polymers) Stress management Same stress / smaller CD = larger gradient Smaller critical void volume 2 Alers-AMC 2004

3 Reliability Concerns for Copper Scaling (1) Via reliability: Limits to scaling Smaller features >> larger stress gradients Thinner barriers >> less coverage >> poor Cu/barrier adhesion e (2) Electromigration: Limits to scaling Smaller features >> less material to migrate Thinner barriers >> less barrier coverage Increasing product requirements Dielectric Reliability: Limits to scaling Low k inter-level dielectrics: soft / poor adhesion Low k dielectric barriers: Less hermetic (Another discussion) 3 Alers-AMC 2004

4 Via Reliability: Scaling Problems 1) Stress: larger stress gradients 2) Via voids: greater sensitivity Potential problems with vias Microtrenching Fences Voids 3) Barrier coverage: thin barriers 4) Etch profile: smaller tolerances SiN or SiC undercut Adhesion σ σ Trench/Via Roughness Trench Depth Variation Via CD Via problems can result in reliability failures 4 Alers-AMC 2004

5 High Stress in Copper Interconnects Byung-Lyul Park st al. (Samsung) IEEE IITC (2002) First Thermal Cycle (passivation): stress ~ 250MPa Recrystallization: stress ~ 20MPa Stress Concentration = Defects Cu stress fundamental to thermal expansion of Cu 5 Alers-AMC 2004

6 Mechanisms for Stress Induced Via Failures (1) Void migration after 400 o C PECVD cycle (2) Stress relaxation at 150 o C o C (3) Poor barrier coverage Fill or etch voids High tensile stress Cu or etch residue Voids migrate to bottom at 400 o C Relaxation of stress = M1 or M2 voids Poor Cu adhesion to via sidewall with thin barrier Voids at via sidewall 6 Alers-AMC 2004

7 Stress Distribution in Via at 400 o C M. Tagami et al., (NEC) IEEE-IITC IITC (2003) Stress concentration in bottom and top of via Copper soft at 400 o C Migration of voids to bottom and middle of via 7 Alers-AMC 2004

8 Broken Vias After Thermal Cycle Failure analysis of via chains after anneal Prior to 400 o C thermal Cycle Voids apparent at via corners After 400C thermal cycle Voids grow with thermal stress >> break in copper of via Via connected before thermal treatment After thermal cycle: partial voids become full voids 8 Alers-AMC 2004

9 Via Reliability: High Temperature Yield Drop Voids in via: Poor barrier / copper adhesion Fill related voids -- migration to regions of high stress Etch profile / poor barrier coverage -- failures at via bottom Yield drop after high temperature cycle Partial voids in via grow with high stress Voids migration to regions of high stress High integrity vias required to survive thermal cycles 9 Alers-AMC 2004

10 Long Time Tests of Kelvin Vias Chain of 5 Kelvins vias with large metal area 5 Kelvin via chain Relative Resistance Change Hard early failure Soft failure No resistance shift low current at 200 o C Vias failures with no stress Resistance increases before failure Vias fail spontaneously = major reliability concern 10 Alers-AMC 2004

11 Void growth in vias with large contact area M. Kawano et al. (NEC) IEEE IITC (2002) Failures occur at via contact with large copper volume 11 Alers-AMC 2004

12 Void growth depends on Cu volume K. Yoshida et al (Toshiba) IEEE IEDM (2002) No failures if Cu volume under (over) via is small Failure rate increases with more Cu below (above) via. 12 Alers-AMC 2004

13 Mechanism for void growth: vacancies E. Ogawa et al. (TI) IEEE-IRPS IRPS (2002) Stress Gradient + Vacancy Diffusion Vacancies collect at via -->> Void formation Voids form through vacancy diffusion to maximum stress gradient (via) 13 Alers-AMC 2004

14 Copper creep: stress / diffusion balance E. Ogawa et al. (TI) IEEE-IRPS IRPS (2002) Stress gradient from T Lower stress at higher T Diffusion of vacancies Two competing elements Maximum void growth at ~ 200 o C 14 Alers-AMC 2004

15 Stress Temperature Behavior of Cu films R.P. Vinci, E.M. Zielinski, J.C. Bravman; Thin Sol. Film 262 (1995) 95) Work considers: Grain boundary diffusion Lattice diffusion Low temperature plasticity Power law breakdown Power law creep Elastic 20 o C to 200 o C Inelastic 200 o C to 400 o C Above ~200 o C, yield properties of copper dominate stress 15 Alers-AMC 2004

16 Stress / Temperature Properties of Copper 1µm SiO 2 70nm SiN 1µm Cu 20nm Ta(N) 1µm SiO 2 Linear: Cu / SiO 2 Differential Thermal Contraction Plastic Yield Of Copper Stress (Relative) 100 MPa Temp. (C) Scan #1 Scan #2 Scan #3 Repeatable hysterisis on sequential cycles: Kinematic Strain Final Cu stress determined by Cu yield stress 16 Alers-AMC 2004

17 Stress in Copper Lines S.H. Rhee, Y. Du and P. S. Ho IEEE - IITC (2001) X-Ray measurements of stress in encapsulated copper lines Stress is very high ~ 700MPa at 20 o C Zero stress at ~350 o C Stress Relaxes with time Inelastic behavior is present 17 Alers-AMC 2004

18 Copper Yield Stress and Thickness Stress (MPa) Copper stress level increases as film thickness decreases Affter 350 o C Anneal As Deposited Copper Film thickness (A) Via resistance shift after thermal cycle Geometry scaling: increased copper stress levels Higher copper stress = more likely to form voids 18 Alers-AMC 2004

19 Thickness Dependence and Creep Copper stress limited by yield Creep rate for copper film: 1 & ε t σ Yield n ( T ) σ Yield G. B. Alers et al., Int. Rel. Phys. Symp. (2005) ( T ) exp( Q / kt ) n = 2 for grain boundary n = 1 for lattice diffusion b µ f µ s βt = ln t (1 ν ) µ f + µ s b ε& t ( n+1) Grain boundary dominated creep predicts: SM ~ (thickness) -3 ln{1- failure rate (5% shift)} ~ t Thickness (nm) 19 Alers-AMC 2004

20 Stress Migration in Low-k k Dielectrics Simulation and Experiments of Stress Migration for Cu/low-k BEoL Charlie Jun Zhai, H. Walter Yao, Amit P. Marathe, Paul R. Besser, Richard C. Blish. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, 2004 pg. 523 Stress Migration in USG and FSG Simulation and Experiment Low-k dielectrics vs. FSG: Good: Thermal expansion closer to Cu, stress lower Bad: Adhesion poor for OSG, low critical stress Conclusion: Stress migration depends on process and integration 20 Alers-AMC 2004

21 Control of Stress in Copper Pre-CMP Anneal of Copper Transfer overburden grain size to small features Control resistivity and CMP rate High temperature anneal + Large Cu volume = problems Low temperature (low stress) / long time anneal Stress level is fundamental to copper Copper stress / temperature is NOT elastic Stress level determined by copper flow stress Grain growth: small contribution to stress Stress + Stress Gradients: Stress migration scale as 1/(node) 3.. Big issue in future 21 Alers-AMC 2004

22 Improving Stress Migration: Barrier Process T. Oshima et al., (Hitachi) IEEE IEDM (2002) Optimization of pre-barrier clean process and via profile 22 Alers-AMC 2004

23 Finite Element Calculations: Stress largest at via corner Stress Maximum at Lower Via Corner Minimum barrier coverage at via corner Void nucleation at corner Via Copper SiO2 SiN Metal 1 Copper High Stress at lower via corner void nucleation Sufficient barrier coverage required at lower corner 23 Alers-AMC 2004

24 Improved Barrier Coverage for PVD G. Alers et al., (Novellus) IITC 2003 PVD barrier deposition Barrier accumulation on via bottom not on the sidewalls Ta Ta Ar + After RF Resputter Barrier redistribution from bottom to sidewalls Barrier on bottom RF-Resputter Sputter onto via sides RF Resputter extends life of PVD 24 Alers-AMC 2004

25 Ar + Barrier First Scheme for Via Cleaning Sputter Etch H 2 O, C x H y Ta +,, N 2 Ar + Ta Ar + Ta + Cu + Dielectric Facet Cu 2 O, C x F y TaN/Ta Cu Contamination Ta Degas TaN Preclean Deposition RF-Resputter Ta Deposition Cu Seed RF- Ta Module No low k damage - No Cu contamination of via sidewalls 25 Alers-AMC 2004

26 Barrier First PVD Alloys Scaling of Barrier Via failures at small via size eliminated Decreasing via area: Void larger fraction of via Higher stress gradients Greater sensitivity to contamination Extendibility with barrier first approach Via voids: Greater concern for future generations Controlled with barrier process 26 Alers-AMC 2004

27 ALD TaN Barriers: Interface Issues K. Higashi et al., (NEC) IITC 2004 Resistance shift after 225 o C / 500h anneal Sandwich PVD Ta ALD only via failures Cu wetting to PVD Ta / ALD Ta(CN) Poor interface between Cu and Ta(CN) PVD Ta required over the Ta(CN) layer Poor ALD Ta(CN) / Cu interface: Poor stress migration (and EM) 27 Alers-AMC 2004

28 ALD W(CN) Barriers: Thickness S. Bruynseraede et al., (IMEC, TI, Infineon), IITC 2004 Electromigration for thick ALD W(CN): Better than PVD Ta for t > 4nm (PVD) W(CN) Electromigration: Lower activation energy Worse EM at lower temperatures Electromigration requires ALD W(CN) layers > ~5nm For thick ALD layers, is there an advantage over PVD? 28 Alers-AMC 2004

29 Barrier Process and Reliability High via integrity is required Strong interface between barrier and Cu Good coverage in bottom corners of the via Proper clean optimization to prevent contamination RF Resputter of Ta Improved coverage for PVD allows a thinner barrier Greater extendibility of PVD to smaller geometries ALD deposition of barrier Conformal barrier allows scaling Carbon from precursor degrades adhesion Film continuity and steric hindrance are an issue 29 Alers-AMC 2004

30 Via Stress Migration and Mechanical Properties of Cu Modulate mechanical properties to improve reliability Soft copper Improved VSM Via Stress Migration Stress (MPa) Chemistry #1 Low Yield Stress -100 Stiff copper Degraded VSM Stress (MPa) Temperature ( o C) Chemistry #2 High Yield Stress Temperature ( o C) Lower yield stress = improved via stress migration 30 Alers-AMC 2004

31 Conclusions on Via Reliability Extendibility Via scaling: Smaller critical volume for via failure Larger stress gradients with smaller dimensions High stress in copper films: Slow relaxation Diffusion of vacancies in response to stress gradient Properties of the copper can improve stress migration Higher stress + gradients = worse SM in future High integrity vias are required for reliability Sufficient barrier coverage to assure good adhesion in via Thick barriers increase effective resistivity 31 Alers-AMC 2004

32 Electromigration Extendibility Review electromigration failure mechanism Surface diffusion Bulk diffusion Extendibility of electromigration Improved SiN/SiC adhesion Metallic Caps Alloys of copper Cost to electromigration improvement: Line resistance 32 Alers-AMC 2004

33 Mechanism of Electromigration Cu atoms feel force from electron flow Diffusion of Cu tends towards direction of electrons 33 Alers-AMC 2004

34 Effect of Stress Gradient: Blech Length Mass flow equation: Flux of Cu atoms Electron force Back diffusion EM Diffusion of Cu High Cu density Critical length at which stress gradient equals EM force Electromigration length ~ µm at typical stress conditions 34 Alers-AMC 2004

35 Increasing Requirements / Decreasing margin As dimensions decrease, critical void volume decreases >> MTTF decreases C.-K. Hu et al., (IBM), IRPS 2004 Requirements on current increase Scaling dimensions >> smaller critical void volume >> Cannot meet current requirements 35 Alers-AMC 2004

36 Controlling Failure Modes Via electromigration: High integrity vias are needed No voids, good profile and coverage Similar issues as via stress migration Interface / bulk electromigration: (CK Hu et al., IRPS 2004) Grain boundary Top Interface Liner Interface Fast diffusion path dominates: SiN (SiC) Interface 36 Alers-AMC 2004

37 Cu / Dielectric Barrier Interface M. Lane et al., (IBM) J. Appl. Phys. 93,, 1417 (2003) Improved Cu / barrier adhesion Pure SiC = CuOx formation (non-hermetic) = poor EM Poor Cu clean = degraded EM Optimum barrier = 20x difference CoWP has best electromigration Can Cu / barrier adhesion be improved more? 37 Alers-AMC 2004

38 Interface Engineering: Cu x Si y Formation M. H. Lin et al., (UMC) IRPS 2004 Cu x Si y layer 2x EM Improvement 10% resistance increase Cu x Si y alloy layer: Good adhesion Shunts current away from interface Increase in resistance from Si in bulk Formation of Cu x Si y layer at interface = improved EM (2x) 38 Alers-AMC 2004

39 Metal Cap Layers C. K. Hu, Appl. Phys. Lett. 84,, 4986 (2004) Single damascene line after electromigration testing Ta / TaN cap Metal cap layers Ta(N), Co(WP), W Advantages: Excellent Cu adhesion Low diffusivity (refractory metal, no EM) Current shunt of void (if thick) Disadvantage: Increased line resistance Additional process Metal cap layers can reduce top interface diffusion 39 Alers-AMC 2004

40 Comparison of Capping Layers C. K. Hu, Appl. Phys. Lett. 84,, 4986 (2004) Ta/TaN Cap ~10x improvement Activation Energy = 1.4eV ~ Cu grain boundary CoWP Cap ~100x improvement Activation energy = 2.4eV Larger than bulk Cu Ea Cobalt is different!! Ta(N) cap layer reduces surface diffusion Co cap is much better than Ta(N), very high activation energy 40 Alers-AMC 2004

41 Cobalt Diffuses into Copper C. K. Hu, Appl. Phys. Lett. 84,, 4986 (2004) Resistance increase with time High current AND low current Not electromigration Diffusion of Co from cap Fit to diffusion equation Resistance increase of ~8% Copper becomes copper alloy Co acts as sacrificial diffuser Improved EM with high Ea Enhanced lifetime of Co due to alloying with Cu Typical thermal budget of a chip: No Co in the Cu 41 Alers-AMC 2004

42 Cu Alloys: Reliability and Resistivity Tonegawa et al. (NEC), IITC 2004 Alloys added to Cu seed layer >> diffusion into bulk of Cu Improved electromigration But: Increased copper resistivity Alloys: Improved reliability at cost of increased Cu resistivity 42 Alers-AMC 2004

43 Increased RC with Cap layers Recessed cap layers increase line resistance (less copper area) 12nm cap, ~120nm deep features (45nm) = 10% increase in line resistance Protruding cap layers increase capacitance (larger sidewall) 12nm cap, ~120nm deep features (45nm) = 5-7% increase in line-line capacitance Remove etch stop layer Requires thick Co layer to act as etch stop (?) Non-oxidizing low k dielectric deposition (?) Higher RC with cap layers 43 Alers-AMC 2004

44 Impact of Reliability on Resistivity Increase in resistivity Additional scattering Grain boundary Surface scattering + 0.5µm-cm at 100nm + 1.2µm-cm at 50nm 2nm barrier: removes copper + 0.2µm-cm at 50nm Alloy elements(10%): + 0.2µm-cm Reliable 50nm interconnects: Effective resistivity increase Small size (big effect) + barrier + alloy = ~3.4 µohm-cm Still less than Al(Cu) 44 Alers-AMC 2004

45 Current Shunting Effect of Barriers C. Bruynseraede,, IEEE Int. Reliability Phys. Symp ( 2004) Reduced line width: Ta/TaN Barrier Metal Larger fraction of line Resistance (Ohms) Barrier can shunt current Failures not catastrophic 5200 More barrier = less Copper Increased line resistance :00:00 55:33:20 111:06:40 166:40:00 222:13:20 277:46:40 333:20:00 388:53:20 444:26:40 500:00:00 555:33:20 t(h:m:s) Increased Barrier / Copper ratio improves EM margin 45 Alers-AMC 2004

46 Scaling Electromigration Requirements: 2X improvement / generation for EM Physics: Reduced lifetime with smaller critical void volume Solutions for collision of physics and requirements Improved dielectric barrier adhesion small improvement Metal cap layer: Increase in RC with cross section change Copper alloys: Increase in resistivity Cost for electromigration improvement = RC increase 46 Alers-AMC 2004

47 Conclusion Via integrity is critical for reliability Barrier process / adhesion / coverage most critical PVD barriers can be extended with resputter ALD layers still have reliability concerns Thick barriers for reliability = increase in resistance Electromigration: solutions exist Increased requirements + smaller volumes = problem PECVD deposited cap layers (pretreatment) Metal cap layers [Ta, W, Co(WP)] Copper alloys Limiter for reducing RC: Reliability 47 Alers-AMC 2004

48 Acknowledgements Members of the Novellus Integration team Bob Havemann, Gary Ray, Bart van Schravendijk, Dan Vitkavage, Greg Harm, Tom Mountsier, Sridhar Kailasam, Chiu Chi, Mahesh Sanganeria, Roey Shaviv, Nao Shoda, Atul Gupta Other contributors from Novellus Systems John Reid, John Sukamto, Michal Danek, Rob Rozbicki University of Texas at Austin Xia Lu, Paul Ho 48 Alers-AMC 2004