6.774 Fall 2006: Global and Local Stress to Enhance CMOS Performance

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1 6.774 Fall 2006: Global and Local Stress to Enhance CMOS Performance techniques have been developed to strain the Si in the MOSFET channel, in order to enhance carrier mobility and current drive some of these approaches involve epitaxial growth of mixtures (alloys) of Si and Ge and of Si, Ge, and C in this lecture we will discuss these materials and stress techniques 6.774, p. 1 Outline Introduction to /Si 1-x Ge x MOSFETs Local ( process-induced ) Strain vs. Global strain ( engineered substrate ) Beyond first generation of strained Si technologies - SSDOI - High-Ge content structures Summary 6.774, p. 2

2 Si and Si 1-x Ge x Crystal Structures Equilibrium (relaxed) Lattices Cubic Si Cubic Si1-xGex Cubic Ge a = Å a Si Si - a Ge mismatch = ~ 4.1% a Si a Ge = Å biaxial compression biaxial tension 1-x Ge x on Relaxed Si (HBTs and some p-channel FETs) on Relaxed Si 1-x Ge x (field-effect transistors) 6.774, p. 3 Effects of Biaxial Tensile Strain on Si Energy Bands: Bulk Case grown on Relaxed Si 1-x Ge x biaxial tension Conduction Band Additional splitting: Band repopulation - reduced intervalley scattering - smaller in-plane effective transport mass Δ 4 Δ 2 [100] μ =q τ m * c [001] [010] Bulk Si Δ 6 E c m t m l mt Δ 4 Δ E s ~ 67 mev/ 10% Ge Δ 2 Single ellipsoid m t < m l Valence Band HH/LH degeneracy lifted at Γ - reduced interband scattering - smaller in-plane transport mass due to band deformation Bulk Si E Γ HH LH Spin-Orbit k E in-plane Δ E s ~ 40 mev/10% Ge out-ofplane k 6.774, p. 4

3 MOS Inversion Layer: Conduction Band J. Welser, et al., IEDM 1994, p. 373 Energy splitting due to strain is additive to field-induced splitting 6.774, p. 5 Surface-channel Strained-Si MOSFET Structures NMOS Welser, et al., IEDM 1994 PMOS Rim, et al., IEDM 1995 Gate high mobility Gate channels Source n+ poly Drain Source n+ poly Drain 120 Å SiO 2 SiO Å o 100 Å p 700 C n 100 Å n+ n+ p+ Strained 5000 Å o Si1-xGex p+ 300 Å p- Relaxed Si 750 C 1-xGex n- Relaxed Si 1-xGex y = x y = x 1.5 μm p- Si 1-yGey Graded Layer o 750 C n- Si 1-yGey Graded Layer y = 0.05 y = 0.05 p+ Si Substrate n+ Si Substrate Graded layer eliminates parasitic buried hole well (true surface-channel PMOS) 6.774, p. 6

4 Energy Band Offsets: /Relaxed Si 1-x Ge x Offsets extracted from MOS C-V analysis From J. Welser, Ph.D. Thesis, Stanford Univ. (1994) Calculations based upon theory from R. People, IEEE J. Quantum Electronics, QE-22 (9), p (1986), and C. G. Van de Walle and R. M. Martin, Phys. Rev. B 34, 5621 (1986) 6.774, p. 7 Strain State of Thin licon Layer: Raman Scattering (521 cm -1 ) J. Welser, Ph.D. Thesis, Stanford Univ. (1994) 514 nm excitation wavelength Raman spectrum shown for as-grown /relaxed SiGe sample 6.774, p. 8

5 Strain State of Silicon After Device Processing: Comparison of Measured Raman Peak Shifts to Theory Δω = x / J. Welser, Ph.D. Thesis, Stanford Univ. (1994) Theory SiGe: Dietrich, et al., J. Appl. Physics 74 (5), p (1993) : Abstreiter, et al., Phys. Rev. Lett 54 (22), p (1985). Δω = x / Relaxed SiGe layers are at least 90% relaxed Strained-Si is pseudomorphic to the relaxed SiGe, and fully strained 6.774, p. 9 Raman Spectrum After Thermal Oxidation No measurable strain relaxation after thermal oxidation (850C,10 min.) similar results obtained for 800C, 40 min. oxidations 6.774, p. 10

6 Effective Mobility (cm 2 / V-sec) V DS = 10 mv NMOS Mobility Enhancements in Strained-Si MOSFETs Measured Room Temperature Characteristics (Welser, IEDM 1994) (Rim, IEDM 1995) Substrate Ge Content, x : CZ Si Control Vertical Effective Field (MV/cm) 0 Effective Mobility (cm 2 / V-sec) increasing strain in Si PMOS V DS = -10 mv 295 K Substrate Ge Content, x : Vertical Effective Field (MV/cm) electron and hole mobilities increase with tensile strain in Si peak mobility enhancement ratios: ~ 1.8X for 30% Ge substrate hole mobility enhancement decreases with increasing Eeff 6.774, p. 11 Mobility Measurements on Industrial Strained-Si MOSFETs Rim, et al., (IBM), VLSI Symp., 2002, p. 98 manufacturing process: STI, CMOS wells, halo implants, raised S/D, 2.2 nm t ox 6.774, p. 12

7 Mobility Enhancements in Surface-channel Strained-Si MOSFETs channel with improved transport properties G S n+ poly D SiO 2 n + n + Relaxed Si 1-x Ge x y = x Si 1-y Ge y Graded Layer y = 0.05 Mobility Ratio: Peak-µ () Peak-µ (CZ Si) Mobility enhancement ratio NMOS Calc. MOS E eff = 0.1 MV/cm (Takagi, JAP 96) Welser, IEDM '92 Welser, IEDM '94 Rim, VLSI '01 Currie, JVST '01 Tezuka, VLSI ' Substrate Ge fraction, x PMOS 2.6 Calculation by Oberhuber et al. 2.4 Rim, et al Currie and Leitz, et al Substrate Ge Content (%) Measured peak mobility enhancement ratios exhibit expected strain dependence Mobility Enhancement Factor 6.774, p. 13 Effective Electron Mobility μ eff (cm 2 /sec V) MOSFET Scaling Challenges: Channel Transport & Universal Mobility Universal mobility 7x x x x10 18 cm -3 ~ 2X Vertical Effective Field E (MV/cm) eff Mobility decreases as channel doping increases Bulk Si MOSFET mobility data from Takagi, et al., TED, 1994 Solution: Strain enables new universal mobility curve 6.774, p. 14

8 Impact of Enhanced Mobility on Drive Current Mobility Enhancement in Channel/Relaxed SiGe n-mosfets v elec. = g mi / C OX (cm/sec) ε OX / C OX = 67 A Epi Si Control L poly (μm) Rim, Hoyt, Gibbons IEDM Intrinsic Transconductance, g mi (ms/mm) 60 Å 130 Å 750 Å 6000 Å 1.5 μm n + LTO Spacer n + poly gate oxide p- p + Si 0.8 Ge 0.2 Punch-through stop p-relaxed Si 0.8 Ge 0.2 p-si 1-x Ge x Graded Layer p + Si Substrate High electronmobility channel n + x = 0.2 x = 0.05 Enhanced-mobility strained Si n-mosfet test structure Biaxial strain increases electron mobility above the universal MOS curve Mobility enhancement of ~ 1.75x persists to high vertical effective fields (>1MV/cm) Mobility enhancements large I d and g m improvements at 100 nm channel length 6.774, p. 15 Misfit Dislocation Formation During Si 1-x Ge x Epitaxial Growth <110> <001> [111] Dislocation spacing, s s Si 1-x Ge x Si Misfit Dislocation Segment thicker epi layer (partially strained) <110> Strained Si 1-x Ge x Plan-view TEM thin epi layer (fully strained) Cubic Si 6.774, p. 16

9 Critical Thickness vs. Ge Content for Si 1-x Ge x on Si Green, et al. 900 C Kasper and Herzog Houghton 500 C Bean, et al. 550 C Noble, et al. 625 C 750 C Lines calculated from kinetic model (Houghton, et al. J. Appl. Phys. 70, 1991) Thickness (nm) 10 3 RELAXED C 550 C C 900 C EQUILIBRIUM (STABLE) Ge fraction, x } METASTABLE 6.774, p. 17 Growth of High Quality Relaxed Si 1-x Ge x (Fitzgerald, et al., J. Vac. Sci. Technol. B 10 (4), 1992) (LeGoues, et al., J. Appl. Phys. 71 (9), 1992) Cubic Si 1-x Ge x Cubic Si y = x y = 0 Si 1-y Ge y Si [111] Misfit Dislocation Threading Arms <001> <110> Grading the Ge content in the buffer layer reduces the threading dislocation density at the surface: Ungradedprofile: > 10 9 cm -2 Graded profile: < 10 5 cm -2 Additional techniques have been developed to improve material 6.774, p. 18

10 Some Materials Issues for Graded Relaxed Si 1-x Ge x Layers on Si Threading dislocation density: decreases for higher growth temperatures, e.g. lower at 900 C compared to 600 C Buried strain field creates cross-hatch : pattern of gentle surface undulations (long period, e.g. 0.1 to 1 μm) Islanding or 3D, non-planar growth increases for higher growth temperatures and steeper Ge grading rates (Ge%/μm) Plan view optical Nomarski micrograph of 20% Ge relaxed layer after defect etching: 4 gm CrO3 in 250 ml H2O and 20 ml of 49% HF Si substrate 6.774, p. 19 Cross Section TEM of Graded Relaxed Si 1-x Ge x Layers 10% Ge Active device region is at surface 30% Ge Si Substrate 20% Ge Si Substrate Si Substrate Some integration issues: Device isolation Silicide formation Dopant diffusion 6.774, p. 20

11 Effective equilibrium diffusivity(cm 2 /sec) Diffusion in SiGe (Data shown for 20% Ge content) Temperature ( o C) Ge M. Griglione et al. n=p=5 x cm -3 P As P. Kuo, et al. B /kT ( ev -1 ) in SiGe: diffusivities of n-type dopants enhanced, B reduced As and B diffusivities comparable in Si 0.8 Ge 0.2 Si Si 0.8 Ge 0.2 Equilibrium, high-concentration diffusion coefficients of dopants (Hoyt, et al., IEDM 2002) 6.774, p. 21 Outline Introduction to /Si 1-x Ge x MOSFETs Local (process-induced) Strain vs. Global strain (engineered substrate) Beyond first generation of strained Si technologies - SSDOI - High-Ge content structures Summary 6.774, p. 22

12 Local Stress: Optimizing Existing Processes for 3D Stress Control C.-H. Ge, et al., IEDM 03 (TSMC) Direction of stress with respect to current flow is important Tensile strain along y (W) believed to be beneficial for N- and P-MOS Effects increase as device is scaled in L and W 6.774, p. 23 Example of Local Stress Technique T. Ghani, et al., IEDM 2003 (Intel) Intel demonstrated large I d (700 to 800 ma/μm) at 90 nm node for p- MOSFETs with selective SiGe in the source/drain regions n-mos I d enhancement ~ 10% PMOS NMOS (biaxial tension) (biaxial tension) 50% μ p enhancement at 1 MV/cm 6.774, p. 24

13 Strain Engineering at 90 nm Many 90-nm and 65-nm technologies are employing some kind of process-induced ( local ) stress to increase current drive Enhancements associated with strain-induced mobility improvement and reduction in series resistance (for SiGe S/D) Emphasis on largely uniaxial strain for p-mosfet PMOS NMOS Recessed SiGe S/D p-mosfet T. Ghani, et al., IEDM 2003 (Intel) Dual-stress liner (Si 3 N 4 ) H.S. Yang, et al., IEDM 2004 (IBM) 6.774, p. 25 Strain Engineering Today Combinations of stressors are being used: Dual-stress liner Stress memory effect Embedded SiGe S/D From, I. Cayrefourcq, et al. ECS Transactions, Vol. 3 (7), Oct. 2006, p Original images from: M. Horstmann, et al. (AMD), Integration and optimization of embedded SiGe, compressive and tensile stressed liner films, and stress memorization effect in advanced SOI CMOS technologies, IEDM 2005, p , p. 26

14 Impact of Device Pitch Stress in channel I. Cayrefourcq, et al. ECS Transactions, Vol. 3 (7), Oct. 2006, p , p. 27 In the Future, Mobility Enhancements Will Depend on How the MOSFET Evolves (or vice-versa) L Must maintain good control of Bulk electrostatics Metal High-K gate Technology solutions: x j, ext Ultra-thin body (UTB) Channel halo Double or triple-gate structures (non-planar) G S oxide Si D oxide Thin body MOSFET 6.774, p. 28

15 Outline Introduction to /Si 1-x Ge x MOSFETs Local (process-induced) Strain vs. Global strain (engineered substrate) Beyond first generation of strained Si technologies - SSDOI - High-Ge content structures Summary 6.774, p. 29 -Directly-on-Insulator (SSDOI) Potential advantages: better performance (as for SOI) eliminates processing and manufacturing issues associated with the thick SiGe layer T. Drake, et al., J. Elec. Mat., Sept Oxide suitable for ultra-thin body transistors that may replace the bulk MOSFET 10 nm-thick strained Si Poly-Si 10 nm strained Si directly on insulator (SSDOI) SiO nm Defected region BOX 30% SSDOI, I. Aberg, et al., VLSI , p. 30

16 Fabrication of SSDOI Using Bond and Etch-Back (Suitable for R&D) Handle Wafer Etch stops Relaxed Si 1-y Ge y Relaxed Si 1-y Ge y LPCVD SiO 2 Relaxed Si 1-y Ge y Relaxed Si 1-y Ge y LPCVD SiO 2 Relaxed Si 1-y Ge y Relaxed Si 1-y Ge y Si 1-x Ge x grade Si 1-x Ge x grade Si 1-x Ge x grade CZ Silicon (p-) CZ Silicon (p-) CZ Silicon (p-) Si 1-x Ge x grade Relaxed Si 1-y Ge y Relaxed Si 1-y Ge y LPCVD SiO 2 Handle Wafer x ~ 22% Relaxed Si 1-y Ge y Relaxed Si 1-y Ge y LPCVD SiO 2 Handle Wafer ( 30% SSDOI started on 30% Ge layer) LPCVD SiO 2 Handle Wafer Final SSDOI structure 6.774, p. 31 Enhanced Thermal Stability of SSDOI Δ Unstrained Si Raman Intensity No RTA 600C 10 sec 800C 10 sec 950C 1 sec Silicon SSDOI T.S. Drake et al., ICSI3, Santa Fe, Mar See also: T. Langdo, et al., 2002 IEEE SOI Conf., p. 211 K. Rim, et al. IEEE IEDM, p. 49, Wavenumber (cm-1) No change in strain (Raman shift Δ) upon thermal annealing of SSDOI Absence of SiGe: eliminates diffusion issues and inhibits dislocation formation 6.774, p. 32

17 Electron Mobility in SSDOI I. Aberg, et al., VLSI 2004 Effective Mobility (cm 2 /Vs) 1200 NMOS 30% SSDOI, ~15 nm % SSDOI, ~18 nm 96% % % SOI * Effective Electric Field (MV/cm) * Universal Mobility S. Takagi et al., IEEE TED 41, p. 2357, 1994 Electron mobility enhanced by 80% compared to Universal Mobility same enhancement as observed for strained Si/SiGe 6.774, p. 33 Hole Mobility in SSDOI Effective Mobility (cm 2 /Vs) PMOS 127% * 40% SSDOI, 6 nm 30% SSDOI, 8 nm 54% 15% SOI, 12 nm Effective Electric Field (MV/cm) Large enhancements, even for thin silicon films * Universal Mobility S. Takagi et al., IEEE TED 41, p. 2357, , p. 34

18 Effective Mobility (cm 2 /Vs) 1000 /Si Ge (Rim) 1-x x 28% Ge 13% Universal (Takagi) Can t Do it All Electrons (a) NMOS Holes Hole mobility is still significantly below electron mobility (all strained Si techniques) Introduction of new materials: Strained-SiGe alloy channels (b) PMOS (Ghani) 100 Universal (Takagi) (Rim) Si-channel Vertical Effective Field (MV/cm) Vertical Effective Field (MV/cm) 6.774, p. 35 Effective Hole Mobility (cm 2 /Vs) Extremely High Hole Mobility in Ge-Channel p-mosfets Universal (Takagi) dual-channel (Ghani) (Rim) Si-channel (b) PMOS 100/50 (Lee) 80/50 (Leitz) 60/30 (Jung) Vertical Effective Field (MV/cm) (tension) (compression) 0.4 Ge 0.6 Relaxed Si 0.7 Ge 0.3 buffer Graded SiGe Si substrate dual-channel hole moblities much larger than for other technologies largest gain for strained Si/strained Ge on 50% SiGe substrate (2x electron mobility, 10x hole mobility, compared to unstrained Si) 6.774, p. 36

19 Tensile Si/Compressive SiGe Dual-Channel Heterostructure Enhanced electron and hole mobilities achievable for strained Si/SiGe dual-channel MOSFETs Nearly symmetric currents for n- and p-mosfets V T tunable by varying strain and Ge fraction 60/30 Structure Drain Current (ma) Long-channel MOSFETs Si N/PMOS Jung el al., SiGe NMOS (Tsi=4.6nm) EDL Vg-Vt=1,2V 2003 SiGe PMOS (Tsi=1.6nm) Drain Voltage (V) this example ~ 2x NMOS, ~ 3X PMOS current increase (Tsi) 0.4 Ge 0.6 (12nm) Relaxed Si 0.7 Ge 0.3 buffer Graded SiGe Si substrate E v E c 6.774, p. 37 Epitaxial Layer Growth 70/50 MOS Capacitor TiN gate 60/30 structure oxide (2.8 nm) SiGe (70% Ge) - Strained SiGe (50% Ge) - Relaxed Applied Materials Epi Centura Low Pressure CVD System (MIT MTL) 1-y Ge y Relaxed Si 1-x Ge x Graded SiGe 450 to 600ºC 450ºC (0.7 < y < 0.9), 365ºC (Ge) 900ºC, in-situ doped, n-type Si substrate 6.774, p. 38

20 Effective Mobility (cm 2 /Vs) Dependence of Hole Mobility on Ge Fraction nm (Ni Chleirigh, et al., MIT, ECS Trans. Vol. 3 (7), Oct. 2006, p 963.) 7nm Si Cap y=1 (Ge), t=6 nm y=0.8, t=9 nm Mobility Enhancement 200 Si Control N inv cm -2 Enhancements of 5X to 8X achieved for channel Ge fractions y between 0.8 and 1.0 (pure Ge) Mobility enhancement decreases at higher N inv as carriers move into the 7 nm-thick Si cap (can eliminate this with ~ 1.5 nm-thick Si cap) y=1 (Ge), t=6 nm nm y=0.8, t=9 nm Inversion in Si cap N inv cm -2 Gate Oxide 7 nm Si (Strained) ~7 nm Si 1-y Ge y (Strained) Si 0.6 Ge 0.4 (Relaxed) Graded SiGe t 6.774, p. 39 Evolution of Engineered Substrates Bulk 0.4 Ge 0.6 Si Si Relaxed Si 0.7 Ge 0.3 Si 1. Si bulk 2. strain-si/sige bulk 3. Dual channel high mobility, degraded SS and thick relaxed SiGe 0.5 Ge 0.5 SOI Si oxide Si 4. SOI 5. SSOI and SSDOI Si oxide HOI 60 on 30 (combines benefits of dual-channel with fully-depleted SOI) 6.774, p. 40

21 Strain in Ultra-thin SiGe Channel HOI (55/25) Intensity (cps) λ = 442 nm t SiGe =4 nm 6 nm 10 nm I. Aberg, et al., (MIT) IEEE TED, May 2006 (y) Si substrate gate oxide Si 1-z Ge z Raman Shift (cm -1 ) 5 nm strained-si (55% Ge) 4 nm strained-sige compression 4 nm strained-si BOX tension Raman analysis indicates strain is maintained in Si and SiGe after layer transfer and MOSFET fabrication (T max ~ 800ºC, 10 s) 6.774, p. 41 SSDOI and HOI MOSFETs I. Aberg, MIT Effective Mobility (cm 2 /Vs) gate (y) BOX 25% SSDOI gate (y) 1-z Ge z (y) BOX NMOS Effective Mobility (cm 2 /Vs) 600 HOI % SSDOI 400 SOI 1.8X X 200 t SiGe =10nm SOI t SiGe =6 nm t cap =5 nm Electron Density (x10 13 cm -2 ) Hole Density (x10 13 cm -2 ) HOI: high hole mobility at all N inv (combined with electrostatics of thin body SOI) SSDOI attractive for NMOS and HOI for PMOS E V E C Variable Si cap thickness, t cap 10 nm SiGe 4 nm bottom Si 55/25 HOI, t SiGe =10 nm, t cap =2.8 nm PMOS 6.774, p. 42

22 D R for s-si/relaxed SiGe (cm 2 /sec) Thermal Budget Constraints: Interdiffusion at /Relaxed SiGe Interfaces G. Xia, Ph.D. Thesis (MIT), June 2006 Symbols: D extracted from shoulder profile by B-M analysis 920C 880C 840C D R ( x Ge + 0.1) 2. 2 X D R ( x Ge ) 800C x Ge Lines: D from R peak fitting Ge fraction C 13 hr as-grown SIMS annealed SIMS Tsuprem4 peak fitting A Depth (A) 4.66eV D R xge) = 310exp(- )exp(8.1* x kt ( Ge ) Ge diffusivity at /SiGe interface increases exponentially with Ge % 6.774, p. 43 Si-Ge Interdiffusion: the Role of Compressive Strain in the SiGe G. Xia, et al., Appl. Phys. Lett., Jan Compressive 56/30 D in TSuprem4 (cm 2 /s) C 2hr D that best fits strained 56/30 SIMS D Relaxed X Ge Dramatic enhancement in interdiffusion at Si/SiGe interface for SiGe layers under compressive strain Trade-off between enhanced mobility (high strain) and Si/SiGe interdiffusion (low strain) Ge fraction Ge fraction C as-grown 0.5 2hr annealed Tsuprem4 0.4 fitting Depth A (A) Relaxed 56/56 800C 2hr Depth A (A) 6.774, p. 44

23 Thermal Budget Constraints: Ge Profiles After RTA SIMS profiles after 10 sec RTA [Ge] in SiGe (%) ºC 950ºC Initial profile 50/25 HOI I. Aberg, IEEE 2004 SOI Conf. Si SiGe Si Depth (nm) 10 s RTA at 950ºC peak Ge decreases by 10 atomic % this will result in poorer hole confinement and lower mobility 6.774, p. 45 Summary Strain enables enhanced transport: Local, global and combined techniques SSDOI attractive as a drop-in for SOI PDSOI today or FDSOI in future Higher Ge content structures are promising: strained SiGe channel for p-mos strained Si channel for n-mos feasible in a single epi layer stack ( dual-channel ) Heterostructure on insulator (HOI): New opportunities and challenges Solutions will involve epitaxy (S/D, channel, and in strained substrate fabrication) 6.774, p. 46