EE 432/532 Field oxide CyMOS process Jan. 24, 2017

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1 EE 432/532 Field oxide CyMOS process Jan. 24, 2017 Group 5 Trevor Brown Michael Miller Xi Zhu David Orona 1. Overview Lab instructor Le Wei An electronic wafer is a thin slice of semiconductor material used in the fabrication of various types of basic electrical components, including BJTs, MOSFETs, and logic gates. In order to achieve these functions, however, an oxide field must be established in order to create the opportunity for gate lithography and diffusion. Therefore, the goal of this lab is to create a known thickness layer of oxide on the wafers utilizing cleaning and heating applications. 2. Starting wafers Lot ID: Orientation: <100> +/- 1 Diameter: 3 Dopant: N/Ph Thickness: μ m Device wafers: 4 Resistivity: 1-10 Ω*cm Test wafers: 4 Figure #1: Starting wafer parameters (based off the contents of the wafer packaging) 3. Standard Clean In essence, the purpose of the standard clean procedure is to help promote the functionality of the wafer(s). By cleaning any debris, dust, or prints that occur upon the device with this method, chances increase in having a successful product output. This practice alone, though, does not ensure total success, as all other processes must have correct implementation. The cleaning process, when simplified, can be broken down in four essential nodes: the set up, the clean, the drying, and the clean up. Using the indicated illustration below, a rudimentary setup of the left and right basins is established.

2 Figure #2: Left and Right Tub Setup Of course, the image does not contain all of the specific details. For instance, between each addition to the respective tub, the 1000 ml graduated cylinder must be properly rinsed to avoid cross-contamination issues. Similarly, the temperature controllers and cascade rinse are not exactly established as to how they turn on and when. However, the main focus is on the above chemical configuration. Following the pronounced methodology in Figure #2, the cleaning process is a straightforward design that relies on systematic implementation with respect to the basins. To put simply, the wafers are submerged and allowed to develop in the following sequence: Figure #3: Cleaning Process Much like the initial setup procedure, several setup were oversimplified and lacking in detail. The technical heating conditions and proper nitrogen feeds to the cascade rinse are more than evident of this notion. However, the notion still stands. The wafers react to the allotted solutions they are immersed, clear all miscellaneous particles or levels undesired, and emerge contaminant-free, ready to take on any new oxidation levels. The remaining actions involve inserting the wafers into a spin/rinse mechanism for a complete dry while at the same time cleaning up the mess created by the previous instructions. There is not too much detail involved, though it is important to dilute the solutions with an amount of NH 4 OH for a safe, neutral liquid for draining.

3 4. Wet Oxidation With a clean wafer at hand, the wet oxide process begins by setting the oven temperature to 800 C. Dry nitrogen is likewise applied into the furnace at the rate of 1.0 slpm. The wafers are then placed into the established boat and are slowly pushed to the center of the furnace (1 inch per 12 seconds). The furnace soon rises up to the proper temperature, wherein the deionized water bubbler is started with nitrogen gas application. The bubbler is heated to 98 C. It is then switched off and the bubbler steam mixture is piped into the furnace tube. Once the desired time is reached, the bubbler can then be turned off and the furnace can be ramped down. With the tube temperature at 800 C or less, the boat is slowly removed. The wafers can eventually be removed after several minutes of cooling. 5. Results The first thing that the group did in lab was to measure the resistance of the varying test wafers. This was done by measuring the voltage at four different currents Then, using the equation V=IR, the impedance was discerned. The respective currents and the voltages for the wafers can be found in the table below: Test Wafer 1 Test Wafer 2 Test Wafer 3 Test Wafer 4 I(mA) V(mV) I(mA) V(mV) I(mA) V(mV) I(mA) V(mV) Figure #4: Current and Voltage Measurements As mentioned, the resistance was determined by finding the resistance at each current level and then taking the average. This gave us a average resistance of Ω for TW1, Ω for TW2, Ω for TW3, and Ω for TW4. The Filmetrics device (or spectroscope) is a tool that, with proper calibration, can measure the thickness of a wafer along with any oxide on its surface. It does so through the magic of sending a wave signal through a laser, bouncing it off the wafer s gleaming surface, and receiving the same signal back, marking the time elapsed in the

4 process. From there, a thickness calculation can be discerned. This can be extremely vital as we continue to grow and dissolve different layers of oxidation. The primary basis of the system revolves around the equation depicted below. With t 1 and t 2 designated as transmission coefficients, the program works to define a t ox value that best fits the nature (i.e. the R 2 value) of the corresponding reflection graph. The determined t ox is then output to the user. Implementing the spectroscope on our Test Wafer #1 (TW1), the team decided to approach it using a wafer map technique, measuring 16 unique points on the individual wafer to form a more diverse thickness model. Figure #5: Wafer map measurements Using direct, center-point measurements on the remaining test wafers, it is interesting to note that TW1, with its wafer map implementation, holds a considerably higher thickness rating as compared to the rest (see Figure #6). This may go to denote the accuracy of using multiple measurements. TW1 (average) TW2 TW3 TW4 Oxide Thickness 3850 Å 3774 Å 3700 Å 3692 Å Figure #6: Thickness readings as measured by Filmetrics

5 When measuring the thickness on the wafers, particularly for test wafers #2 through #4, the spectroscope constantly declared?? on many of the team s findings. This is a designation of improper signal registration. Whether it be due to some debris on the wafer or tampered blocking the scope s light emitter, the signal ultimately did not get through very well and provided untrustworthy results. Though this was later fixed by reset of the machine, there is still the possibly the latter three thicknesses are WAY off, hence the varying nature. 6. Appendix Determining the time for the designated thickness: B...where A and B for the wet oxidation equate to: Based on the above conditions, the only parameter needed to be resolved is the B time element. In order to achieve that, A and B must be distinguished, which thereby implies the knowing the temperature variable T. Since we know T = 800 C due to the furnace ramp up, the time can be determined.

6 CyMOS process Spring 2016 Iowa State University Start Date: 11/24/2017 Starting Material Orientation: <100> +/- 1 Dopant: N/Ph Resistivity: 1-10 Ω cm Doping Concentration: cm 3 Diameter: 3 inch Thickness: μm Lot Identification: Wafer Count Device wafers: 4 Test wafers: 4