STUDY ON HIGH MOBILITY CHANNEL. TRANSISTORS FOR FUTURE SUB-10 nm CMOS TECHNOLOGY

Transcription

1 STUDY ON HIGH MOBILITY CHANNEL TRANSISTORS FOR FUTURE SUB-10 nm CMOS TECHNOLOGY FEI GAO NATIONAL UNIVERSITY OF SINGAPORE 2007

2 STUDY ON HIGH MOBILITY CHANNEL TRANSISTORS FOR FUTURE SUB-10 nm CMOS TECHNOLOGY Fei GAO (B. Eng, Xi an Jiaotong University, PR CHINA) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2007

3 Acknowledgements Upon completion of this thesis, as I retrospect my four years research life in SNDL, I realize there are indeed many people to thank. I would like to thank: My supervisors, Dr. Lee Sungjoo (NUS) and Dr. Subramanian Balakumar (IME) for their effective guidance during the past four years; their knowledge, insights and ideas are critical to the successful completion of my PHD research. Their fresh thought and creative thinking always inspire me when I was lost in direction. My deepest thanks and heartfelt appreciation are always with them. Prof. D.L. Kwong (IME), A/P. B.J Cho (NUS), Dr. D.Z. Chi (IMRE), Dr. N. Balasubramanian (IME), Dr. G-Q Lo (IME) and Prof. C.W. Liu (National Taiwan University) for their insightful comments and fruitful discussions during the course of my research; their professionalism also impresses me greatly; Mr. C.H. Tung (IME), Dr. A. Jay (IME), Dr. C.K. Chia (IMRE), Dr. T. Sudhiranjan (IMRE), Dr. J.S. Pan (IMRE), Dr. Y.-L. Foo (IMRE), Dr. A. Du (IME), and Mr. L.J. Tang (IME), for their help in setting up the experiment and analyzing experimental results; their easily comprehensible illustrations have greatly broadened my horizon and their dedication to science is hard to forget. My collaborators Li Rui, S.J. Whang, and H.B. Yao for their assistance in experiment; I can still recall vividly those sleepless nights we spent together in SNDL. I want to extend my gratitude to many other staff & students in SNDL, IME and IMRE, who had helped me in processing my samples, carrying out analysis, or in other formats, my sincere thanks go to them and I wish them all the best in future. Finally, I would like to express my deepest love to my parents for everything they provided. I

4 TABLE of CONTENTS Acknowledgements Table of Contents Abstract List of Tables List of Figures List of Symbols I II VI VIII IX XIV Chapter 1: Introduction Introduction MOSFET Scaling Scaling Trend Requirements for Further Scaling Challenges for Scaling Approaches for Further Scaling High-k and Metal Gate Innovative Device Structure Advanced Channel Material Summary Thesis Organization Reference Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application 25 II

5 2.1 Surface Passivation for Ge Introduction Experiment Results and Analysis Passivation Gate Stack TEM C-V and I-V Characteristics Gate Stack Thermal Stability Effect of AlN Thickness Scalability Ge MOSFET with AlN Passivation Conclusion Surface Passivation for GaAs Introduction Experiment Results and Discussion Surface Cleaning Effect Surface Morphology PN Surface Treatment AlN Surface Treatment Electrical Characteristics TEM of Gate Stack Thermal Stability GaAs n-mosfet with AlN-HfO Conclusion Summary Reference Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate Introduction SPE to Form Localized GOI Concept of Localized GOI Formation Experiment III

6 3.2.3 Results and Discussion Seed Region Analysis GOI Structure Conclusion Condensation of amorphous SiGe Film on SOI Substrate to form SGOI Condensation Mechanism Experiment Results and Discussion Amorphous SiGe layer on SOI Crystal Quality and Composition of SGOI XRD strain analysis of SGOI Cyclic Anneal Effect Conclusion Summary Reference Chapter 4: High Mobility Channel MOSFET Integrated with Highk/Metal Gate and Schottky S/D Introduction High Mobility Channel MOSFET Integration Schottky S/D Transistor Schottky S/D MOSFET on Si 0.05 Ge 0.95 /Si Substrate Experiment Results and Discussion Gate Stack Performance of Long Channel MOSFET Performance of Short Channel MOSFET Conclusion Schottky S/D MOSFET on thin SGOI substrate SGOI substrate and Transistor Structure Gate Stack and S/D TEM Transistor Characteristics Conclusion Summary IV

7 Reference Chapter 5: Conclusion Conclusion Surface Passivation for Ge and GaAs GOI and SGOI fabrication Schottky S/D transistor Recommendations Reference List of Publications V

8 Abstract Driven by consumers demand for IC (Integrated Circuits) chips with higher performance but lower cost, the dimension of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been scaled continuously, following the Moor s law. However, further scaling of conventional MOSFET with poly-si/sion/si-substrate structure is approaching its physical limits: intolerable high gate leakage current, undesirable poly-si gate depletion and difficulties in controlling the short channel effects. MOSFET made on high mobility channel materials, such as Ge and GaAs, with high-k/metal gate stack, is a possible alternative to extend the Moor s law. Hence, in this thesis, several technical aspects regarding the high-mobility channel MOSFET are explored. High quality gate stack is critical for high performance Ge and GaAs MOSFET. It was found that the surface oxidation of Ge and GaAs substrates during the high-k deposition should be avoided since the formed oxides would cause the dysfunction of the MOS devices. Hence, surface passivation using thin sputtered AlN film on both Ge and GaAs substrates, prior to the deposition of high-k, is proposed and investigated. XPS (X-Ray Photoelectron Spectroscopy) analysis confirms the role of AlN in preventing the substrates from oxidation, resulting in excellent Ge and GaAs MOS devices. Besides, PN (Plasma Nitridation) surface treatment on GaAs substrate is applied. With optimized nitridation process, excellent GaAs MOS capacitors are realized. Excellent thermal stability of the aforementioned passivation methods is also confirmed by thermal stress tests. Subsequently, Ge and GaAs MOSFETs with AlN passivation and HfO 2 /TaN gate stack are also demonstrated. VI

9 For highly scaled MOSFET fabrication, high mobility on insulator structure is more desirable than bulk substrate, due to its better immunity to short channel effects, reduced parasitic junction capacitance and free of latch-up. Methods of realizing localized high mobility channel on insulator structure and cost effective approaches are always attractive for integration and commercial purpose. By using Ge SPE (Solid Phase Epitaxy) lateral growth at 800 o C on pre-patterned Si substrate, localized GOI (Germanium on Insulator) structure on Si substrate is fabricated. Besides, strained high-ge concentration SGOI is successfully demonstrated by two-step oxidation of sputtered low Ge content α-sige (amorphous SiGe) on a SOI substrate. Compared with conventional condensation approach, this novel condensation method is not only cost effective but also process simple. Finally, an integration scheme for Ge and SiGe (with high Ge percentage) MOSFET with HfO 2 /TaN gate stack is proposed by using Schottky S/D (Source/Drain) rather than the conventional doped S/D. The metallic Schottky S/D with low formation temperature can overcome several sever technical issues facing the doped S/D in these channels: low dopant solubility, insufficient dopant activation, dopant loss and Ge out-diffusion into the high-k at high temperature dopant activation process. Ni-germanide Schottky S/D p-mosfet with 85% hole mobility enhancement over the universal hole mobility was realized on Si 0.05 Ge 0.95 /Si substrate with HfO 2 /TaN gate stack. Besides, thin-s 0.35 G 0.65 OI Schottky S/D transistor, one of the promising non-classical architectures for future CMOS application, was demonstrated using a self-aligned top gate process. VII

10 List of Tables Table 1.1 HP, LSP and LOP Logic Technology Requirements (MPU: Microprocessor Unit; EOT: Equivalent Oxide Thickness; J g,limit : Gate Leakage Current Density Limit.) Table 1.2 Properties of semiconductor materials: Si, Ge, GaAs, InAs, InP, and InSb (μ electron : Electron Mobility; μ hole : Hole Mobility) Table 2.1 Top surface roughness RMS values measured by AFM within an area of 5 μm by 5 μm after different process steps Table 2.2 Interface state density (D it ) estimated by conduction method for TaN/HfO 2 /GaAs stack with different passivations Table 4.1 Comparison between this work and previous works regarding the characteristics of Schottky S/D and conventional MOSFETs; L g is gate length, I d is drain current and I on / off is on/off ratio VIII

11 List of Figures Figure 1.1 Figure 1.2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Figure 2.9 Technology and feature size versus year; the inset is transistor cost versus year [9] J g, limit and J g, sim for HP, LSP and LOP logic devices XPS analyses: (A) Ge 3d spectra for SN sample after DHF cleaning, SN and HfO 2 deposition; (B) N 1s spectra for SN sample after annealing in NH 3 at 600 ;(C) Al 2p spectra for AlN sample before and after HfO 2 deposition; (D) Ge 3d spectra for both SN and AlN samples after HfO 2 deposition TEM image of TaN/HfO 2 /Ge gate stack with AlN-passivation (A) Measured high frequency C-V and simulated low frequency C-V for AlN sample and measured high frequency C-V for SN sample; (B) shows the gate Leakage current density versus gate voltage EOT and gate leakage current density at V g -V fb =1V for both AlN and SN sample after different post annealing conditions Measured C-V characteristics from Ge capacitor with different AlN passivation thickness and high-k HfO 2 thickness. Although 0.5 nm AlN is thick enough to protect the Ge surface from being oxidized when depositing thin 2 nm HfO 2 ; stretch-out of C-V curve is observed with HfO 2 thickness increased to 3.5 nm, implying the surface oxidation of Ge Gate leakage density (normalized at V g -V fb =1V) as a function of EOT for AlN X /HfO 2 on Ge substrate and HfO 2 on Ge substrate with conventional SN treatment. (The leakage data for HfO 2 on Ge substrate with SN treatment is from reference [14].)As a reference, the leakage current from SiO 2 on the Si substrate is also included. All the leakages are from n-type substrates Typical as-measured inversion C-V characteristics for Ge p-mosfet with 1nm-AlN X /4nm-HfO 2 gate dielectric. The inversion side capacitance corresponds to an EOT of 2.05 nm (A) I s -V g characteristics of Ge p-mosfet with AlN X /HfO 2 gate dielectric. Sub-threshold swing as low as 82 mv/dec is obtained; (B) I s -V d curves for Ge p-mosfet with AlN X /HfO 2 gate dielectric Hole mobility of the Si and Ge p-mosfets with AlN or SN passivation, Ge MOSFET with thin-aln/hfo 2 passivation shows 20% and 40% increase over the mobility of Si and Ge p-mosfet with SN/HfO 2, IX

12 respectively Figure 2.10 Measured I s -V d output characteristics for Ge n-moseet with AlN- HfO 2 /TaN at gate bias from 0 to 2V Figure 2.11 Structure for GaAs MOS capacitors with different pre-gate cleaning and passivation techniques integrated with high-k/metal gate Figure 2.12 XPS analysis of GaAs surface before and after DHF and HCl pre-gate cleaning: (A) Ga 3d spectra and (B) As 3d spectra. The spectra indicate both pre-gate cleaning methods are effective in removing the native oxides in GaAs surface Figure 2.13 C-V characteristics for Si-passivated GaAs capacitor with 5nm-HfO 2 /TaN gate stack using HCl and DHF pre-gate clean. The inset is the gate leakage current Figure 2.14 AFM surface image on HfO 2 /GaAs stack with DHF clean and AlNpassivation, smooth surface with no detectable damaged was noted Figure 2.15 (A) XPS N 1s core level region of the GaAs surface after PN process, (B) is XPS As 3d core level region of the GaAs surface before and after PN process; (C) XPS Ga 3d core level peak before and after nitridation, and after DHF etching of the nitride layer for 10 minutes Figure 2.16 High-frequency C-V characteristics of TaN/HfO 2 /GaAs stack with different plasma nitridation processes (time and temperature) Figure 2.17 (A) Ga 2p XPS spectra for GaAs after DHF clean and after ALD HfO 2 deposition with and without AlN-passivation; (B) Peak separation for Ga 2p signal from the sample without passivation after ALD HfO 2 deposition; (C) Peak separation for Ga 2p signal from the sample with thin AlN passivation after ALD HfO 2 deposition; (D) As 3d XPS spectra for GaAs after DHF clean and after ALD HfO 2 deposition with and without AlNpassivation Figure 2.18 C-V curves of both TaN/HfO 2 /p- & n-gaas stack using PN, AlN- and Sipassivation techniques. EOT is indicated in the figure Figure 2.19 Flat band voltage extracted from TaN/HfO 2 /GaAs stack using PN, AlNand Si-passivation techniques, the theoretical V fb is also plotted as reference Figure 2.20 Gate leakage current density as a function of EOT for TaN/HfO 2 /GaAs stack. Reported results for HfO 2 /Si, HfO 2 /Ge and SiO 2 /Si are compared.-53 Figure 2.21 TEM pictures of TaN/HfO 2 /GaAs stack with (A) plasma nitridation (B) X

13 AlN-passivation, and (C) Si-passivation Figure 2.22 Figure 2.23 EOT and gate leakage current density after thermal tests for TaN/HfO 2 /GaAs capacitor with Si passivation TEM and EDX of the GaAs sample with Si passivation after PMA 850 o C anneal, EDX shows diffusion of Ga and As into HfO Figure 2.24 Normalized C-V characteristics for TaN/HfO 2 /GaAs stack with Sipssivation after post-metal annealing Figure 2.25 (A) Normalized C-V characteristics for TaN/HfO 2 /GaAs stack with PNpassivaiton, and (B) Normalized C-V characteristics for TaN/HfO 2 /GaAs stack with AlN-passivation; inset is gate leakge currenty density Figure 2.26 Frequency dispersion after FGA at 600 o C for 10 minutes for TaN/HfO 2 /GaAs stack with (A) Si-passivation and (B) AlN-passivation.-59 Figure 2.27 Junction current versus the voltage applied at N + side of N + P GaAs junction; a two-step Si and P co-implantation is used and the activation temperature is 750 o C; a I forward /I reverse ratio of 10 7 is achieved Figure 2.28 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 (A) I s -V g of GaAs n-mosfet, (B) I s -V d of the GaAs n-mosfet Concept of using SPE lateral growth to form localized GOI structure, the open window on the Si substrate is called seed region where the epitaxial growth of Ge will be initialized Process flow for SPE GOI growth, (A) a layer of SiO 2 was grown by thermal oxidation; (B) selective etch of SiO 2 to open seed windows; (C) a layer of Ge was deposited by DC sputtering and covered by a layer of SiO 2, followed by thermal annealing XRD intensities versus 2θfrom the seed area from three samples annealed at different conditions: FA at 800 for 2 hours, FA at 600 for 2 hours, RTA at 940 for 4 seconds (A) HRTEM picture of the sample annealed at 600 for 2 hours, inserted plot is the SAD pattern. (B) HRTEM picture of the sample annealed at 800 for 2 hours (A)High resolution TEM picture of single crystal GOI structure. (B) SAD pattern indicates that the Ge film on insulator is single crystal Process for condensation of amorphous SiGe on SOI wafer to form single XI

14 crystal SGOI substrate:(a) a amorphous low Ge content SiGe layer was deposited on a SOI wafer; (B) after high temperature oxidation process, due to condensation, SPE mechanisms, high Ge concentration single crystal SGOI was formed between the BOX and top SiO 2 layer; (C) top SiO 2 layer etch Figure 3.7 Figure 3.8 Figure 3.9 Auger depth profiling of the as-deposited sample before any oxidation process; the inset (A) illustrates the structure of the sample High resolution TEM of the S 0.4 G 0.6 on insulator structure achieved after two step oxidation process. Inset (A) shows the twin defect observed in the SGOI, and inset (B) represents FFT image of the SGOI film Raman spectra from the as-deposited sample and the sample after two-step oxidation; much narrower Raman modes associated with Si-Si, Si-Ge, and Ge-Ge vibration peaks reveal high crystalline quality Figure 3.10 XRD scans of SGOI sample after two-step oxidation process. The Si and SiGe diffraction peaks are used for Ge composition estimation Figure 3.11 Temperature profile for the cyclic anneal process for SGOI substrate, two cycles are shown in the graph Figure 3.12 High resolution TEM of the S 0.4 G 0.6 on insulator structure after cyclic Thermal treatment; no twin defect is observed in the SGOI film as shown in inset (A); inset (B) represents an FFT image; and diffraction pattern of the SGOI film shown in inset (C) reveals single crystalline phase Figure 3.13 Figure 3.14 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Raman Analysis showing that the strain in SiGe on insulator is maintained after the cyclic anneal Thin SGOI achieved with thickness of 20 nm The structure of the Schottky S/D transistor, the S/D is a Schottky contact (A) band diagram for p-mosfet, and (B) band diagram for n-mosfet [11, 12] (A) TEM picture of the Si 0.05 Ge 0.95 /Si substrate, the Ge concentration is detected by EDX, (B) High resolution TEM shows the interface between the Si-sub and epitaxially grown SiGe layer, arrows point out the misfit dislocation. However, the top SiGe layer is believed of high-quality single crystal, which is also verified by gate stack TEM (Figure 4.6) Illustration of photoresist trimming process in O 2 plasma (A) photoresist XII

15 after develop has a length of L, defined by the mask; (B) The photoresist is encroached by O 2 plasma in both vertical and horizontal directions; (C) Photoresist with smaller length L is achieved Figure 4.5 (A) Excellent inversion C-V curve of the Schottky S/D transistor, low gate leakage current density is also demonstrated in (B) Figure 4.6 high resolution TEM of the gate stack from the Ni-Schottky S/D p- MOSFET which shows high interface quality. HfO 2 high-k dielectric remained amorphous. The clear lattice image of the channel indicates the high quality of the Si 0.05 Ge 0.95 top layer Figure 4.7 Figure 4.8 Figure 4.9 Figure 4.10 Typical I s -V d characteristics measured from the Ni- Schottky S/D transistor fabricated on the Si 0.05 Ge 0.95 /Si substrate with a gate length of 20 μm Effective hole mobility μ hole versus the effective electric field E eff. ~1.8X times peak hole mobility from Ni-Schottky S/D MOSFET on Si 0.05 Ge 0.95 /Si is demonstrated compared to universal hole mobility form Si p-mosfet SEM top image of the Ni-Schottky S/D transistor after the photoresist trimming and formation of the nitride spacer, it indicates that the gate length is 97 nm (A) I s -V d curves from short channel Ni-germanide Schottky S/D PMOSFET; (B) I s -V g curves from short channel Ni-germanide Schottky S/D PMOSFET; Figure 4.11 High resolution TEM image of the SGOI wafer prepared by oxidation of amorphous SiGe on SOI wafer. The thickness of the body is ~30 nm and the Ge atomic concentration detected by EDX is 65% Figure 4.12 Schematics of device cross-sectional structure of SGOI MOSFET with Schottky S/D and HfO 2 /TaN gate stack Figure 4.13 TaN-HfO 2 -Si 0.35 Ge 0.65 gate stack and S/D area of the fabricated thin SGOI Schottky S/D transistor, the composition of the S/D area is determined by EDX analysis Figure 4.14 Inversion capacitance-voltage curve of the fabricated Schottky SGOI p- MOSFET. The inset shows the gate leakage current density versus the gate voltage when the Si 0.35 Ge 0.65 channel is under inversion Figure 4.15 I d /I s -V g characteristic for the SGOI Schottky S/D p-mosfet transistor with a gate length of 5μm XIII

16 List of symbols a Ge a Si lattice constant of Germanium lattice constant of Silicon a Si1-xGex C C inv C ox D it E g E eff g d I d I off I on J g J junction I s k k high-k K L N D N A N i lattice constant of Si 1-x Ge x capacitance density inversion capacitance density oxide capacitance density interface state density band gap of semiconductor effective electric field drain conductance drain current of MOSFET off current of MOSFET on current of MOSFET gate leakage current density junction current density source current of MOSFET relative permittivity permittivity of high-k dielectric Boltzmann s constant channel length of MOSFET donor concentration acceptor concentration intrinsic carrier density XIV

17 q Q n Q b t t high-k electronic charge inversion charge density bulk charge density dielectric thickness thickness of high-k gate dielectric t SiO2 thickness of SiO 2 T μ μ electron μ hole μ eff V fb V g V t W W m W s V d temperature carrier mobility electron mobility hole mobility effective mobility flat band voltage gate voltage of MOSFET threshold voltage of MOSFET channel width of MOSFET work function of metal work function of semiconductor drain voltage ε SiO2 relative permittivity of SiO 2 ε 0 χ Φ b Φ n Φ p vacuum permittivity electron affinity Schottky barrier height electron barrier height hole barrier height XV

18 Chapter 1: Introduction Chapter 1 Introduction 1.1 Introduction It is regarded by many that semiconductor technology is the foundation of IT (Information Technology) revolution. The scale of the semiconductor industry has reached hundreds of billions of dollars, with the estimation that it will account for 2.6% of the world GDP by the year of 2010 [1]. Successful fabrication of the world s first transistor in Bell Lab by Bardeen, Brattain and Shockley in 1947 [2] marked the beginning of semiconductor device technology. 11 years later, in 1958, the first IC (Integrated Circuits) consisting of one transistor, three resistors, and one capacitor was demonstrated by Kilby in Texas Instrument [3]. From those early days, through continuous development and innovation for several decades, evolved from LSI (Large Scale Integrated Circuits), VLSI (Very Large Scale Integrated Circuits) and ULSI (Ultra Large Scale Integrated Circuits), the number of transistors integrated in a single IC chip has been increased to billions [4]. It is also predicted that this number will be increased to 1 trillion by the year of With increased integration density and hence reduced cost but more functions, IC chips are playing a vital role in communication, computing, and control; greatly improving the convenience and quality of human lives. All these IC chips, just like skyscrapers made from bricks, are assembled from discrete semiconductor devices. One of the most important semiconductor devices used nowadays is MOSFET (Metal Oxide Semiconductor Field Effect Transistor). 1

19 Chapter 1: Introduction 1.2 MOSFET Scaling Scaling Trend MOSFET is a four terminal semiconductor device. Due to its superior properties in device miniaturization and power dissipation, MOSFET has been the mainstream microelectronic device technology since the 1980s. MOSFET device with Si as conducting channel, thermally grown amorphous SiO 2 as gate dielectric and highly doped poly-si as gate electrode has been used by semiconductor industry for several decades, due largely to the system s superior properties such as low interface density between SiO 2 and Si substrate, excellent thermal stability of SiO 2 on Si, and high hard breakdown field of SiO 2 [5]. In recent years, SiO 2 is replaced by SiON to reduce the gate leakage and suppress the dopant penetration from poly-si gate, the aforementioned properties are retained. Although the fundamental structure of MOSFET remained the same during the past several decades; the dimension of the MOSFET has been scaled progressively, driven by consumer s demand for IC chips with lower cost but improved functions and performance such as faster speed and lower power consumption. The scaling trend of the MOSFET is predicated by the famous Moore s law formulated in the 1960s, which simply states that the density of the devices in a chip doubles every 18 months [6-8]. Following Moore s law, Intel s 90 nm technology processor contains MOSFET with gate length as short as 45 nm and gate oxide as thin as 1.2 nm, only a few atom layers. Figure 1.1 details the relationship between the size of the transistor versus year, and the inset shows how the unit cost of a single transistor is reduced as the technology advances [9]. 2

20 Chapter 1: Introduction Figure 1.1 Technology and feature size versus year; the inset is transistor cost versus year [9]. One important electrical parameter associated with the device scaling is the drive current, which determines the speed of integrated circuits. It is always desirable to improve the drive current of a MOSFET so that the speed of circuits can be enhanced. The saturation drive current I d of a MOSFET can be simply stated as [5]: I d =W/LμC inv (V g -V t ) 2 /2 (1.1) In the above equation, W and L are the channel width and channel length of the MOSFET, respectively. V g is the gate bias and the threshold voltage of the transistor is denoted by V t. μ is the carrier mobility in the channel and C inv is the capacitance density when the channel is inverted. Ignoring the quantum mechanical and depletion effects from substrate and gate, the capacitance can be formulated as: C=kε 0 /t (1.2) 3

21 Chapter 1: Introduction Where k denotes the relative permittivity of the gate dielectric material, ε 0 is the permittivity of the free space, which equals to ff/μm; t is the physical thickness of the gate dielectric. Improving I d is usually implemented by reducing the gate length L and dielectric thickness t, due to limitations or difficulties in changing other parameters in equation (1.1): μ is predetermined by using Si as conducting channel; V g can not be increased drastically because of high gate leakage current; V t can not be easily reduced below 200mv due to the concern over statistical fluctuation [5] and increasing W will result in unfavorable increase of the chip size Requirements for Further Scaling Although L and t have been scaled down to 35 nm and 1.2 nm, respectively, for Intel s 65 nm technology processor [4], further scaling is still required to continue the performance boost. In order to keep the historic trend of 17% performance improvement each year, the requirements for industry s future technology are predicated in ITRS (International Technology Roadmap for Semiconductor) [10], a document produced by a group of semiconductor industry experts. Part of the projected requirements is shown in the following table 1.1, adopted from the latest version of ITRS published in the year of 2005 [10]. The MOSFETs are classified for three different applications: HP (high-performance), LSP (Low Standby Power) and LOP (Low Operating Power), and their requirements are slightly different. However, so far, no manufacturable solutions can be offered to meet those requirements with a grey background. The challenges in meeting the requirements are elaborated as follows. 4

22 Chapter 1: Introduction Table 1.1 HP, LSP and LOP Logic Technology Requirements (MPU: Microprocessor Unit; EOT: Equivalent Oxide Thickness; J g,limit : Gate Leakage Current Density Limit.) MPU Metal 1 ½ Pitch (nm) MPU Physical Gate length (nm) EOT for HP logic (Ǻ) EOT for LSP logic (Ǻ) EOT for LOP logic (Ǻ) J g,limit for HP logic (A/cm 2 ) 8.0E E E+03 J g,limit for LSP logic (A/cm 2 ) 2.2E E E E-0.1 J g,limit for LOP logic (A/cm 2 ) 7.8E E E+02 Manufacturable Solutions are not known Challenges for Scaling With further reduction of the SiO 2 thickness, several sever issues are emerging, one of which is intolerable high gate leakage current and it is one of the most constraining factors in scaling. It is found that with every 2 Ǻ thickness reduction of the SiO 2, the gate-to-channel tunneling leakage increases by around 1 order; which causes high power dissipation [11, 12]. Although SiON was later used by industry to alleviate the leakage issue [13], SiON is still not a long term solution for MOSFET scaling and is approaching or has approached its limits. The following figure 1.2 shows simulated gate leakage current J g,sim through SiON under the condition that EOT and V d meet the requirements set by ITRS, together 5

23 Chapter 1: Introduction with J g,limit (gate leakage current density limit) for HP, LSP and LOP logic device application [10]. Once the J g,sim is higher the J g, limit, it means that ITRS EOT and gate leakage requirements can not be met by using SiON HP 10 2 J g (A/cm 2 ) LOP SiON can't meet ITRS requirement beyong this crossover point 10-2 Solid Symbol: J g, limit 10-3 Open Symbol: J LSP g,sim(sion) Calendar Year Figure 1.2 J g, limit and J g, sim for HP, LSP and LOP logic devices. As can be seen from the figure 1.2, SiON can not meet the LSP application in the year of 2007, followed by HP application in 2008 and LOP in On the other hand, due to quantum effects and poly-si gate depletion, the charge in the gate electrode and in the inversion layer in the channel will locate at a certain distance from the Si/SiO 2 interface, resulting in increased EOT [14-16]. The estimated centroind for the inversion charge is 1 nm away from the SiO 2 /Si interface, which will increase the EOT by ~0.3 nm. Taking this effect on both sides, the EOT will be increased by ~0.7 nm [17]. With the EOT requirement for HP logic device is only 0.75 nm or less from 2009 and onwards, 0.7 nm contribution from quantum effects 6

24 Chapter 1: Introduction and poly-si gate depletion is intolerably high, which poses tremendous challenges in meeting the requirement of EOT. 1.3 Approaches for Further Scaling Although poly-si/sio 2 (SiON)/Si based MOSFET structure has been adopted by semiconductor industry for many decades, fundamental limitations mentioned above have prompted researchers to investigate alternative materials and innovative MOSFET structures to continue the roadmap for scaling. Some of the proposed solutions are: 1) high-k gate dielectric/metal gate stack to replace SiO 2 /poly-si; 2) innovative device structure; and 3) advanced channel materials High-k and Metal Gate As shown in the equation (1.2) (ignoring the quantum mechanical and poly-si gate depletion effects), the capacitance is proportional to relative permittivity value of the gate dielectric, if SiO 2 can be replaced by a material with higher k value to achieve the same capacitance, the relationship between the ε SiO2 (relative permittivity of SiO 2 ), t SiO2 (physical thickness of SiO 2 ), k high-k (relative permittivity of high-k gate dielectric) and t high-k (physical thickness of high-k gate dielectric) can be expressed as: t high-k = t SiO2 ε SiO2 / k high-k (1.3) By using a dielectric with higher k value to replace SiO 2 as gate dielectric, even with a substantially thicker physical thickness, it can still improve gate capacitance. A high-k material with thicker physical thickness and suitable band offset to Si, can also suppress the gate leakage current [18-22]. Hence by using high-k gate dielectric, EOT and leakage current can possibly be controlled within the ITRS requirements. 7

25 Chapter 1: Introduction However, k value and band offset are only two among a set of criteria in choosing the suitable high-k gate dielectric for MOSFET integration. Others include, but are not limited to [18]:1) thermodynamic stable on Si substrate; 2) good interface quality with Si substrate; 3) high crystallization temperature; and 4) CMOS process compatibility and excellent reliability. Through the past decade, various high-k materials have been investigated to check the feasibility of their application in MOSFET. The long list contains Ta 2 O 5, SrTiO 3, Y 2 O 3, La 2 O 3, ZrO 2, TiO 2, Al 2 O 3, HfO 2, HfON, HfSiO, HfTaO, HfTaON [23-35]. After searching and evaluating for more than 10 years, it was found that Hf-based oxides hold the most promising properties for application. In addition, using metal gate electrode to replace conventional poly-si gate electrode, the poly-gate depletion effect can be eliminated, resulting in easier EOT scaling. Besides, there are other benefits of using metal gate such as low sheet resistance, elimination of high temperature activation for poly-si gate. In order to achieve a suitable V th value and symmetrical V th for n-mosfet and p- MOSFET, planner bulk devices require the metal electrode to have a work function near conduction band and valance band edge of Si for n-mosfet and p-mosfet application, respectively [36]. Besides, other requirements should be met to qualify the metal electrode for possible CMOS integration such as: good thermal stability, good adhesion with the beneath high-k gate dielectric, and CMOS process compatibility. So far, a large collection of metal gates have also been examined including elemental metals, metal silicides and metal nitrides, metal oxide and metal alloys [37-43]. One of key challenges for gate electrode integration is the Fermi level pinning induced thermal instability [44], although Fermi level pinning is also utilized by some 8

26 Chapter 1: Introduction researchers to achieve suitable metal work function [45]. In order to mitigate the concern over the thermal instability, gate last process was proposed [46]. In this gate last process, the high-k/metal gate stack is formed after the activation of S/D (Source/Drain) rather than prior to in the conventional process. However, in this gate last process, the issue of misalignment between the gate stack and the channel limits its application. Which combination of high-k and metal gate will prove to be the final solution to replace SiO 2 and poly-si gate, and how they can be implemented are still under exploration Innovative Device Structure According to the projection by ITRS 2005, high-k gate dielectric and metal gate electrode will be needed by the year of 2008 to meet the historical 17% performance enhancement each year, while in the same time keeping the leakage within a tolerable level. However in long term, for 32 nm technology node and beyond, scaling of planar bulk MOSFET will face tremendous challenges since in order to control the short channel effects, the channel doping has to be increased undesirably high, resulting in following undesired effects: degradation of electron and hole mobility in the channel, high junction leakage due to band to band tunneling and increase of gateinduced drain leakage [5]. Due to these challenges facing planar bulk MOSFET, several non-classical MOSFET structures are under development for possible replacement of bulk MOSFET such as FD (Fully Depleted) MOSFET and multiple-gate MOSFET. The FD MOSFET is fabricated on a SOI (Silicon on Insulator) substrate with thin Si thickness, thinner than the maximum depletion thickness. This type of device 9

27 Chapter 1: Introduction provides a series of benefits: reduced parasitic capacitance, high transconductance, immunity for short-channel effects, and a near-ideal subthreshold slope [47]. Hence, FD MOSFET provides better scalability than bulk device. SOI MOSFET using high-k gate dielectric and metal gate electrode with excellent performance has been demonstrated [48]. Another transistor structure to control the short channel effects is called double gate transistor in which the gates enclose the channel area to control the communication between the source and drain so that the short channel effect and transistor leakage can be suppressed [49]. FinFET transistors with the channel formed in a vertical Si fin and controlled by self-aligned gates on its two sides made on SOI substrate is attractive double gate architecture, and is under research and exploration [50-52]. FinFET with gate length down to 10 nm were also realized [53]. Extended from the double gate transistor, with further improved short channel immunity, the concept of GAA (gate-all-around) transistor was proposed and the device was also demonstrated [54]. However, the process complexity for GAA transistor will limit its practical application Advanced Channel Material Si has been used as channel material by the industry for decades, due largely to excellent properties of its thermally grown SiO 2. However, in order to achieve higher drive current for improved performance, high mobility semiconductor materials are considered to replace Si, including Ge, SiGe and III-V materials. The properties for Si, Ge and some of the III-V semiconductor materials are listed in the table 1.2 [55]. 10

28 Chapter 1: Introduction From table 1.2, it is noted that Ge offers both higher electron and hole mobility than those of Si, making it an attractive channel material for both n-mosfet and p- MOSFET application. Although intrinsic hole mobility of III-V semiconductors is relative low compared to that of Ge, they have much higher electron mobility, making them the potential candidates for high performance n-mosfet fabrication. Among all the III-V semiconductor materials, GaAs attracts intensive research interest: GaAs has a suitable band gap, and also a similar lattice constant to that of Si and Ge, which makes integration of GaAs based technology on Si or Ge substrate much easier [56, 57]. Table 1.2 Properties of semiconductor materials: Si, Ge, GaAs, InAs, InP, and InSb (μ electron : Electron Mobility; μ hole : Hole Mobility) Si Ge GaAs InAs InP InSb μ electron (cm 2 /V-s) μ hole (cm 2 /V-s) Lattice constant (Ǻ) Band gap (ev) A good quality gate dielectric on Ge and GaAs substrate is critical for high performance Ge and GaAs MOSFET. However, unlike good properties of SiO 2 on Si substrate, native oxides of Ge and GaAs are of poor quality and are not qualified for MOSFET application, which greatly hinders the development of Ge and GaAs MOSFET [58, 59]. With the progress made in high-k deposition technique, Ge and GaAs MOS devices with various high-k materials have been reported [60-63]. However, it is found that during the gate stack formation, the surface of Ge and GaAs 11

29 Chapter 1: Introduction would be oxidized and the generated oxides could severely degrade the performance of these devices [61, 64]. Hence passivation techniques for Ge and GaAs substrates are needed to suppress the formation of interfacial oxides. Thermal nitridation for Ge substrate and Si or Ge passivation for GaAs have been proposed [60, 63, 65]. Improved MOS devices with these applications were also demonstrated. However these passivation techniques have their own limitations: although thermal nitrididation passivation is proven to be successful on n-type Ge substrate, few research results on p-type Ge were shown; Si and Ge are both amphoteric impurities in GaAs, using Si and Ge passivation for GaAs would cause the concern over substrate counter doping and threshold voltage fluctuation [66]. Hence, new and innovative passivation techniques are to be explored for Ge and GaAs MOS technology. On the other hand, looking forward, due to the similar limits for bulk Si MOSFET, bulk Ge or GaAs technology is not attractive compared with Ge or GaAs on insulator structure. Although so far no GaAs on insulator fabrication has ever been reported, various ways of fabricating GOI (Ge on Insulator), SGOI (Silicon Germanium on insulator) have been proposed including bonding [67] and smart-cut [68], condensation [69]. Among them, Ge condensation technique has drawn great attention due to its simple process steps and easy control over Ge concentration. This condensation process starts with epitaxial growth of SiGe film on SOI wafer followed by multi-step oxidation process. However, since this condensation requires SiGe epitaxy, the process cost would be significantly increased. Cost effective novel condensation approaches are yet to be developed. Besides, it is very attractive if Ge devices can be integrated into Si-based substrate for integration purpose, so methods for localized GOI, SGOI fabrication are of particular interest. 12

30 Chapter 1: Introduction Finally, there are tremendous process integration challenges for new substrate MOSFET with high-k gate dielectric and metal gate: Ge easily diffuses into the highk gate dielectric, causing the high gate leakage [70] whcih is also likely for GaAs substrate since As is quite volatile, so the process temperature for Ge and GaAs MOSFET can not be as high as Si MOSFET. In addition, low solid solubility of dopants in Ge [71], and low activation efficiency of dopants in Ge and GaAs [72, 73] requires innovation in S/D fabrication. 1.4 Summary In summary, driven by consumers demands for IC chips with higher performance but lower cost, the dimension of MOSFET has been scaled continuously following the Moor s law for nearly half a century. Further scaling of conventional MOSFET with Si as substrate, SiON as gate dielectric and highly doped poly-si as gate electrode is reaching its fundamental limits: intolerable high tunneling gate leakage, difficulties in EOT scaling due to poly-si gate depletion effect and challenges in controlling the short channel effects. Fundamental changes on the materials and structure of the MOSFET are inevitable in order to continue the historical aggressive scaling for leading-edge logic device. The high-k and metal gate technology is needed to replace the SiON and ploy- Si gate in the near future. However, in the long-term for 32 nm technology node and beyond, FD MOSFET, double gate MOSFET and high mobility channel MOSFET could be the possible solutions. But whether these potential solutions will be introduced by the industry depend largely on future research results and technology breakthrough. There are still many technical challenges and inadequate understanding associated with these devices such as process integration, modeling, carrier 13

31 Chapter 1: Introduction transportation and process variation. Different companies could finally adopt their individual approach where their strength lies in. 1.5 Thesis Organization Regarding advanced channel material MOSFET, important issues should be addressed as mentioned in section 2: 1) effective surface passivation technique for Ge and GaAs MOS device; 2) localized GOI fabrication and cost effective process for manufacturing high mobility channel material on insulator; 3) integration of high mobility channel MOSFET with high-k and metal gate. These aspects will be discussed and explored in this thesis with the hope that it can provide useful information for further development. Hence, chapter 2 begins with the passivation techniques for Ge and GaAs. Thin AlN passivation is applied to both Ge and GaAs substrates. Besides, nitridation surface treatment of GaAs surface before the deposition of high-k is also discussed. Then, chapter 3 covers fabrication techniques for high mobility channel on insulator structure (SGOI and GOI). In the first part of the chapter, SPE (Solid phase Epitaxy) growth method was proposed for localized GOI fabrication. Then in the second part, cost effective novel condensation method would be investigated for high Germanium percentage SGOI substrate preparation. In chapter 4, the process integration for high mobility channel MOSFET with high-k and metal gate using Schottky S/D would be discussed. Schottky S/D transistor fabricated on both SGOI and Ge 0.95 Si 0.05 /Si substrates are demonstrated. Finally, the closing chapter summaries the thesis and discusses possible research opportunities in the area of advanced channel material MOSFET. 14

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35 Chapter 1: Introduction [29] C. Choi, C.Y. Kang, S.J. Rhee, M.S. Abkar, S.A. Krishna, M. Zhang, H.Kim, T. Lee. F.Zhu, I. Ok, S. Koveshnikov, and J.C. Lee, Fabrication of TaN-gated Ultra- Thin MOSFETs (EOT<1.0nm) with HfO 2 using a Novel Oxygen Scavenging Process for Sub 65nm application, 2005 Symposium on VLSI Technology Digest of Technical Papers, p.226 (2005); [30] S.B. Samavedam, H.H. Tseng, P.J. Tobin, J. Mogab, S.D.-Murthy, L.B. La, J. Smith, J. Schaeffer, M. Zavala, R. Martin, B.-Y. Nguyen, L. Hebert, O. Adetutu, V. Dhandapani, T.-Y. Luo, R. Garcia, P. Abramowitz, M. Moosa, D.C. Glimer, C. Hobbs, W.J. Taylor, J.M. Grant, R. Hegde, S. Bagchi, E. Luckowski, V. Arunachalam, M. Azrak, Metal Gate MOSFETs with HfO 2 Gate Dielectric, 2002 Symposium on VLSI Technology Digest of Technical Papers, p.24 (2002); [31] E.P. Gusev, D.A. Buchana, E. Cartier, A. Kumar, D. Dimaria, S. Guha, A. Callegari, S, Zafar, P.C. Jamison, D.A. Neumayer, M. Copel, M.A. Gribelyuk, H.Okron-Schmidt, C.D Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L-A, Ragnarsson, P. Ronsheim, K. Rim, R.J. Fleming, A. Mocuta, and A. Ajmera, Ultrathin high-k gate stacks for advanced CMOS Devices, IEDM Technical Digest., 2001, p (2001); [32] H.Y. Yu, J.F. Kang, J.D. Chen, C. Ren, Y.T. Hou, S.J. Whang, M.-F. Li, D.S.H. Chan, K.L. Bera, C.H. Tung, A. Du and D.-L. Kwong, Thermally Robust High Quality HfN/HfO 2 Gate Stack for Advanced CMOS Devices, IEDM Technical Digest., 2003, p (2003); [33] J.C. Lee, H.J. Kang, C.S. Kang, Y.K. Kim, R. Choi, C.Y. Kang, M. Abkar, High-k dielectrics and MOSFET characteristics, International Electron Devices Meeting, 2003, p (2003); 18

36 Chapter 1: Introduction [34] Choi, R. Harris, R. Lee, B.H. Young, C.D. Sim, J.H. Matthews, K. Pendley, M. Bersuker, G., Threshold voltage instability of HfSiO dielectric MOSFET under pulsed stress, Reliability Physics Symposium, Proceedings. 43rd Annual IEEE International, p.634 (2005); [35] M. H. Zhang, J. Rhee, C.Y. Kang, C.H. Choi, M.S. Akbar, S.A. Krishnan, T. Lee, I.J. Ok, F. Zhu, H.S. Kim, and J.C. Lee, Improved electrical and material characteristics of HfTaO gate dielectric with high crystallization temperature, Appl. Phys. Lett. 87, p (2005); [36] Y.-C. Yeo, T.-S. King, and C.Hu, Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology, Journal of Applied Physics, vol. 92, p.7266 (2002); [37] Y.-C. Yeo, Q. Lu, O. Ranade, H. Takeuchi, K.J. Yang, I. Polishchuk, T.-S. King, C. Hu, S.C. Song, H.F. Luan, D.-L. Kwong, Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric, IEEE Electron Device Letter, vol. 22, p.227 (2001); [40] W.P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, M.-R. Lin, Transistor with dual work function metal gates by single full silicidation (FUSL) of polysilicon gates, International Electron Devices Meeting, 2002, p.367 (2002); [41] C.S. Kang, H.-J. Cho, Y.H. Kim, R. Choi, K. Onishi, A. Shahriar, and J.C. Lee, Characterization of resistivity and work function of sputtered-tan film for gate electrode application, Journal of Vacuum Science and Technology, Vol. 21, p.2026 (2003); [42] H. Zhong, G. Heuss, and V. Misra, Electrical properties of RuO 2 gate electrodes for dual metal gate Si-CMOS, IEEE Electron Device Letter, vol, 21, p.593 (2000); 19

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39 Chapter 1: Introduction [58] O.J. Gregory, E.E. Crisman, L. Pruitt, D.J. Hymes, and J.J. Rosenberg, Electrical characterization of some native insulators on germanium, Proceeding of Materials Research Society Symposium, vol.76 (1987); [59] H. Hasegawa, K.E. Forward, and H.L. Hartnagel, New Anodic Native Oxide of GaAs with Improved Dielectric and Interface Properties, Applied Physics Letters, vol.26, p.567 (1975); [60] W.P. Bai, N. Lu, J. Liu, A. Ramirez, D.L. Kwong, D. Wristers, A. Ritenour, L. Lee, and D. Antoniadis, Ge MOS Characteristics with CVD HfO 2 gate dielectric and TaN Gate Electrode, Digest of Technical Papers Symposium on VLSI Technology, (2003); [61] C.O. Chui, S. Ramanathan, B.B. Triplett, P.C. McIntyre, and K.C. Saraswat, Germanium MOS Capacitors Incorporating Ultrathin High-k Gate Dielectric, IEEE Electron Device Letters, Vol, 23, p.473 (2002); [62] M.M. Frank, G.D. Wilk, D. Starodub, T. Gustafsson, E. Garfunkel, Y.J. Chabal, J. Grazul, and D.A. Muller, HfO 2 and Al 2 O 3 Gate Dielectrics on GaAs Grown by Atomic Layer Deposition, Applied Physics Letters, vol. 86, p (2005); [63] S. Koveshnikov, W. Tsai, I. Ok, J.C. Lee, V. Torkanov, M. Yakimov, and S. Oktyabrsky, Metal-Oxide-Semiconductor Capacitors on GaAs with High-k Gate Oxide and Amorphous Silicon Interface Passivation layer, Applied Physics Letters, 88, p (2006); [64] K. Kita, M. Sasagawa, K. Tomida, K. Kyuno, and A. Toriumi, Oxidation- Induced Damage on Germanium MIS Capacitors with HfO 2 Gate Dielectrics, Extended Abstract of the 2003 International Conference on Solid State Devices and Materials, p.292 (2003); 22

40 Chapter 1: Introduction [65] D.Shahrjerdi, M.M. Oye, A.L. Holmes, S. K. Banerjee, Unpinned Metal Gate/High-k GaAs Capacitors: Fabrication and Characterization, Applied Physics Letters, 89, p (2006); [66] T. Moriizumi and K. Takahashi, Si- and Ge-Doped GaAs p-n junction, Japanese Journal of Applied Physics, vol. 8, p.348 (1969); [67] G. Taraschi, A.J. Pitera, and E.A. Fitzgerald, Strained Si, SiGe, and Ge oninsulator: review of wafer bonding fabrication techniques, Solid-State Electronics, vol 48, p.1297 (2004); [68] Y.-L. Chao, R. Scholz, M. Reiche, U.M. Gosele, and. J.C.S. Woo, Fabrication and Characterization of Germanium-on-Insulator, Extended Abstract of the 2004 International Conference on Solid State Devices and Materials, 2004, p.224 (2004); [69] S. Nakaharai, T. Tezuka, N. Sugiyama, Y. Moriyama, and S.-I. Tagagi, Characterizaiton of 7-nm-thick strained Ge-on-insulator layer fabricated by Gecondensation technique, Applied Physics Letters, vol. 83, p.3516 (2003); [70] S.V. Elshocht, B. Brijs, M. Caymax, T. Conard, T. Chiarella, S.D. Gendt, S.D. Jaeger, S. Kubicek, M. Meuris, B. Onsia, O. Richard, I. Teerlinck, J.V. Steenbergen, C. Zhao, and M. Heyns, Deposition of HfO 2 on Germanium and the impact of surface pretreatments, Applied Physics Letter, Vol. 85, p.3824 (2004); [71] F.A. Trumbore, Solid solubilities of impurity elements in germanium and silicon, Bell Syst. Tech. J., p.205 (1960); [72] H. Shang, K.-L. Lee, P. Kozlowski, C.D Emic, I. Babich, E. Sikorshi, M. Ieong, H.-S.P. Wong, K. Guarini, W. Haensch, Self-Aligned n-channel Germanium MOSFETs With a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate, IEEE Electron Device Letters, vol.25 (2004); 23

41 Chapter 1: Introduction [73] J.M. Woodcock, J.M. Shannon, and D.J. Clark, Electrical and Cathodoluminescence Measurements on Ion Implanted Donor Layers in GaAs, Solid-State Electronics, vol. 18, p.267 (1975). 24

42 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Chapter 2 Surface Passivation for Ge and GaAs substrates for MOS Device Application As mentioned in the previous chapter, in searching for new substrate materials for high performance CMOS application, Ge and GaAs have gained extensive research interest due to their attractive property of higher carrier mobility. However, their poor quality native oxides greatly retard the development of Ge and GaAs MOSFETs (Metal Oxide Semiconductor Field Effect Transistor). Minimizing the formation of interfacial oxides on Ge and GaAs substrate during the gate stack formation is critical for high performance Ge and GaAs MOSFETs. Hence, effective surface passivation techniques are essential for Ge and GaAs based MOS technology. And in this chapter, the proposed passivation methods for both Ge and GaAs substrates will be discussed and analyzed. By using these surface passivation methods, Ge and GaAs MOS devices with improved C-V (Capacitance-Voltage) and thermal stability are also presented. In section 2.1, ultrathin AlN x passivation for Ge substrate is touched. AlN passivation and plasma nitridation for GaAs substrate are presented in section 2.2. Finally section 2.3 summarizes this chapter. 25

43 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application 2.1 Surface Passivation for Ge Introduction Although the world s first integrated circuit was made on Ge substrate [1], the material was quickly eclipsed by Si as the prime semiconductor. However, Ge has recently regained tremendous attention since it offers very high electron and hole mobility making this material ideally suited for high-speed circuits. Unfortunately, unlike Si-Oxide, it is known that Ge-Oxide is thermodynamically unstable and soluble to water [2]. Ge MOS capacitor with GeO 2 as the gate dielectric shows distorted C-V characteristics, indicating high level of interface states and interface traps [3, 4]. Later, SiO 2, Si 3 N 4, GeON have been tried as gate dielectric for Ge MOS device; however the results are rather disappointing [5, 6]. Lack of a suitable high quality oxide for Ge greatly hinders the development of Ge MOSFET. Fortunately, the deposited high-k material as an alternative gate dielectric provides a chance to fabricate good performance Ge-MOSFETs. So far several groups have demonstrated either Ge-MOS capacitors or Ge-MOSFETs integrated with Al 2 O 3 [7], ZrO 2 [8] and HfO 2 [9, 10]. It was reported that during the post process, Ge surface would be oxidized to form GeO x, which leads to the degradation of device performance [8, 11, 12, 13]. The method of SN (Surface Nitridation) in NH 3 prior to high-k deposition to form a thin layer of Ge oxynitride was proposed to reduce the excessive GeO 2 growth [10]. Improvement in electrical performances was demonstrated by using SN passivation on both p-mos capacitors and p-mosfets fabricated on n-type Ge substrate [10]. However, no successful results have been reported on Ge n-mos devices [14]. The difficulties in making a good Ge n- 26

44 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application MOSFET lie in higher P type dopants activation temperature but poor thermal stability of the thin oxynitride. In addition, it is still unclear how effectively the thin Ge oxynitride layer can prevent Ge-O formation during the high-k deposition since no relative analysis was reported. In this section, Ge surface passivation using ultra-thin AlN x layer is discussed. Improved film quality is examined with XPS (X-ray Photoelectron Spectroscopy) and TEM (Transmission Electron Microscopy) analyses, and electrical and thermal properties are compared to SN passivated samples Experiment MOS capacitors were fabricated on P type (Ga-doped) and N type (As-doped), (100) Ge wafers. After dipping in 1% dilute HF solution, two pre-gate treatments were applied: (SN sample) SN at 600 in NH 3 ambient for 2 minutes; (AlN sample) ultra-thin AlN x layer was deposited by reactive sputtering of Al target in N 2 /Ar ambient. The thickness of the AlN layer was estimated to be ~1.5 nm based on measured deposition rate of sputtering. The deposition rate was kept low and the 1.5 nm AlN deposition took 45 seconds. Then metal organic chemical vapor deposition or ALD (Atomic Layer Deposition) HfO 2 was deposited on both samples followed by PDA (Post Deposition Annealing) at 400 for 60 seconds in N 2. The ALD HfO 2 deposition was carried out at 320 using H 2 O and HfCl 4 as precursors. TaN gate electrode was prepared by sputtering of Ta target in Ar/N 2 ambient. After gate patterning, the Ge capacitors received a forming gas annealing (FGA) at 300 for 10 minutes to passivate the dangling bonds. 27

45 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Ge p- & n-mosfets were also fabricated. For Ge MOSFET fabrication, after TaN gate definition, boron (for p-mosfet) and phosphorus (for n-mosfet) were implanted into the wafer to form self-aligned source and drain. The implantation energy was 35 KeV for B and 50 Kev for P, implantation does for both B and P was 1E15/cm 2. After the dopant activation at 400 o C for B and 600 o C for P, Al contact was deposited on the S/D by sputtering. Finally the devices received FGA at 300 for 10 minutes Results and Analysis Passivation effects XPS analysis was carried out at the pressure of 10-9 mbar using monochromatic Al kα source with an energy of ev. The C 1s line with a binding energy of ev was used as a reference to eliminate the charge effect during the analysis. Figure 2.1 (A) shows Ge 3d spectra after each processing step for SN sample. No peak corresponding to GeO 2 was observed after dilute HF cleaning indicating that GeO 2 was removed completely. A small increase in the intensity of the Ge 3d peak at ~ 32.3 ev after SN on Germanium surface is caused from the slight oxidation during thermal nitridation of Ge. figure 2.1 (B) shows N 1s signal for SN sample, a peak with a binding energy of ev corresponding to N-Ge bond shows that a thin Ge oxynitride was formed during this 600 nitridation process [10]. It is observed that the intensity of the GeO 2 peak increased significantly after HfO 2 deposition, indicating that most of GeO 2 was formed at the interface during HfO 2 deposition process as shown in figure 2.1 (A). Figure 2.1 (C) shows Al 2p XPS spectra of AlN sample both after and before HfO 2 deposition. After the AlN x deposition, Al 2p peak 28

46 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application was observed at a binding energy 73.9 ev confirming that the deposited layer was AlN x. The shift of the Al 2p peak to a higher binding energy by 0.56 ev after the Intensity [A.U] Ge HfO 2 dep. (A) GeO 2 Ge 3d SN DHF Binding Energy [ev] Intensity [A.U.] N 1s N-Ge N-O (B) Binding Energy [ev] Intensity [A.U] 0.56eV Al 2p (C) AlN+ HfO 2 AlN dep Binding Energy [ev] Intensity [A.U.] Ge 3d Ge GeO 2 (D) SN AlN Binding Energy [ev] Figure 2.1 XPS analyses: (A) Ge 3d spectra for SN sample after DHF cleaning, SN and HfO 2 deposition; (B) N 1s spectra for SN sample after annealing in NH 3 at 600 ; (C) Al 2p spectra for AlN sample before and after HfO 2 deposition; (D) Ge 3d spectra for both SN and AlN samples after HfO 2 deposition; 29

47 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application HfO 2 deposition shows that part of the sputtered AlN x thin film is oxidized to form Al-O bond. This could be explained by a much larger standard heat of formation of Al 2 O 3 (-1675K.J/mol) than that of AlN (-348K.J/mol) [15, 16]. Since AlN x acted as an oxygen reaction barrier, so it was effective in minimizing the GeO 2 formation during the high-k deposition. Figure 2.1 (D) of Ge 3d XPS spectra of SN sample and AlN sample after PDA clearly shows that the GeO 2 was reduced in case of AlN x passivated sample Gate Stack TEM TaN HfO 2 38Å Ge substrate 7Å Figure 2.2 TEM image of TaN/HfO 2 /Ge gate stack with AlN-passivation. Figure 2.2 shows the TEM picture of the gate stack for AlN sample. Ultra thin (7Å) interfacial layer is observed beneath the conformal HfO 2 layer. As expected, the 30

48 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application HfO 2 layer remained amorphous which was an advantage of the low temperature process because the grain boundary of crystallized high-k often acts as oxygen diffusion route and serves as high-leakage paths [17] C-V and I-V characteristics C (ff/μm 2 ) (A) Measured HFCV (AlN Sample) Simulation LFCV (AlN Sample) Measured HFCV (SN Sample) V g (V) 10-7 SN AlN J g (A/cm 2 ) 10-8 (B) V g (V) Figure 2.3 (A) Measured high frequency C-V and simulated low frequency C-V for AlN sample and measured high frequency C-V for SN sample; (B) shows the gate Leakage current density versus gate voltage. 31

49 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application C-V characteristics measured at 1 MHz are shown in figure 2.3(A). For SN sample, the C-V was severely distorted in the inversion part which is believed to be due to the excessive GeO 2 piled at the interface between the Ge and the gate dielectric. However, for AlN sample, excellent C-V curve was achieved and the EOT was extracted to be 20 Å. The good fit between the measured C-V and simulated low frequency C-V indicates the excellent interface between the Germanium and high-k gate stack. Gate leakage current density level was in the same order for this two different surface treatment as indicated in figure 2.3 (B) Gate Stack Thermal Stability In order to make Ge n-mosfets, we need to activate the dopant Phosphorus at around 600, or even higher temperature for other dopants such as Arsenic [18, 19]. The thermal stability of Ge MOS capacitors are also investigated after post anneal at various temperatures. Both SN sample and AlN sample were annealed at 500, 600 and 700 by rapid thermal annealing at N 2 ambient for 2 minutes. Gate leakage current density at V g -V fb =1 V and EOT were extracted after each post annealing and were plotted in figure 2.4. It shows that after 600 annealing for 2 minutes, the gate leakage current density for SN increased by ~ 6 orders. By contrast, the gate leakage current density for AlN sample increased by less than 3 orders even after annealing at 700 for 2 minutes. It is believed that the sudden increase in leakage density is partially due to the Ge diffusion from the substrate to HfO 2 [11, 20]. Observed results suggest that thin layer of AlN x is more effective in preventing the Ge diffusion than thin Ge oxynitride due its robustness. EOT of both SN and AlN sample decreased slightly after 500 annealing due to HfO 2 densification. Further high temperature 32

50 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application annealing led to slight increase in EOT because of the interfacial layer growth [21]. Low leakage density level for AlN sample after post annealing at 600 for 2 minutes and stable EOT implied that this AlN x passivation technique could sustain the high temperature dopant activation process during the Ge-MOFET fabrication without severe degradation of device performance. Figure 2.4 EOT and gate leakage current density at V g -V fb =1V for both AlN and SN sample after different post annealing conditions Effect of AlN thickness The impact of AlN film thickness on the C-V characteristics of the Ge MOS capacitors was also investigated. By controlling the deposition time of sputtering, AlN layer with thickness of 1 nm (sputtering time 30s) and 0.5 nm (sputtering time 20s) were deposited on pre-cleaned Ge wafers, followed by HfO 2 deposition with a thickness of either 2 nm or 3.5 nm. Metal TaN was still used as the gate electrode. 33

51 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application The following figure 2.5 shows the typical C-V characteristics from the fabricated Ge MOS capacitor with different AlN and HfO 2 thichkness. Excellent C-V with sharp rise and saturated accumulation capacitance was observed with 1 nm AlN and 2 nm HfO 2. C-V of the same quality was also achieved by using thinner 0.5 nm AlN. The higher saturated capacitance (corresponding to an EOT of 1.05 nm) value is due to difference of AlN thickness. Hence, 0.5 nm AlN was thick enough to protect the Ge surface from oxidation when depositing 2 nm HfO 2. However, the obvious stretch-out of C-V curve was observed once the the thickness of HfO 2 was increased to 3.5 nm. This implies that during the HfO 2 deposition, the oxidant continuously diffuses through HfO 2 layer and oxidizes the AlN. If the thickness of AlN is too thin, degradation of the interface will happen. C (ff/μm 2 ) EOT= 1.05nm AlN(0.5nm)+HfO 2 (2nm) AlN(0.5nm)+HfO 2 (3.5nm) AlN(1nm)+HfO 2 (2nm) V g (V) Figure 2.5 Measured C-V characteristics from Ge capacitor with different AlN passivation thickness and high-k HfO 2 thickness. Although 0.5 nm AlN is thick enough to protect the Ge surface from being oxidized when depositing thin 2 nm HfO 2 ; stretch-out of C-V curve is observed with HfO 2 thickness increased to 3.5 nm, implying the surface oxidation of Ge. 34

52 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Scalability In order to evaluate the performance of AlN X /HfO 2 dielectric more representatively, we have benchmarked the gate leakage density as a function of EOT as is shown in figure 2.6. The gate leakage current is collected from Ge MOS capacitor made on n-type substrate with different EOT. As a reference, gate leakage of SiO 2 on Si and the gate leakage of HfO 2 on Ge substrate with SN treatment are also included [14, 23]. It is observed that Ge with AlN X /HfO 2 gate dielectric exhibits reduced gate leakage compared with SN samples, and at least ~3 order gate leakage density reduction than SiO 2 on Si substrate. J g (A/cm 2 ) AlN X /HfO 2 Si/SiO 2 SN [14] EOT (Å ) Figure 2.6 Gate leakage density (normalized at V g -V fb =1V) as a function of EOT for AlN X /HfO 2 on Ge substrate and HfO 2 on Ge substrate with conventional SN treatment. (The leakage data for HfO 2 on Ge substrate with SN treatment is from reference [14].)As a reference, the leakage current from SiO 2 on the Si substrate is also included. All the leakages are from n-type substrates Ge MOSFET with AlN passivation 35

53 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Figure 2.7 plots the typical inversion C-V characteristics measured at f=1mhz for the Ge p-mosfet with 1.0 nm AlN passivation layer and 4 nm HfO 2. Excellent inversion characteristics were achieved and the peak inversion capacitance corresponds to an EOT of 2.05 nm. 14 C (ff/μm 2 ) Passivation: AlN 1nm HfO 2 4nm Inversion EOT= 2.05nm V g (V) Figure 2.7 Typical as-measured inversion C-V characteristics for Ge p-mosfet with 1nm-AlN X /4nm-HfO 2 gate dielectric. The inversion side capacitance corresponds to an EOT of 2.05 nm. 36

54 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application I S (μa/μm) (A) S.S=82mV/dec V d = -1V W/L=400/10 μm V d = -0.05V V g (V) I s (μa/μm) V g =0 to -2V Step= -0.4V W/L=400/10 μm (B) V d (V) Figure 2.8 (A) I s -V g characteristics of Ge p-mosfet with AlN X /HfO 2 gate dielectric. Sub-threshold swing as low as 82 mv/dec is obtained; (B) I s -V d curves for Ge p- MOSFET with AlN X /HfO 2 gate dielectric. 37

55 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Figure 2.8 (A) shows the well-behaved I s -V g characteristic of the fabricated Ge p- MOSFET at the drain bias of V and -1 V. S.S (sub-threshold slope) as low as 82 mv/dec is obtained which indicates the excellent interface quality, to the best of our knowledge, this is the lowest S.S ever reported. Typical output I s -V d (Source Current versus Drain Voltage) of the Ge p-mosfet is shown in figure 2.8 (B). Extracted hole mobility of the Ge p-mosfet with AlN X /HfO 2 and hole mobility from Si & Ge p-mosfets with SN surface treatment and HfO 2 gate dielectric are compared in figure 2.9 [24, 25]. It can been seen that hole mobility of Ge p-mosfet with AlN X /HfO 2 shows 20% and 40% increase over the mobility of Si and Ge p- MOSFET with SN/HfO 2, respectively. Hole Mobility (cm 2 /V-s) Si SN+HfO 2 Ref [25] Ge SN+HfO 2 Ref [24] Ge AlN X /HfO Electric Field (MV/cm) Figure 2.9 Hole mobility of the Si and Ge p-mosfets with AlN or SN passivation, Ge MOSFET with thin-aln/hfo 2 passivation shows 20% and 40% increase over the mobility of Si and Ge p-mosfet with SN/HfO 2, respectively. 38

56 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Ge n-mosfet with AlN passivation and HfO 2 /TaN gate stack is also demonstrated and the typical I s -V d curves are shown in the figure The relative low current could be due to dopant loss and/or insufficient dopant activion [26], which is another challenge in fabricating high performance Ge MOSFET especially for n-mosfet, hence innovation in S/D technology is needed [the S/D engineering is discussed in Chapter 4] V g = 0 to 2V L= 20 μm I s (μa/μm) V d (V) Figure 2.10 Measured I s -V d output characteristics for Ge n-moseet with AlN- HfO 2 /TaN at gate bias from 0 to 2V Conclusion In conclusion, an effective Ge surface passivation using a thin layer of AlN x to prevent the GeO 2 formation was demonstrated. Compared with SN, superior Gecapacitor with excellent C-V characteristics and thermal stability was achieved using 39

57 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application this passivation method. Besides, by using AlN x passivation, Ge p- and n-mosfet with HfO 2 /TaN gate stack were successfully demonstrated. Ge p-mosfet showed improved hole mobility compared with Si or Ge MOSFET with SN surface treatment. However, dopant loss and low activation inefficiency could be the root cause for low drive current of Ge n-mosfet. Hence, for high performance n-mosfet application, GaAs was considered as an alternative option. In the following section, we will move to GaAs based MOS device fabrication. 2.2 Surface Passivation for GaAs Introduction Due to its higher (~5X) intrinsic electron mobility and lower effective mass than those of Si, GaAs is a promising channel material for future high-performance n- MOSFET devices. Recent progresses in development of high-k dielectric have reopened the possibility of realizing CMOS devices in GaAs, overcoming its poor quality native oxide issues [27]. Recently, without surface-passivation, GaAs MOSdevices with ultra high vacuum Ga 2 O 3 (Gd 2 O 3 ) or ALD Al 2 O 3 as gate dielectric have been successfully demonstrated [28-31]. However, direct deposition of ALD HfO 2, one of the most promising high-k candidates for future MOS devices, on GaAs showed abnormal C-V without accumulation capacitance [32]. The different interfacial layer growth on GaAs during ALD Al 2 O 3 and ALD HfO 2 processes were also observed [33]. Si or Ge passivation before ALD HfO 2 deposition was proposed and improved C-V characteristics was demonstrated [32, 34, and 35]. In these passivation methods, a thin layer of Si or Ge was deposited on the GaAs surface before the high-k HfO 2 deposition. However, Si and Ge can be both n- and p-type dopants for GaAs substrate, a thin layer of Si or Ge between the HfO 2 and GaAs may 40

58 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application alter the doping concentration or even counter-doping the GaAs substrate, causing the instability of the threshold voltage. In this section, we proposed the PN (Plasma Nitridation) and AlN-passivation techniques for GaAs devices. By using these surface passivation techniques, excellent n- and p-gaas capacitors with both ALD HfO 2 and Al 2 O 3 gate dielectrics are demonstrated Experiment n- (Si-doped) and p-type (Zn-doped) (100) GaAs wafers were pre-gate cleaned by either DHF for 20 minutes or 25% HCl for 20 minutes. After pre-gate cleaning, three different passivation techniques were applied, 1) ~1.5 nm Si deposition on GaAs substrate by sputtering; 2) ~1.5 nm AlN deposition on GaAs substrate by sputtering; 3) PN of GaAs surface at 150~280 0 C in NH 3 /N 2 ambient. ALD-HfO 2 film using H 2 O and HfCl 4 as processors were deposited at 320 o C, followed by PDA in N 2 ambient. Reactive sputtered TaN was used as gate electrode. After lithography and pattering, the GaAs capacitors received FGA at 400~600 o C for 10 minutes. The device structure is shown in figure TaN ALD High-K Passivation layer GaAs (P and N type) Figure 2.11 Structure for GaAs MOS capacitors with different pre-gate cleaning and passivation techniques integrated with high-k/metal gate. 41

59 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Results and Discussion Surface Cleaning Effect First, the pre-gate cleaning effect on GaAs was investigated. Figure 2.12 shows (A) Ga 3d and (B) As 3d XPS spectra from GaAs surface before and after pre-gate cleaning. It shows that native oxides of GaAs, which lead to the Fermi level pinning and gap states [29], can be removed by either DHF or HCl cleaning. (A) Ga-As Ga 3d Intensity [A. U.] W/O clean HCl Ga-O DHF Binding Energy [ev] (B) As-Ga As 3d Intensity [A. U.] W/O Clean DHF HCl As-O Binding Energy [ev] Figure 2.12 XPS analysis of GaAs surface before and after DHF and HCl pre-gate cleaning: (A) Ga 3d spectra and (B) As 3d spectra. The spectra indicate both pre-gate cleaning methods are effective in removing the native oxides in GaAs surface. 42

60 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Figure 2.13 shows the C-V characteristics for Si-passivated GaAs capacitor with 5nm- HfO 2 using HCl and DHF pre-gate clean. The inset is the gate leakage density as a function of the gate voltage. Better C-V characteristic was obtained from DHFcleaned Si-passivated HfO 2 sample with comparable leakage possibly due to the Asrich surface after HCl cleaning [36]. And As rich surface could be the cause of surface pining [37], resulting in distorted C-V. Hence, DHF cleaning was used to fabricate other devices in this work C (ff/μm 2 ) 8 6 Jg (A/cm 2 ) Vg (V) 4 HCl DHF V g (V) Figure 2.13 C-V characteristics for Si-passivated GaAs capacitor with 5nm-HfO 2 /TaN gate stack using HCl and DHF pre-gate clean. The inset is the gate leakage current Surface Morphology Surface roughness and morphology of the GaAs samples were measured by AFM (Atomic Force Microscopy) within an area of 5μm 5μm after pre-gate cleaning, passivation and ALD high-k dielectric deposition. AFM surface image on 43

61 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application HfO 2 /GaAs stack with DHF clean and AlN-passivation is shown in figure 2.14 and smooth surface without obvious damage is observed. RMS (Root Mean Square) values within acceptable range are summarized in table 2.1. Relatively high RMS value after PN process may be induced by plasma damage during the PN process. Figure 2.14 AFM surface image on HfO 2 /GaAs stack with DHF clean and AlNpassivation, smooth surface with no detectable damaged was noted. Table 2.1 Top surface roughness RMS values measured by AFM within an area of 5 μm by 5 μm after different process steps: Sample RMS (nm) Without clean DHF HCl DHF+Al 2 O DHF+HfO DHF+PN DHF+AlN+HfO

62 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application PN Surface Treatment PN process of GaAs surface is studied by XPS shown in figure N 1s core level spectrum in figure 2.15 (A) is recorded from the GaAs surface after PN process. N-Ga and N-O bonds indicate that a thin layer of GaON is formed during the PN process. No As-N signal is detected in N 1s and As 3d spectra in figure 2.15 (B), implying no presence of As-oxynitride at interface. figure 2.15 (C) shows the Ga 3d spectra before and after PN process, confirming the formation of GaON. However if the sample after PN was dipped in DHF and re-examined by XPS, there would be no N-Ga bond found as also shown in figure 2.15 (C), indicating GaON can be etched away by DHF. C-V characteristics of TaN/HfO 2 /GaAs stack with different plasma nitridation conditions are examined in figure It was found that C-V shape and V fb are sensitive to nitridation condition, suggesting that the interface quality is greatly affected by the amount of N-incorporated and the thickness of GaON layer. Degraded interface is observed for insufficient nitridation process, however over nitridation will not only increase the EOT, but also degrade the C-V characteristics. N-O N-Ga N 1s Intensity [A.U.] (A) Binding Energy [ev] 45

63 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application As 3d 5/2 Intensity [A.U.] After DHF Clean After Nitridation (B) Bing Energy (Ev) (C) Ga-As DHF+Nitridation +DHF Ga 3d Intensity [A.U.] DHF Ga-N Ga-O DHF+Nitridation Binding Energy (ev) Figure 2.15 (A) XPS N 1s core level region of the GaAs surface after PN process, (B) XPS As 3d core level region of the GaAs surface before and after PN process; (C) XPS Ga 3d core level peak before and after nitridation, and after DHF etching of the nitride layer for 10 minutes. 46

64 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application C (ff/μm 2 ) S, 150 o C, HfO 2 30S, 280 o C, HfO 2 60S, 280 o C, HfO 2 10S, 150 o C, HfO KHz V g (V) Figure 2.16 High-frequency C-V characteristics of TaN/HfO 2 /GaAs stack with different plasma nitridation processes (time and temperature) AlN Surface Treatment Effect of AlN-passivation on GaAs substrate is also studied by XPS. Ga 2p spectra in figure 2.17 (A) are taken from GaAs surface after DHF clean and HfO 2 deposition with or without AlN passivation. The Ga-As peak and Ga-O peak are separated as shown in figure 2.17 (B) for the sample without AlN passivation and in figure 2.17 (C) for the sample with AlN passivation. It shows in figure 2.17 (B) that appreciable amount of GaO was formed during the HfO 2 depostion process without surface passivation. However, figure 2.17 (C) confirms that the formation of GaO during ALD HfO 2 process is effectively suppressed by thin AlN-passivation before the deposition of HfO 2. 47

65 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Ga 2p DHF+AlN+HfO 2 (A) Intensity [A. U.] DHF+HfO 2 DHF Binding Energy [ev] Ga 2P DHF+HfO 2 Ga-O Ga-As (B) Binding Energy [ev] Figure 2.17 (A) Ga 2p XPS spectra for GaAs after DHF clean and after ALD HfO 2 deposition with and without AlN-passivation; (B) Peak separation for Ga 2p signal from the sample without passivation after ALD HfO 2 deposition; 48

66 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Ga 2P DHF+AlN+HfO 2 Ga-As (C) Ga-O Binding Energy [ev] (D) As-Ga As 3d Intensity [A.U] DHF+AlN+HfO 2 DHF+HfO 2 DHF Binding Energy [ev] Figure 2.17 (C) Peak separation for Ga 2p signal from the sample with thin AlN passivation after ALD HfO 2 deposition; (D) As 3d XPS spectra for GaAs after DHF clean and after ALD HfO 2 deposition with and without AlN-passivation; 49

67 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Similarly, the formation of AsO after HfO 2 deposition was also suppressed by using AlN surface passivation as shown in figure 2.17 (D). The XPS analysis for Si passivated samples showed that Si protects the GaAs from being oxidized during the HfO 2 deposition process. Since AlN and Sipassivation layers act as an oxygen barrier, they are effective in minimizing the GaO and AsO formation during the ALD HfO 2 process, resulting in improved C-V Electrical Characteristics High-frequency C-V characteristics of TaN/HfO 2 /GaAs (p- and n-type) stack with different passivation techniques are shown in figure The abnormal lowfrequency behavior of high-frequency inversion C-V, usually observed for high-k/ge system [38], was not observed for both p- and n-mos GaAs capacitors. Both n- and p-gaas capacitors show good accumulation characteristics implying the absence of interface pinning between GaAs and HfO 2. The EOT for each capacitor is also marked in the graph by quantum mechanical C-V simulation. Figure 2.19 shows the extracted V fb and theoretical V fb of these devices. The theoretical V fb (ignoring the charge effects) is defined by the following equation [39]: V fb =W m -W s (2.1) 50

68 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application C (ff/μm 2 ) nm 3.1nm 3.6nm HfO 2 : 5nm PN AlN Si V g (V) 3.15nm 100KHz 3.2nm 4.05 nm Figure 2.18 C-V curves of both TaN/HfO 2 /p- & n-gaas stack using PN, AlN- and Sipassivation techniques. EOT is indicated in the figure. In the above equation, W m denotes the work function of the metal (gate electrode) and is taken as 4.4eV for TaN in our calculation [40]. W s is the work function of semiconductor substrate which can be expressed as n-sub: Ws= qχ+ qktln(n D /N i ) (2.2) p-sub: Ws= qχ+ qktln(n A /N i )+Eg/2 (2.3) q is the electronic charge and equals to C; χ is the electron affinity; K is Boltamann s constant (= J/K) and T is temperature; N D and N A are donor and acceptor concentration in the semiconductor substrate, respectively; N i and E g are the intrinsic carrier density and band gap of the semiconductor. Since the doping concentration in the GaAs substrate provided by the wafer vendor extends over a 51

69 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application range rather than a fixed value, so the theoretical value Vfb also has a distribution as shown in figure V fb for PN passivated samples is close to theoretical value, implying its low fixed charge density. Deviation of V fb for AlN-passivated and Si-passivated samples is attributed to the Al&N induced fixed charges and the doping effects of Si on GaAs. 1.5 Flatband Voltage (V) Theoretical V fb for n-sub GaAs Capacitor n-sub GaAs p-sub GaAs Theoretical V fb for p-sub GaAs Capacitor -1.5 Si+HfO 2 Si+Al 2 O 3 PN+HfO 2 AlN+HfO 2 Figure 2.19 Flat band voltage extracted from TaN/HfO 2 /GaAs stack using PN, AlNand Si-passivation techniques, the theoretical V fb is also plotted as reference. Gate leakage current density at V g = V fb +1V as a function of EOT for TaN/HfO 2 /GaAs stack is shown in figure 2.20, and compared with previously reported HfO 2 /Si, HfO 2 /Ge and SiO 2 /Si results. Although the leakage current level of GaAs capacitors is acceptable for high performance CMOS device application, results show that in order to achieve further EOT scaling and lower leakage current, the gate integrity and interface quality of high-k/gaas stack should be further improved and optimized. 52

70 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application 10 2 Si Passivation 10 0 SiO 2 /Si Plasma Nitridation AlN Passivation J g (A/cm 2 ) TaN/HfN/ HfO 2 /Si [41] HfO 2 /Ge [42] EOT (nm) High-K: HfO 2 Figure 2.20 Gate leakage current density as a function of EOT for TaN/HfO 2 /GaAs stack. Reported results for HfO 2 /Si, HfO 2 /Ge and SiO 2 /Si are compared. The interface state density (D it ) of GaAs devices is estimated by conduction method [43], and summarized in table 2.2. D it level of GaAs MOS-capacitors at midgap is in the range of ~ ev -1 cm -2. Table 2.2. Interface state density (D it ) estimated by conduction method for TaN/HfO 2 /GaAs stack with different passivations. Passivation PN Si AlN D it (cm -2 ev -1 ) 3.59E E E10 53

71 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application TEM of Gate stack TEM pictures of TaN/HfO 2 /GaAs stack with PN, AlN-, and Si-passivations after FGA at 400 o C are shown in figure Smooth interfacial layers and conformal HfO 2 layers are observed. The out-diffusion of Ga and As into HfO 2 was not detected by EDX (Energy Dispersive X-Ray) analysis. (A) (B) 54

72 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application (C) Figure TEM pictures of TaN/HfO 2 /GaAs stack with (A) plasma nitridation (B) AlN-passivation, and (C) Si-passivation Thermal Stability EOT (nm) J g (A/cm 2 ) 3.2 W/O FGA FGA 500 o C FGA 600 o C PMA 850 o C 10-6 Figure 2.22 EOT and gate leakage current density after thermal tests for TaN/HfO 2 /GaAs capacitor with Si passivation. 55

73 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Thermal stability of GaAs devices are studied by investigating the EOT, J g and C- V after FGA at 500 o C, 600 o C for 10 mins, and PMA at 850 o C for 1 min. As shown in figure 2.22, the EOT increases as annealing temperature increases due to the interfacial layer growth. It must be noted that the leakage current also increases after anneal, which is attributed to the crystallization of HfO 2 after anneal, as shown in TEM (figure 2.23), and the out-diffusion of Ga and As into HfO 2 with main diffusion of As, which is also confirmed by EDX. Figure 2.23 TEM and EDX of the GaAs sample with Si passivation after PMA 850 o C anneal, EDX shows diffusion of Ga and As into HfO 2. Figure 2.24 shows the normalized C-V characteristics for Si-passivated sample after FGA and PMA. The degradation of the interface quality is observed with stretch-out of the C-V with increased annealing temperature. 56

74 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application C/Cox 1.0 W/O FGA FGA 500 o C FGA 600 o C PMA 850 o C V g (V) Figure Normalized C-V characteristics for TaN/HfO 2 /GaAs stack with Sipssivation after post-metal annealing. On the other hand, after FGA at 600 o C, no obvious C-V stretch-out is observed for PN and AlN-passivated GaAs capacitors (figure 2.25). Slight reduction in leakage current is observed after FGA (inset), unlike Si-passivated device in figure 2.22, possibly due to the increase of interfacial layer without diffusion of Ga/As. Frequency dispersion of the C-V characteristics for Si and AlN-passivated GaAs samples after FGA is compared in figure AlN-passivated sample shows much lower frequency dispersion, indicating its good interface quality after the thermal treatment, due to the robustness of AlN diffusion barrier, effectively preventing Ga and As from diffusing into HfO 2 dielectric. 57

75 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application 1.2 (A) C/Cox PN With HfO J g (A/cm 2 ) V g (V) 0.2 W/O FGA FGA 500 o C 0.0 FGA 600 o C V g (V) C/Cox (B) J g (A/cm 2 ) V g (V) V g (V) W/O FGA FGA 500 o C FGA 600 o C AlN with HfO 2 Figure (A) Normalized C-V characteristics for TaN/HfO 2 /GaAs stack with PNpassivaiton, and (B) Normalized C-V characteristics for TaN/HfO 2 /GaAs stack with AlN-passivation; inset is gate leakge currenty density. 58

76 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application C (ff/um 2 ) (A) 1M 100K 10K 3 Si+HfO 2 2 after FGA o C V g (V) C (ff/um 2 ) AlN+HfO 2 After FGA 600 o C 1M 100K 10K (B) V g (V) Figure 2.26 Frequency dispersion after FGA at 600 o C for 10 minutes for TaN/HfO 2 /GaAs stack with (A) Si-passivation and (B) AlN-passivation. 59

77 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application GaAs n-mosfet with AlN-HfO 2 GaAs n-mosfet was also fabricated using AlN-HfO 2 /TaN gate stack. After the TaN gate definition, a thin SiO 2 sacrifice layer was deposited on the wafer before implantation. Two-step implantation was used in our experiment: first Si was implanted at an energy of 50 Kev with a dose of /cm 2 followed by P implantation with an energy of 60 Kev and a dose of /cm 2. The Si can replace either Ga atom or As atom in GaAs as donor or acceptor [44], respectively. Assume the number of Si atom replacing Ga atoms is denoted as N Ga and the number of Si atom replacing As atom is expressed as N As, then the total activation percentage can be calculated using the following equation: Si activation percentage= (N Ga -N As )/N (2.4) N is total number of Si atoms implanted. The purpose to introduce P implantation is to reduce the number of N As since P can occupy the As vacancy sites [45], hence the activation percentage can be possibly enhanced. After the implantation, a 100 nm SiO 2 layer was deposited on the wafer to protect the As & Ga atoms from diffusion or sublimation [46] during the subsequent activation process, which was done in a RTA chamber at 750 o C for 1 minute under N 2 environment. Subsequently, front contact metals AuGe(80nm)/Ni(10nm)/Au (200nm) and back contact metals Ti(10nm)/Pd(20nm)/Au(300nm) were deposited by e-beam evaporation. Finally, silicidation was carried out at 360 o C for 1 minute in N 2. The following figure 2.27 shows the relationship between J junction (Junction Current Density) and voltage applied at the N + side of the fabricated N + P GaAs junction by this Si and P co-implantation method. A J forward /J reverse (Junction forward current density/junction reverse current density) ratio of 10 7 is achieved. 60

78 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Figure 2.28 (A) shows the I s -V g curve from the GaAs n-mosfet using AlN passivation and HfO 2 as gate dielectric at a drain bias of 0.05V and 1.2V. Channel length of the device is 20 μm. The threshold voltage of the transistor is 0.309V, extracted by the maximum conductance method. A I on /I off (On current/off current) ratio of 6 orders is obtained. The S.S of the device is 129 mv/dec. Well-behaved I s -V d curves of the GaAs n-mosfet are also presented in figure 2.28 (B) Annealing condition: 750 o C 1 minute J junction (A/cm 2 ) co-implanation: Si 1E14 50kev P 1E15 60kev V (V) Figure 2.27 Junction current versus voltage applied at N + side of N + P GaAs junction; a two-step Si and P co-implantation is used and the activation temperature is 750 o C; a I forward /I reverse ratio of 10 7 is achieved. 61

79 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application I s (μa/μm) V d = 1.2V W/L = 320 μm / 20μm V th = 0.309V V g (V) V d = 0.05V S.S=129 mv/dec (A) W/L = 320μm / 20μm Vg-Vth= 0 to 1.2V Step=0.3V (B) I s (μa/μm) V d (V) Figure 2.28 (A) I s -V g of GaAs n-mosfet, (B) I s -V d of the GaAs n-mosfet 62

80 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application Conclusion Novel surface passivation on GaAs using plasma nitridation and AlN-passivation l has been carried out. Results show that robust passivation layers can be achieved at HfO 2 /GaAs interface, leading to good C-V characteristics on both n- and p-type GaAs with low leakage current. It is also found that plasma nitridation and AlN-passivation are more thermally stable than Si passivation. In addition, by using AlN passivation, GaAs n-mosfet integrated with AlD-HfO 2 /TaN was demonstrated. 2.3 Summary In this chapter, passivation techniques for Ge (AlN passivation) and GaAs (AlN and PN passivation) are explored. As shown by XPS results, the passivation layer is effective in reducing the interfacial oxides during the high-k deposition process, resulting in improved performance of the MOS devices. Thermal stability study was also carried out. The results indicate that Ge and Ga/As atoms easily diffuse into highk gate dielectric at elevated temperature, causing high leakage current and performance degradation. The proposed passivation techniques can improve the thermal stability of the devices by effectively retarding and preventing this diffusion process. B using AlN passivation, Ge n- & p-mosfets and GaAs n-mosfet are demonstrated. 63

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84 Chapter 2: Surface Passivation for Ge and GaAs substrates for MOS Device Application [28] Y.L. Huang, P. Chang, Z.K. Yang, Y.J. Lee, H.Y. Lee, H.J. Liu, J. Kwo, J.P. Mannaerts and M. Hong, Thermodynamic stability of Ga 2 O 3 (Gd 2 O 3 )/GaAs interface, Appl. Phys. Lett. Vol. 86, (2005); [29] P. D. Ye, G.D. Wilk, B. Yang, J. Kwo, S.N.G. Chu, S. Nakahara, H.-J.L. Gossmann, J.P. Mannaerts, M. Hong, K.K. Ng, and J. Bude, GaAs Metal-Oxide- Semiconductor field-effect transistor with nanometer-thin dielectric grown by atomic layer deposition, Appl. Phys. Lett., vol.83, p.180 (2005); [30] Y.Q. Wu, H.C. Lin, P.D. Ye and G.D. Wilk, Current Transport and Maximum Dielectric Strength of Atomic-Layer Deposited Ultrahin Al 2 O 3 on GaAs, Applied Physics Letters, 80, p (2007); [31] K. Rajagopalan, R. Droopad, J. Abrokwah, P. Zurcher, P. Fejes, M. Passlack, 1- um Enhancement Mode GaAs N-Channel MOSFETs with Transcondance Exceeding 250 ms/mm, IEEE Electron Device Letters, vol.28, p.100 (2007); [32] S. Koveshnikov, W. Tsai, I. Ok, J.C. Lee, V. Torkano, M. Yakimov, and S. Oktyabrsky, Metal-oxide-semiconductor capacitors on GaAs with high-k gate oxide and amorphous silicon interface passivation layer, Appl. Phys. Lett., vol.88 (2006); [33] M.M. Frank, G.D. Wilk, D.Starodub, T. Gustafsson, E. Garfunkel, and Y.J. Chabal, HfO 2 and Al 2 O 3 gate dielectrics on GaAs grown by atomic layer deposition, Appl. Phys. Lett., vol. 86 (2005); [34] H.-S. Kim, I. Ok, M. Zhang, C. Choi, Y. Lee, F. Zhu, G. Thareja, L. Yu, and Jack C. Lee, Ultrahin HfO 2 (Equivalent Oxide Thickness = 1.1 nm) Metal-Oxide- Semiconductor Capacitors on n-gaas Substrate With Germanium Passivation, Applied Physics Letters, 88, p (2006); [35] H.-S. Kim, I. Ok, M. Zhang, T. Lee, F. Zhu, L. Yu, and Jack C. Lee, S. Koveshnikov, W. Tasi, V. Tokranov, M. Yakimov, and S. Oktyabrsky, Depletion- 67

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87 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate Chapter 3 Fabrication of High-Mobility Channel on Insulator Substrate 3.1 Introduction As discussed in chapter 1, SOI structure provides better scalability than the bulk structure MOSFET because of its better immunity to short channel effect, reduced parasitic junction capacitance and free of latch-up. The methods for Si SOI substrate fabrication have been pursed for many years. Commonly used techniques for Si SOI fabrication include SIMOX (Separation by Implanted Oxygen) [1], wafer bonding & etch back [2] and Smart-Cut [3]. Research on high mobility semiconductor (SiGe, Ge and GaAs) on insulator substrate fabrication is still in its incipient stage, however it is gaining more and more attention because of the scaling limitations for Si based MOSFET mentioned in the introduction chapter. Although there is still no demonstration of GaAs on insulator, several methods for GOI (Germanium On Insulator) and SGOI (Silicon Germanium On Insulator) fabrication have been reported including: intermixing [4], SIMOX [5], wafer bonding [6], and condensation [7, 8]. Intermixing of amorphous Ge on SOI by high temperature annealing was only suitable for low Ge percentage SGOI fabrication and detailed studies have to be made to get SiGe with targeted Ge percentages. The process of SIMOX is also not suitable for SGOI fabrication with a Ge concentration higher than 30% [9]. Wafer bonding technique to form SGOI or GOI is limited by its process complexity and interface disorder [5]. Thin SGOI and GOI are difficult to be achieved by wafer bonding without chemical mechanical polishing to thin down the SiGe or Ge layer. In this context, Ge condensation has drawn great attention due to its 70

88 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate simple process steps and easy control over Ge concentration. Using condensation technique by oxidizing the epitaxially grown single crystal Si 1-X Ge X with low Ge concentration on Si SOI wafer, it is easy to achieve thin SGOI, GOI layers with uniform Ge composition and sharp interfaces. However, this condensation method is still far from perfect for production in terms of integration and cost: 1) localized GOI structure on Si substrate is desired for integration purpose, since Ge channel is suitable for high performance application but not attractive for low standby power application due to its high leakage. Hence, for SOC (system on chip) technology, only parts of the chips use Ge as conducting channel while others may still rely on Si; 2) MBE (Molecular Beam Epitaxy) or UHVCVD (Ultra High Vacuum Chemical Vapor Deposition) Epitaxy growth of Si 1-x Ge x on SOI in conventional condensation method is expensive (both the process and equipment), and a cost effective method is yet to be developed. More exploration is needed in this area to provide solutions for the above mentioned issuess. Hence this chapter is focusing on high mobility channel on insulator substrate fabrication. Firstly, SPE (Solid Phase Epitaxy) technique to form localized GOI structure is investigated. Then in the second half of this chapter, a cost effective novel condensation method to form high Ge concentration SGOI substrate is discussed. 3.2 SPE to Form Localized GOI Concept of Localized GOI Formation The vertical epitaxial growth is well known for both homoepitaxial and heteroepitaxial such as Si on Si, Ge on Si or GaAs on Ge [10, 11]. If the epitaxial growth can be extended laterally over an insulator, the localized SOI structure can be 71

89 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate achieved. The concept of using SPE lateral growth to achieve localized GOI is illustrated in the figure 3.1. A layer of amorphous Ge is deposited on the pre-patterned Si substrate. The open area where the Ge reaches the Si substrate is called the seed region. The amorphous Ge layer can regrow epitaxially upon annealing, starting from the seed region and following the crystal direction of the Si substrate. The epitaxial growth would propagate laterally over the SiO 2 and localized GOI structure can be formed. The advantage of this lateral growth for lattice mismatched substrates is that the defects are confined in the seed area by the side wall of the insulator with the lateral growth layer defects-free [12]. This method is process simple and compatible with standard Si MOSFET manufacturing process. Figure 3.1 Concept of using SPE lateral growth to form localized GOI structure, the open window on the Si substrate is called seed region where the epitaxial growth of Ge will be initialized Experiment 72

90 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate P type Boron doped Si (100) wafer was first dipped in dilute HF to form clean surface. In order to fabricate GOI, SiO 2 was grown by thermal oxidation, followed by selective SiO 2 etching to open the seed windows. Then Ge film was deposited on the wafer by DC sputtering. Subsequently, a layer of SiO 2 was deposited by plasma enhanced CVD (Chemical Vapor Depositon) to cover the Ge surface in order to minimize Ge evaporation during the post annealing process. FA (Furnace annealing) and RTA (Rapid Thermal Annealing) of these samples were done at various temperatures and all anneals were carried out in N 2 ambient under an atmosphere pressure. The following figure 3.2 shows the process flow for the experiment. (A) SiO 2 SiO 2 (B) 73

91 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate Ge SiO 2 SiO 2 SiO 2 (C) Figure 3.2 Process flow for SPE GOI growth, (A) a layer of SiO 2 was grown by thermal oxidation; (B) selective etch of SiO 2 to open seed windows; (C) a layer of Ge was deposited by DC sputtering and covered by a layer of SiO 2, followed by thermal annealing Results and Discussion Seed Region Analysis Figure 3.3 shows the θ -2θ XRD (X-Ray Diffraction) scans of seed region after different anneal conditions: FA at 600 for 2 hours, FA at 800 for 2 hours and RTA anneal at 940 for 4 seconds. The Si (400) peak is observed at 2θ=69.2 degree. It is reported that Ge (400) peak lies at 2θ=64 degree [13]. We note that for the sample annealed for 2 hours at 600, no other peak is observed except Si (400) in θ - 2θ scan, indicating the absence of Ge (400) or SiGe (400) planes that are orientated epitaxially with the underlying Si (001) substrate. This implies that the temperature of 600 o C could be too low to initiate the SPE of Ge on Si substrate. In case of the sample annealed at the 940, a temperature above the melting point of Ge, a low intensity peak is observed at 2θin a range between 65 and 67 degree. This low intensity hump is due to partial crystallization of the amorphous Ge layer that has (004) planes orientation parallel to the underlying substrate. The low intensity can be probably due 74

92 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate to short annealing time of 4 seconds. On the other hand, XRD data of the sample annealed at 800 for 2 hours shows a higher peak which is because of thicker more complete crystallization of amorphous Ge formed during 2 hours anneal. Unlike Si peak, the peak of Si 1-x Ge x has wider distribution mainly because of continuous change of the x (Ge composition) in the film together with the strain contained in the film [14] Si(400) XRD Intensity [A.U.] 10 8 Si X Ge 1-X (400) 10 7 Ge(400) C, 2Hours C, 2Hours C, 4S Diffration Angle 2θ Figure 3.3 XRD intensities versus 2θfrom the seed area for three samples annealed at different conditions: FA at 800 for 2 hours, FA at 600 for 2 hours, RTA at 940 for 4 seconds. High resolution TEM (Transmission Electron Microscope) of the samples annealed at 600 for 2 hours and 800 for 2 hours are shown in figure 3.4. The interface is clearly observed for the sample annealed at 600 as indicated in figure 3.4 (A). The top Ge film is the mixture of amorphous and poly-crystallized Ge, which is confirmed by the SAD (Selected Area Diffraction) pattern inserted in figure 3.4 (A). 75

93 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate Large defects clusters within the Ge film are observed. It is also noted that the crystal orientation of the Si and Ge is misaligned, indicating Ge growth is not epitaxial growth but likely due to random nucleation. HRTEM of the sample annealed at 800 shows that top ~150Å layer is single crystal Si 1-x Ge x with x in a range of ~0.3 to ~0.7. The formation of single crystal Si 1-x Ge x layer on Si can be explained by two aspects: one is due to the top Ge diffusion to the Si substrate, the other is the epitaxial growth of Ge film from the Si substrate. The original interface of Si and Ge is believed in the starting point of the thread dislocations as shown in figure 3.4 (B). The threading dislocation is caused because of the misfit strain. Since the Ge diffusion to the Si may not cause the thread dislocation in Si substrate, the single crystal Si 1-x Ge x above the interface would be initiated by the Ge SPE growth following the crystal orientation of Si-substrate GOI Structure GOI structure is realized and shown in figure 3.5 (A). The annealing condition for this sample is 800 for 2 hours in N 2 ambient. It is observed that growth of single crystal Ge propagates from the seed region to the top of the SiO 2. Although defects and dislocations in the Si 1-x Ge x film in the seed region are observed, the GOI structure is of good quality with clear crystal image visible. The lateral dimension of the single crystal Ge is 20 µm. The SAD pattern in figure 3.5 (B) confirms that the Ge film on top of SiO 2 is of single crystal and has the same crystal orientation as that of Si substrate. 76

94 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate A Misalign Defects Ge Si Interface B Ge 70.3% Si X Ge 1-X Ge 68.4% SiXGe1-X Ge 33% Interface Interface Thread Dislocation Silicon Figure 3.4 (A) HRTEM picture of the sample annealed at 600 for 2 hours, inserted plot is the SAD pattern. (B) HRTEM picture of the sample annealed at 800 for 2 hours. 77

95 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate Ge film A SiO 2 Seed Area 5 nm Si Sub B Ge Si 0.01 nm Figure 3.5 (A) High resolution TEM picture of single crystal GOI structure. (B) SAD pattern indicates that the Ge film on insulator is single crystal. 78

96 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate Conclusion XRD and TEM are used to examine the process of Ge SPE on Si substrate which suggest that the temperature of 600 o C is too low to initiate the process. SPE growth of Ge on Si substrate at elevated temperature of 800 o C is clearly observed. By annealing the amorphous Ge deposited on pre-patterned Si substrate at 800 o C to initiate the SPE process, localized GOI structure on Si substrate is achieved due to lateral growth. Localized GOI structure made by this method is promising for integration of highmobility Ge MOSFET on Si substrate for SOC application. 3.3 Condensation of amorphous SiGe Film on SOI substrate to form SGOI In the first section of this chapter, localized GOI structure on Si is demonstrated by SPE method; and in this section we will discuss a novel cost effective condensation approach to fabricate SGOI substrate with high Ge percentage Condensation Mechanism It was reported that oxidation of SiGe film at high temperature results in growth of pure SiO 2 layer with Ge piling up behind it [15-17]. The phenomena can be explained by the displacement chemical reaction between GeO 2, and Si, which can be written as: GeO 2 + Si=SiO 2 +Ge [18] This reaction is found to be possible at high temperature of 800 o C. Hence during the oxidation of SiGe layer on Si SOI substrate at a high enough temperature, with ample supply of Si from the substrate, GeO 2 can be converted to pure Ge with only SiO 2 formed. In addition, the out diffusion of Ge atoms is suppressed by the top oxide and 79

97 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate BOX (Buried Oxide) layer. Therefore, the total amount of Ge in the SiGe layer will be preserved during the oxidation process. Because Si is consumed during the oxidation, the Ge concentration in the remaining film can be enhanced. That s why the process is called condensation. Suppose that the initial thickness of SiGe layer and percentage of Ge concentration is t 1 and c 1, respectively; and after the oxidation or condensation process, the thickness and concentration of Ge become t 2 and c 2. With little Ge element loss, the following equation should hold. t 1 c 1 =t 2 c 2 (3.1) The following figure 3.6 depicts the Ge condensation process. It should be pointed out that in the conventional condensation process, the SiGe layer is prepared by epitaxial growth and the layer is in single crystal structure with the same orientation as the SOI wafer. However, in figure 3.6 (this experiment) the initial SiGe is in its amorphous state (α-sige) which is deposited by sputtering. The mechanism that the amorphous SiGe can be converted to single crystal structure is due to Ge diffusion and SPE discussed in the first part of this chapter. (A) 80

98 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate (B) Figure 3.6 Process for condensation of amorphous SiGe on SOI wafer to form single crystal SGOI substrate:(a) a amorphous low Ge content SiGe layer was deposited on a SOI wafer; (B) after high temperature oxidation process, due to condensation, SPE mechanisms, high Ge concentration single crystal SGOI was formed between the BOX and top SiO 2 layer; (C) top SiO 2 layer etch (C) Experiment P type Boron doped SOI wafers were used as starting substrates in this experiment. The thickness of Si-on-insulator layer was thinned down to ~80 nm by thermal oxidation and DHF etching. Then the SOI wafers were loaded into a sputter chamber with a base pressure of torr. ~100 nm SiGe film was deposited on the wafers by co-sputtering of the pure Si and Ge targets in Argon plasma at a base pressure of 3 mtorr. The thickness was calculated by multiplying the sputtering rate with the sputtering time. The RF powers applied to the Si and Ge targets were tuned 81

99 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate so that the final deposited SiGe film contains 20-30% of Ge. The as-deposited samples were then oxidized in an oxidation furnace. The oxidation process was first done at a higher temperature at 1050 o C until the Ge percentage in the film reaches ~ 50%, and after removing the top oxide layer, further oxidation was carried out at a lower temperature below 1000 C to ensure that the SiGe film does not melt during the whole oxidation process. Finally the top oxide layer was removed by DHF after the two-step oxidation process. To investigate the structural properties and quality of these fabricated SGOI layers, TEM, EDX, micro-raman and HR-XRD (High- Resolution XRD) measurements are carried out Results and discussion Amorphous SiGe layer On SOI Figure 3.7 shows the auger depth profiling of the as-deposited sample before any oxidation process. The inset shows the sample structure. Such depth profiling confirms the presence of a thin SiGe film deposited on single crystal SOI surface. The average Ge atomic concentration is ~25%. O and C singles are also observed, which are likely due to native oxide layer and the surface contamination since cleaning process was not done immediately before the analysis Crystal Quality and Composition of SGOI Figure 3.8 shows the high resolution TEM image of the SGOI sample after twostep oxidation. The film thickness is found to be ~43.4 nm with a uniform Ge atomic percentage of 60%. This composition profiling is carried out using EDX analysis. Considering the initial SiGe layer with a thickness of ~100 nm and Ge percentage of ~25%, the results testify equation (3.1) confirming that Ge element is preserved 82

100 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate during our condensation process. In addition, TEM images also show the presence of twin defects as shown in the inset (A) of figure 3.8. The inset (B) in figure 3.8 shows the FFT (Fast Fourier Transform) image of the SGOI film which indicates that the Si 0.4 Ge 0.6 film is single crystal nature though dislocations and defects are observed in the film. Atomic Concentraction (%) SiGe Si SiO 2 sputtered SiGe Sigle Crystal Si BOX Si-Sub Sample Structure 40 Ge Si 20 O C Ion Etching Time (S) Figure 3.7 Auger depth profiling of the as-deposited sample before any oxidation process; the inset (A) illustrates the structure of the sample; 83

101 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate (B) Si 0.4 Ge 0.6 Si 0.4 Ge 0.6 BOX 43.4nm Si 0.4 Ge 0.6 (A) Twin defect SiGe BOX Figure 3.8 High resolution TEM of the S 0.4 G 0.6 on insulator structure achieved after two step oxidation process. Inset (A) shows the twin defect observed in the SGOI, and inset (B) represents FFT image of the SGOI film; In order to probe the crystalline quality of these SGOI layers, micro-raman measurements are carried out. Raman spectra are recorded using a JYT6400 set up with a liquid nitrogen cooled CCD detector. The nm line of an argon laser is used as an excitation source, which gives a focused laser spot of 1.2 μm. The spectral resolution of the Raman set up is about 0.2 cm -1 and from the Raman peak analysis, the error values in the Ge composition is about ±0.5%. For this excitation wavelength, the penetration depth of the Raman probing is about nm and 8-10 nm for bulk Si and Ge, respectively [19]. Since the Ge composition in these SGOI films (thickness 43.4 nm) is expected about 60%, we can probe the whole SGOI layer along with the underlying Si (100) substrate. To probe the composition uniformity, Raman spectra are recorded from several positions of the SGOI surface. We have found out 84

102 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate that there is no significant change of the peak positions (average peak shift due to large area probing < ±1.5 cm -1 ) and linewidth. The Raman Spectra of as deposited sample before any oxidation and the sample after the two-step oxidation are shown in figure 3.9. For the as deposited sample, only Si-Si peak from SOI is observed implying that the deposited SiGe film by co-sputtering is of amorphous nature. This is evident from the much broader background signal due to absence of long-range order. In case of the sample after oxidation, besides the intense Si-Si peak from the SOI substrate, Si-Si, Si-Ge and Ge-Ge related vibrations from the Si 1-X Ge X film are clearly observed. The Si-Si peak from the SiGe shows substantial phonon softening with a broad low-energy tail when compared to reference peaks recorded from single crystalline strained and relaxed Si 1-X Ge X layers with Ge content > 35%. These observations reveal that the Ge content in our SGOI samples is much higher [20, 21]. In addition, linewidth of the Si-Ge and Ge-Ge peaks resembles the Raman lineshape of single-crystal high Ge-content SiGe films. Using the method described in Refs [20-25], we can also estimate a Ge composition > 64% in these films from the Raman peak shift where composition estimation is carried out with reference to the unstrained phonon frequency. Such a peak shift is compensated by the amount of in-plane lattice strain. In a similar way, we can also estimate an average in-plane strain component in these layers when compared to Raman peak shift of the unstrained bulk Si 1-x Ge x layers. It is found that the film after two-step oxidation process possesses 0.26% compressive strain. Such an amount of strain in SGOI layers is beneficial for the improvement of hole mobility [26]. 85

103 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate Intensity [A. U.] Ge-Ge After Two-step Oxidation As-deposited Si-Si (Sub) Si-Ge Si-Si (in SiGe) Raman Shift (cm -1 ) Figure 3.9 Raman spectra from the as-deposited sample and the sample after two-step oxidation; much narrower Raman modes associated with Si-Si, Si-Ge, and Ge-Ge vibration peaks reveal high crystalline quality XRD strain analysis of SGOI Since the amount of average in-plane strain given by Raman analysis is based on several approximations related to phonon peaks of compositional-dependent unstrained SiGe, we have carried out a comparative analysis using HRXRD. The anisotropy of the strain in the Si 1-x Ge x layer is deconvoluted by HR-XRD using the PANalytical X'Pert PRO Extended MRD system. The HR-XRD measurements were performed with line-focused Cu K α1 radiation (λ = Å) from a four-crystal Ge (220) monochromator which provides an angular divergence of < 12 arc-s with a wavelength spread Δλ/λ ω-2θ overview scans were obtained with a detector acceptance angle of 2, while an additional two-crystal Ge (220) analyzer 86

104 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate was placed between the sample and the detector to obtain high-resolution (detector acceptance angle 12 arc-s) scans and reciprocal lattice maps about both symmetric and asymmetric reflections. The maps are generated by taking repetitive ω-2θ rocking curve scans starting at different initial values for ω. The symmetric ω-2θ rocking curve scan of the SGOI film after two-step oxidation is shown in figure The peak at 2θ of 69.1 degree is from the Si (400). A combination of (004) and (224) reciprocal maps at orthogonal φ was used to isolate tilt effects, and the Ge percentage is calculated to be 61.1% which is in consistence with the concentration given by EDX. The lattice constant of the SiGe (both the in-plane X and Y directiona, refer to inset (A) of figure 3.10) calculated from the reciprocal space map is 5.536Å, while the out-of-plane lattice constant of SiGe in Z direction is 5.594Å. According to Vegard s law [27], The lattice constant for single crystal Si 1-x Ge x can be written as: a Si1-xGex = (1-x)a Si +xa Ge (3.2) where, x denotes the atomic percentage of Ge in SiGe alloy, and a i is the lattice constant for material i. Hence, a fully relaxed SiGe crystal with a Ge percentage of 61.1% would have a lattice constant of 5.569Å. Therefore, in X and Y directions, the SGOI film involves 0.59% compressive strain whilst in Z direction, the SGOI film involves 0.45% tensile strain. It is believed that the overall effect of these strains would improve the performance of the p-mosfet [28, 29]. The difference in the strain values estimated from Raman and XRD could be due to difference in the probing area and depth. In literature, the phonon deformation potential constants for SiGe with Ge composition higher than 50% are not well established. Such limitations may also lead to a large fluctuation in the strain values in SGOI probed by Raman technique. 87

105 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate 10 7 Z Si (400) XRD Intensity [A. U.] Y (A) SiGe BOX SiGe X Diffraction Angle 2θ (degree) Figure 3.10 XRD scans of SGOI sample after two-step oxidation process. The Si and SiGe diffraction peaks are used for Ge composition estimation Cyclic Anneal Effect It is reported that cyclic anneal process is effective in reducing the defect and dislocation density in Ge film epitaxially grown on Si [30], by mechanisms such as dislocation glide and annihilation [31]. In this study, the effect of cyclic anneal on the quality of SGOI is also investigated. The Si 0.4 Ge 0.6 -on-insulator wafer prepared by two-step oxidation received 5 cycles of anneal between a high annealing temperature (900 ) for 10 minutes and a low annealing temperature (760 ) for 10 minutes. The temperature profile of the anneal process is shown in the following figure

106 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate T ( o C) one anneal cycle t (minutes) Figure 3.11 Temperature profile for the cyclic anneal process for SGOI substrate, two cycles are shown in the graph. Figure 3.12 shows the TEM picture of the SGOI sample after this thermal treatment which confirms that the quality of the film is improved by cyclic anneal. In addition, no twin defects were observed after the cyclic anneal as shown in the inset (A) of figure The inset (B) and inset (C) of figure 3.12 represent FFT image and the diffraction pattern of Si 0.4 Ge 0.6 film, respectively, which confirm the single crystal nature of the film. In addition, as shown in figure 3.13, there is no obvious Raman peak shift after the cyclic anneal, which implies that the SGOI film still retains its original strain. By using this novel condensation method, SGOI with thickness as thin as 20 nm is achieved as shown in figure This substrate can be used for fully depleted SGOI MOSFET fabrication. 89

107 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate SiGe BOX (A) (B) Si 0.4 Ge nm (C) BOX Figure 3.12 High resolution TEM of the S 0.4 G 0.6 on insulator structure after cyclic Thermal treatment; no twin defect is observed in the SGOI film as shown in inset (A); inset (B) represents an FFT image; and diffraction pattern of the SGOI film shown in inset (C) reveals single crystalline phase. Ge-Ge Ge-Si Si-Si (SiGe) Si-Si (Sub) In tensity [A.U] SGOI Before Cyclic Anneal SGOI After Cyclic Anneal Raman Shift (Cm -1 ) Figure 3.13 Raman Analysis showing that the strain in SiGe on insulator is maintained after the cyclic anneal. 90

108 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate Figure 3.14 thin SGOI achieved with thickness of 20 nm Conclusion In summary, strained Si 0.4 Ge 0.6 on insulator has been successfully demonstrated by oxidation of SiGe amorphous films deposited on SOI wafers by co-sputtering pure Si and Ge targets. The Ge composition is quite uniform in the film and the Ge concentration estimated by EDX is consistent with calculation from the XRD spectrum. The amount of strain in the Si 0.4 Ge 0.6 film is characterized by both Raman and XRD techniques. It is found the strain in the Si 0.4 Ge 0.6 is beneficial for p- MOSFET. In addition, a cyclic annealing process can further improve the quality of SGOI. SGOI wafer with SiGe layer as thin as 20 nm is also achieved. Such a cost effective and process simple method can be used to prepare high Ge-content SGOI and Ge-on-insulator substrates for high performance MOSFETs. 91

109 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate 3.4 Summary In this chapter, fabrication methods for high mobility channel on insulator substrate are investigated. Localized GOI structure on Si substrate is realized by Ge SPE lateral growth on pre-patterned Si wafer. Besides, by using cost effective novel condensation approach, high quality strained SGOI with high Ge percentage is achieved. 92

110 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate Reference [1] B. Aspar, C. Pudda, A.M. Papon, A.J. Aubertom-Herve, and J.M. Lamure, Ultra Thin Buried Oxide Layers Formed By Low Dose SIMOX Process, in S. Cristoloveanu, ed., Silicon-On-Insulator Technology and Devices, The Electrochemical Society, Proceedings Vol , p.62 (1994); [2] P.B. Mumola, and G.J. Gardopee, Advances in the Production of Thin-Film Bonded SOI and Ultra Flat Bulk Wafers Using Plasma Assisted Chemical Etching, Extended Abstracts of the International Conference on Solid-State Devices and Materials, p.256 (1994); [3] C. Maleville, B. Aspar, T. Poumeyrol, H. Moriceau, M. Bruel, A.J. Auberton- Herve, T. Barge, and F. Metral, Physical Phenomena Involved in the Smart-Cut Process, Silicon-on-Insulator Technology and Devices, VII, Pro. Electrochemical Society, Vol. 96-3, p.34 (1996); [4] K. Kutsukake, N. Usami, K. Fujiwara, T. Uhihara, G. Sazaki, K, Nakajima, B. Zhang, and Y. Segawa, Fabrication of SiGe-on-Insulator by rapid thermal annealing of Ge on Si-on-Insulator substrate, Applied Surface Science, 224, p.95 (2004); [5] S. Fukatsu, Y. Ishikawa, T. Saito, and N. Shibata, SiGe-based semiconductor-oninsulator substrate created by low-energy separation-by-implanted-oxygen, Appl. Phys. Lett., 72, p.3485 (1998); [6] G. Taraschi, A.J. Pitera, and E.A. Fitzgerald, Strained Si, SiGe, and Ge on- Insulator: Review of Wafer Bonding Fabrication Techniques, Solid-State Electron., 48, p.1297 (2004); [7] T. Tezuka, N. Sugiyama, and S.-i. Takagi, Dislocation-free relaxed SiGe-on- Insulator Mesa Structures Fabricated by High-Temperature Oxidation, Journal of Applied Physics, vol. 94, p.7553 (2003); 93

111 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate [8] S. Nakaharai, T. Tezuka, N. Sugiyama, Y. Moriyama, and S.-I. Takagi, Characterization of 7-nm-thick strained Ge-on-Insulator Layer Fabricated by Ge- Condensation technique, Applied Physics Letter, vol. 83, p.3516 (2003); [9] Y. Ishikawa, N. Shibata, and S. Fukatsu, Factors limiting the composition window for fabrication of SiGe-on-Insulator substrate by low-energy oxygen implantation, Thin Solid Film, 369, p.213 (2000); [10] E.A. Fitzgerald, Epitaxial Growth of GaAs/Ge Interfaces, Abstract of ECS 210 th Meeting, p.1460 (2006); [11] X. Chen, S. Joshi, J. Chen, T. Nagi, and S.K. Banerjee, MOS Capacitors on Epitaxial Ge-Si 1-x Ge x with High-k Dielectrics Using RPCVD, IEEE Transactions on Electron Devices, vol.51, p.1532 (2004); [12] T.A. Langdo, C.W. Leitz, M.T. Currie, E.A. Fitzgerald, A. Lochtefed and D.A. Antoniadis, High Quality Ge on Si by Epitaxial Necking, Applied Physics Letters, vol. 76, p.3700 (2000); [13] T.Numai, T. Koide, T. Minemoto, H. Takakura, and Y. Hamakawa, Lateral Graphoepitaxy of Germanium Controlled by Microholes on SiO 2 surface, Extended Abstract o fthe 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004, p.492 (2004); [14] J.-M. Baribeau, X-ray reflectometry study of interdiffusion in Si/Ge heterostructures, J. Appl. Phys., 74, p.3805 (1993); [15] O.W. Holland, C. White, and D. Fathy, Novel oxidation process in Ge+implanted Si and its effect on oxidation kinetics, Applied Physics Letters, vol. 51, p. 520 (1987); [16] F. K. LeGoues, R. Rosenberg, T. Nguyen, F. Himpsel, and B.S. Meyerson, Oxidation studies of SiGe, Journal of Applied Physics, vol. 65, p.1724 (1989); 94

112 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate [17] D. Nayak, K. Kamjoo, J.C.S. Woo, J.S. Park, and K.L. Wang, Rapid thermal oxidation of GeSi strained layers, Applied Physics Letter, vol.56, p.66 (1990); [18] Y. Maeda, Visible Photoluminescence from Nanocrystallite Ge Embedded in A Glassy SiO 2 Matrix: Evidence in Support of the Quantum-Confinement Mechanism, Physical Review B, vol. 51, p.1658 (1995); [19] D. E Aspnes, and A. A. Studna, Dielectric functions and optical parameters of Si, Ge, GaP, GaAs, GaSb, InP, InAs, and InSb from 1.5 to 6.0 ev, Phys. Rev. B 27, p.985 (1983); [20] B. Dietrich, E. Bugiel, H. J. Osten, and P. Zaumseil, Raman investigations of elastic strain relief in Si1 xgex layers on patterned silicon substrate, J. Appl. Phys. 74, p.7223 (1993); [21] J. C. Tsang, P. M. Mooney, F. Dacol, and J. O. Chu, Measurements of Alloy Composition and Strain in thin Ge x Si 1-x layers, J. Appl. Phys. Vol.75, p.8089 (1994); [23] M. L. Lee and E. A. Fitzgerald, M.T. Bulsara, M.T. Currie, and A. Lochtefeld Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors, J. Appl. Phys. 97, p.1 (2005); [24] S.J. Koester, K. Rim, J.O. Chu, P.M. Mooney, and J.A. Ott, M.A. Hargrove, Effect of Thermal Processing on Strain Relaxation and Interdiffusion in Si/SiGe Heterostructures Studied using Raman Spectroscopy, Applied Physics Letters, vol. 79, p.2148 (2001); [25] X.H. Zheng, H. Chen, Y.K. Li, Q. Huang, J.M. Zhou, Strained State of the Layer System depending on the SiGe Layer thickness by Micro-Raman Mapping, Journal of Crystal Growth, vol. 264, p.104 (2004); [26] H.-S.P Wong, Advanced CMOS Devices: Part I: Conventional Devices And Technology Options, Proceeding of Electrochemical Society , p.3 (2005); 95

113 Chapter 3: Fabrication of High-Mobility Channel on Insulator Substrate [27] C.K. Maiti, N.B. Chakrabarti, and S.K. Ray, Strained Silicon and Heterostructures: Materials and Devices, the Institute of Electrical Engineering, Lodon, (2001); [28] Y. Kanda, A Graphical Representation of the Piezoresistance Coefficients in Silicon, IEEE Transaction on Electron Devices, vol.29, p.64 (1982); [29] C.S. Smith, Piezoresistace Effect in Germanium and Silicon, Physical Review, vol.94, p.42 (1954); [30] H.C. Luan, D.R. Lim, K.K. Lee. K.M. Chen, J.G. Sandland, K. Wada, and L.L. Kimerling, High-quality Ge epilayers on Si with low threading-dislocation densities, Applied Physics Letters., vol. 75, p.2909, (1999); [31] G.E. Beltz, M. Chang, M.A. Eardley, W. Pome, A.E. Romanov, and J.S. Speak, A Theoretical Model for Threading Dislocation Reduction During Selective Area Growth, Materials Science and Engineering, A , p.794 (1997). 96

114 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D Chapter 4 High Mobility Channel MOSFET Integrated With High-k/Metal Gate and Schottky S/D 4.1 Introduction High mobility channel MOSFET integration Besides the issue of surface passivation discussed in chapter 2, integration of SiGe (with high Ge percentage) and Ge channel MOSFET with high-k gate dielectric and metal gate faces many other challenges. It is well known that the solid solubility of dopants in Ge is relatively low compared with that in Si [1]. Besides, dopant loss during the activation process and insufficient dopant activation in Ge substrate were reported [2]. These facts make realization of low resistance S/D (Source/Drain) in Ge MOSFET very difficult. With high S/D resistance, significant reduction of the transistor s drive current is expected [2, 3]. The S/D resistance issue will be more sever for thin body SGOI or GOI structure without S/D epitaxial extension. In addition, fast dopant diffusion in Ge during the activation process due to non-equilibrium effects such as transient enhanced diffusion poses tremendous challenges in forming shallow junction for highly scaled devices [4]. On the other hand, MOSFETs made on Ge or SiGe substrates usually suffer from high gate leakage especially after elevated temperature process, due to: 1) formation of poor quality Ge oxide interfacial layer [5], which will not only distort the C-V (Capacitance-Voltage) curve but will also lower the band offset of high-k to the 97

115 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D substrate resulting in higher gate tunneling current [6]; 2) the diffusion of Hf into the interfacial oxide/ge-substrate [7], 3) diffusion of Ge into the HfO 2 film (Chapter 1). Although passivation technique proposed in chapter 1 shows its effectiveness in minimizing the interfacial oxides formation and retarding the Ge diffusion process, low temperature fabrication for SiGe and Ge MOSFET is always desirable to minimize the degradation. However, commonly used dopant implanted S/D technology requires high temperature process to activate the impurities and repair the crystal damages caused by implantation process [8, 9], which limits its application in SiGe and Ge MOSFET. Therefore, low resistance S/D with low formation temperature is required to solve or as least alleviate the aforementioned concerns for integration of Ge and SiGe MOSFET with high-k and metal gate Schottky S/D Transistor Schottky S/D MOSFET has been proposed as an alternative to heavily doped S/D MOSFET [10]. The fundamental structure of Schottky S/D transistor is the same as the conventional doped S/D MOSFET. The difference is that in the Schottky S/D MOSFET, the S/D is formed by alloying the substrate with a metal to form a Schottky contact rather than using conventional ion implantation to form a PN junction. Therefore, the high temperature dopant activation process can be eliminated. Besides, since the S/D is metallic like germanides (silicides), resistance of the Schottky S/D can be greatly reduced. Figure 4.1 shows the structure of a Schottky S/D MOSFET. In the S/D side, the metallic like material forms a Schottky contact to the substrate. In operation mode, when the gate voltage and drain voltage are applied to the device, the electrons (for n- 98

116 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D MOSFET) or holes (for p-mosfet) will tunnel through the Schottky barrier from the source to the drain as shown in figure 4.2 [11, 12]. However, these carriers have to overcome a Schottky barrier height Φ b (normally we use Φ p for hole tunneling barrier in p-mosfet and Φ n for electron tunneling barrier in n-mosfet) before injected from the source to the channel. Figure 4.1 the structure of the Schottky S/D transistor, the S/D is a Schottky contact. Figure 4.2 (A) band diagram for p-mosfet, and (B) band diagram for n-mosfet [11, 12] 99

117 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D Therefore, the drain current depends on the value of Φ b and the channel resistance. For a high Φ b, the drain current depends mainly on the tunneling resistance, and for a lower Φ b, the drive current becomes almost the same as those of a conventional MOSFET, in which the drive current is determined by the channel resistance. Hence materials that can form low Φ p and Φ n are desirable for p-mosfet and n-mosfet application, respectively. So far, Schottky S/D transistors on bulk Si substrate or SOI with various metals have been demonstrated including Co [13], Dy [14], Er [15], Pt [14, 15]. Relative high barrier height is found on Si substrate. For example CoSi 2 has Φ n = 0.42 ev, PtSi has Φ p =0.24 ev and ErSi 1.7 has a Φ n =0.28 ev. The high barrier height may be overcome or at least alleviated by using Ge or SiGe substrate, because of their low band gap. Hence, in this chapter we will discuss the Schottky S/D transistor on high mobility substrate integrated with high-k gate dielectric and metal gate electrode. In the first part of this chapter, we will explore the Ni-germanide Schottky S/D p-mosfet on Si 0.05 Ge 0.95 /Si substrate; followed by the discussion on Schottky S/D transistor using Ni-germanosilicide on the thin SGOI wafer by a conventional self-aligned top gate process. 4.2 Schottky S/D MOSFET on Si 0.05 Ge 0.95 /Si Substrate Experiment Due to limited amount of Ge element on earth and its high cost, the Ge/Si (Ge on Si) architecture is proposed by several groups [16-18]. In this architecture, inversion channel of the MOSFET is formed in the high mobility material Ge, while relative cheap bulk Si acts as supporting substrate combining the merits of both. Hence, in 100

118 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D our experiment ~500 nm Si 0.05 Ge 0.95 was grown on Si substrate at Anelva Japan. A TEM (Transmission Electron Microscope) image of the substrate is shown in figure 4.3. The total thickness of the SiGe layer is found to be ~533 nm. EDX (Electron Dispersive X-ray spectroscopy) data confirms uniform Ge concentration in top 200 nm of the SiGe layer, with variation of Ge atomic percentage less than 0.5%. Due to large (4%) lattice mismatch between Si and Ge, misfit dislocations in the interface between the Si and SiGe layers are observed as indicated by arrows in figure 4.3 (B); however the dislocation density decreases as the thickness of SiGe increases, 500 nm SiGe is grown to ensure the top SiGe epitaxial layer of high quality for MOSFET application. After the preparation of the substrate, a SiO 2 sacrifice layer was deposited on the wafer followed by phosphorus channel implantation with ion energy of 110 KeV and a dose of /cm 2. The activation of the dopants was done at 800 o C for 10s. The purpose of this channel implantation is to turn the substrate into n-type semiconductor since during the SiGe gowth process, no extra dopants were introduced. Because no device structure had been formed on the sample, high temperature annealing can be used to activate the dopant and repair the implantation damage. After dipping in dilute HF to remove the SiO 2, the Si 0.05 Ge 0.95 /Si substrate was loaded into a sputter chamber. Subsequently, ultra-thin amorphous Si passivation layer was deposited on SGOI to suppress the GeO 2 formation [19], followed by pure Hf metal deposition by DC sputtering. Rapid thermal oxidation of the sputtered Hflayer on the substrate was done at 500 for 1 minute in a N 2 /O 2 ambient, after which the Hf metal can be converted into HfO 2 [20]. A ~150 nm TaN metal gate was deposited by reactive sputtering of Ta target in N 2 ambient. 101

119 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D (A) SiGe Dislocations Si-sub (B) Figure 4.3 (A) TEM picture of the Si 0.05 Ge 0.95 /Si substrate, the Ge concentration is detected by EDX, (B) High resolution TEM shows the interface between the Si-sub and epitaxially grown SiGe layer, arrows point out the misfit dislocation. However, the top SiGe layer is believed of high-quality single crystal, which is also verified by gate stack TEM (Figure 4.6). 102

120 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D After lithography and removal of the exposed photoresist, trimming of the photoresist was carried out to reduce the gate length of the transistor defined by the mask. The photoresist trimming process is illustrated in figure 4.4. Figure 4.4 (A) shows that after lithography and photoresist develop, the gate length (photoresist length) is L, which is defined by the dimension of the pattern in the mask. Subsequently, the wafer with attached photoresist was loaded into O 2 plasma chamber. As illustrated in figure 4.4 (B), in the O 2 plasma environment, the photo resist would be encroached by the O 2 both vertically and horizontally, resulting in reduced height and length. Finally, the photoresist with length L was achieved. By using this photoresist trimming method, the gate length of the transistor can be made much smaller than what was originally designed in the mask. However, the O 2 flow, plasma power and process time should be well controlled to ensure that the targeted length L can be achieved. After the photoresist trimming process in O 2 plasma, gate electrode metal TaN was removed by reactive ion etching in a Lam TCP9400 etcher, followed by photoresist stripping in asher. Then Si 4 N 3 spacer was deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition). Immediately after the spacer etching and DHF dipping to remove the oxides in the S/D area, pure Ni was deposited on the wafers by e-beam evaporator. Although it is found that Pt-germanide has more favorable hole barrier (Φ p = -0.1eV, Φ n =0.76eV) than that of Ni-germanide (Φ p = eV, Φ n = 0.74eV) by the reverse current measurement [21, 22], Ni was selected because of its easy removal. Schottky S/D was formed in a rapid thermal process chamber at 400 for 1 minute in N 2 ambient at atmosphere pressure. Finally, un-reacted Ni was removed by wet etching in 5% HNO 3 solution. 103

121 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D (A) (B) (C) Figure 4.4 Illustration of photoresist trimming process in O 2 plasma (A) photoresist after develop has a length of L, defined by the mask; (B) The photoresist is encroached by O 2 plasma in both vertical and horizontal directions; (C) Photoresist with smaller length L is achieved. 104

122 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D The whole process flow for the Ni-Schottky S/D MOSFET fabrication from the Si 0.05 Ge 0.95 /Si substrate preparation is summarized as follows: (1) Growth of Si 0.05 Ge 0.95 on Si substrate; (2) 10 nm sacrifice SiO 2 deposition; (3) Phosphorus channel implantation: implantation energy 110KeV and dose /cm 2 ; (4) Source/Drain activation at 800 o C for 10s; (5) DHF cleaning to remove the sacrifice oxide; (6) Thin Si passivation layer deposition by sputtering; (7) Pure Hf deposition by sputtering; (8) Post deposition annealing at 500 in N 2 /O 2 ; (9) TaN metal deposition by reactive sputtering; (10) Lithography, photoresist develop and photoresist trimming in O 2 plasma; (11) Reactive ion etching of gate electrode TaN; (12) Photoreist stripping in asher; (13) PECVD Si 3 N 4 spacer formation; (14) DHF dip to remove the oxides in S/D area; (15) 30 nm Ni deposition by E-beam evaporator; (16) Silicidation at 400 for 1 minute; (17) Removal of Ni residue by HNO Results and Discussion Gate Stack Figure 4.5 (A) shows the typical inversion C-V characteristics of the fabricated p- MOSFET measured at 1 MHz, the peak inversion capacitance corresponds to an EOT 105

123 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D (Equivalent Oxide Thickness) of 2.9 nm, taking the quantum mechanics into consideration. Gate leakage current density as a function of gate bias is shown in figure 4.5 (B), at V G = -1 V. A low gate leakage current density on an order of 10-6 A/cm 2 is achieved, which indicates the integrity of the gate stack, probably as a result of Si passivation and sub-500 process temperature Ni-Si 0.05 Ge C (ff/μm 2 ) 6 4 (A) High-k: HfO 2 2 Measured at 1MHz V g (V) J g (A/cm 2 ) (B) V g (V) Figure 4.5 (A) Inversion C-V curve of the Schottky S/D transistor, low gate leakage current density is also demonstrated in (B). 106

124 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D High resolution TEM of the gate stack from Ni-Si 0.05 Ge 0.95 Schottky S/D transistor is shown in figure 4.6. Smooth and high-quality interface between the high-k and SiGe/Si substrate is observed without detectable evidence of reaction between them. The channel region is high-quality single-crystal SiGe layer as indicated by clear lattice image. HfO 2 remained amorphous, a desired property, which is due to the low temperature process. TaN HfO 2 SiGe Figure 4.6 high resolution TEM of the gate stack from the Ni-Schottky S/D p- MOSFET which shows high interface quality. HfO 2 high-k dielectric remained amorphous. The clear lattice image of the channel indicates the high quality of the Si 0.05 Ge 0.95 top layer Performance of Long Channel MOSFET 107

125 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D Well behaved I s -V d curves from Ni-Si 0.05 Ge 0.95 Schottky S/D p-mosfet with channel W/L= 320/20 μm are shown in figure 4.7. V g -V th is from 0 to -0.9 V with a step of -0.3 V. At V d =V g -V th = -0.9 V, a drain current of 4~4.5 μa/μm is achieved. For Schottky S/D MOSFET, high drive current is difficult to obtain if barrier height between the source and the channel is high. The observed high driverability of the fabricated p-mosfet is due to the low Schottky barrier height of the S/D to channel. 5 4 Ni-Si 0.05 Ge 0.95 Lg = 20 μm V g -V th = 0 to -0.9 V Step= -0.3 V I s (μa/μm) V d (V) Figure 4.7 Typical I s -V d characteristics measured from the Ni- Schottky S/D transistor fabricated on the Si 0.05 Ge 0.95 /Si substrate with a gate length of 20 μm. Effective mobility is extracted using conventional split C-V method [23]. The effective carrier mobility μ eff can be formulated as μ eff =g d L/(WQ n ) (4.1) g d is the drain conductance and can be defined as: 108

126 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D g d = I d / V d (4.2) L and W are the length and width of the transistor, respectively; and Q n is the inversion carrier density. The vertical surface electric field, E eff is defined by the following expression: E eff =(Q b +ηq n )/kε o (4.3) Q b is the charge density in the space-charge region. η accounts for averaging of the electric field over electron distribution in the inversion layer, which is usually taken as 1/2 for the electron and 1/3 for the hole mobility [24, 25]. K is relative dielectric constant for the channel material and ε o is the permittivity in vacuum and equals to F/cm. In our experiment, effective mobility was extracted from the inversion capacitance measured at a frequency of 1 MHz and a drain current as a function of gate bias measured under drain voltage of -50 mv. K value for Si 0.05 Ge 0.95 substrate is taken as ε Ge (relative permittivity of Ge), which is 16 [26]. This is a good approximation, since the channel material consists of 95% Ge and only a small amount of Si. The relationship between extracted effective hole mobility μ hole and E eff is plotted in figure 4.8. Peak μ hole for fabricated Ni-Si 0.05 Ge 0.95 PMOSFET is cm 2 /V-s. Universal μ hole from SiO 2 /Si is also plotted for the purpose of comparison. As can be seen from the plot, for the fabricated Schottky p-mosfet, ~85% peak μ hole enhancement is achieved against the universal μ hole from Si MOSFET. The improved mobility also indicates the good interface quality due to the effectiveness of the Si passivation. The hole mobility enhancement is also maintained at high electric field region. 109

127 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D μ hole (cm 2 /Vs) % Hole Universal Ni-Si 0.05 Ge E eff (MV/cm) Figure 4.8 Effective hole mobility μ hole versus the effective electric field E eff. ~1.8X times peak hole mobility from Ni-Schottky S/D MOSFET on Si 0.05 Ge 0.95 /Si is demonstrated compared to universal hole mobility form Si p-mosfet Performance of Short Channel MOSFET The minimum gate length defined by the mask used in our experiment is 0.5 μm. The aforementioned photoresist trimming process was carried out to reduce the minimum gate length we can achieve. SEM (Scanning Electron Microscopy) was used to monitor the gate length after the trimming process. The following picture in figure 4.9 shows the top view SEM image taken from the sample after the the formation of the Si 3 N 4 spacer. The TaN electrode and Si 3 N 4 spacer are clearly discernable. The horizontal white dash lines were used as the boundaries of TaN to measure the gate length. As shown in the picture, the value of Y, which denotes the distance between the two horizontal lines (gate length) after photoresist trimming, is 97 nm. 110

128 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D Figure 4.9 SEM top image of the Ni-Schottky S/D transistor after the photoresist trimming and formation of the nitride spacer, it indicates that the gate length is 97 nm. Figure 4.10 (A) shows I s -V d of Ni-germanides Schottky S/D p-mosfet with high drivability, which is attributed to the negative hole barrier height of Nigermanide on Ge and its low resistivity [22]. The V g -V th is from 0 to -1.2 V with a step of -0.4 V. Figure 4.10 (B) shows transfer characteristic of Ni-germanide Schottky S/D p-mosfet. Relative high I off current is observed which is possibly due to much smaller bang gap. The table 4.1 compares this work with other previous works regarding the characteristics of Schottky S/D MOSFETs and conventional Si MOSFETs. By normalizing the difference of gate length and EOT, fabricated Ni-germanide MOSFET on Si 0.05 Ge 0.95 /Si shows higher drive current compared with Si conventional and Schottky S/D transistors. However, due to its small band gap, controlling I off is critically important. 111

129 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D I s (μa/μm) Ni-Si 0.05 Ge 0.95 V g -V th = 0 to - 1.2V Step = - 0.4V (A) V d (V) 10 (B) I s (μa/μm) V d = - 50 mv V g (V) Figure 4.10 (A) I s -V d curves from short channel Ni-germanide Schottky S/D PMOSFET; (B) I s -V g curves from short channel Ni-germanide Schottky S/D PMOSFET; 112

130 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D Table 4.1 Comparison between this work and previous works regarding the characteristics of Schottky S/D and conventional MOSFETs; L g is gate length, I d is drain current and I on / off is on/off ratio; Devices EOT (nm) L g (nm) I d (μa/μm) I on /I off This work Si Bulk doped S/D Ref [27] Si Bulk Schottky S/D Ref [28] Si Bulk Schottky S/D Ref [28] Conclusion In this section, high performance Si 0.05 Ge 0.95 /Si p-mosfet with HfO 2 /TaN gate stack using Ni-germinde Schottky S/D technology is demonstrated. Because of low Schottky barrier height between the S/D and the channel, high drive current of the p- MOSFET is achieved. In addition, the extracted peak hole mobility for fabricated Schottky S/D PMOSFET is found to be ~1.8X times higher than the universal hole mobility from Si MOSFET. Schottky MOSFET with gate length of 97 nm is also demonstrated using photoresist trimming process; the device shows improved driverability compared with Si MOSFET with either conventional or doped S/D. 4.3 Schottky S/D MOSFET on thin SGOI substrate The difficulties in achieving highly doped S/D due to the poor activation and solid solubility limits of dopants in Ge-based MOSFET, together with its small band gap cause high junction leakage. A SOI structure can effectively suppress the leakage. Hence, combination of ultra-thin body structure and Schottky S/D engineering has been considered as one of the promising non-classical CMOS technology. Recently, 113

131 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D Pt-germanide Schottky S/D transistor on Ge-on-insulator using buried SiO 2 as gate dielectric and Si-substrate as bottom gate electrode has been reported with excellent performances, operating in accumulation mode [29]. In this section, we will discuss the Schottky S/D transistor using Ni-germanosilicide on the thin SGOI wafer and HfO 2 /TaN gate stack fabricated by conventional self-aligned top gate structure SGOI substrate and Transistor Structure Figure 4.11 shows the high resolution TEM of the SiGe layer on insulator prepared by oxidation of amorphous SiGe film on SOI wafer. The details of this novel condensation approach have been discussed in chapter 3. The thickness of the single crystal SiGe layer is found to be ~30 nm with Ge concentration of ~65% detected by EDX. Ge concentration is quite uniform within this ~30 nm SiGe layer. The transistor fabrication process is the same as the process mentioned in the previous section. However, no photoresist trimming was involved in this SGOI Schottky S/D transistor fabrication process. Some process conditions are slightly different from what was used to fabricate the Ni-Si 0.05 Ge 0.95 /Si Schottky transistor: 1) channel implantation: Phosphorus with energy of 100 KeV and dose of /cm 2 ; 2) dopant activation: spike anneal at 1000 o C for 1s; since the concentration of Ge is decreased to 65%, slightly high activation temperature is used; 3) the thickness of Ni deposited in the S/D is 10 nm~15 nm rather than 30 nm used in bulk SiGe/Si Schottky MOSFET fabrication: the SiGe film thickness of SGOI wafer is quite thin (30nm). During the silicidation process, the supply of Si and Ge element in the S/D area may not be enough. 114

132 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D Figure 4.12 shows schematic view of cross-sectional structure of the Schottky S/D MOSFETs fabricated with Ni-germanosilicide S/D and HfO 2 /TaN gate stack on Si 0.35 Ge 0.65 channel. Figure 4.11 High resolution TEM image of the SGOI wafer prepared by oxidation of amorphous SiGe on SOI wafer. The thickness of the body is ~30 nm and the Ge atomic concentration detected by EDX is 65% Gate Stack and S/D TEM High resolution TEM of the gate stack is shown in figure The amorphous interfacial layer is quite uniform and that layer is believed to be a compound of Si. As can be seen in high resolution TEM of gate stack, a conformal HfO 2 film on single 115

133 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D crystal Si 0.35 Ge 0.65 channel remains amorphous and has sharp interface with the SiGe. Ultra-thin interfacial layer is observed between HfO 2 film and Si 0.35 Ge 0.65 channel, which is believed to be formed during oxidation process. Figure 4.12 Schematic drawing of device cross-sectional structure of SGOI MOSFET with Schottky S/D and HfO 2 /TaN gate stack.. In addition, the clear smooth interface between Si 0.35 Ge 0.65 channel and Nigermanosilicide is observed at S/D region. The epitaxial growth of Nigermanosilicide grain on Si 0.35 Ge 0.65 (001) is also observed. The sufficient overlap of Ni-germanosilicide S/D with gate electrode may be explained by the fact that Ni is the main diffusing species during solid-state reaction of Ni with Si and Ge [30]. The atomic composition of Ni: Si: Ge detected by EDX is 52: 22: 26. The Si-Ge ratio in the Ni-germanosilicide film is different from that in the SGOI film probably because only stable phases can exist in the Ni-germanosilicide film after reaction between Ni and SGOI. Segregation and diffusion out of rich Si and Ge were also reported [30]. In addition, according to previous report, three stable ternary phases, Ni 3 Si-Ni 3 Ge, Ni 2 Si-Ni 2 Ge, and NiSi-NiGe can be formed during reaction of Ni with SiGe. At a 400 rapid thermal anneal process, our EDX data indicates that NiSi-NiGe is the preferred phase. 116

134 Chapter 4: High Mobility Channel MOSFET Integrated with High-k/Metal Gate and Schottky S/D Figure 4.13 TaN-HfO 2 -Si 0.35 Ge 0.65 gate stack and S/D area of the fabricated thin SGOI Schottky S/D transistor, the composition of the S/D area is determined by EDX analysis Transistor Characteristics Figure 4.14 shows the inversion C-V (capacitance-voltage) curve of the fabricated SGOI p-mosfet measure at 1MHz. The peak inversion capacitance corresponds to an equivalent oxide thickness of 2.2 nm, considering the quantum mechanical effect. The C-V in figure 4.14 was measured under V g swept from positive to negative voltage. The inset shows gate leakage current density as a function of the gate bias when the channel is in inversion. By using low temperature process for Nigermanosilicide S/D formation, we successfully demonstrate Schottky S/D p- MOSFET on SGOI with excellent C-V characteristic together with low gate leakage. 117