Xilinx XC4036EX FPGA

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1 Construction Analysis Xilinx XC4036EX FPGA Report Number: SCA Global Semiconductor Industry the Serving Since N. 75th Street Scottsdale, AZ Phone: Fax: Internet:

2 INDEX TO TEXT TITLE PAGE INTRODUCTION 1 MAJOR FINDINGS 1 TECHNOLOGY DESCRIPTION Die Process 2-3 ANALYSIS RESULTS I Die Process and Design 4-6 ANALYSIS PROCEDURE 7 TABLES Overall Quality Evaluation 8 Die Material Analysis 9 Horizontal Dimensions 10 Vertical Dimensions 11 - i -

3 INTRODUCTION This report describes a construction analysis of the Xilinx XC4036EX Field Programmable Gate Array (FPGA). One decapped device was received for the analysis. The device was date coded MAJOR FINDINGS Questionable Items: 1 None. We found no areas of reliability concern. Special Features: Sub-micron gate lengths (0.45 micron N-channel and 0.5 micron P-channel). 5T SRAM (select-ram) cells for programming. Reflowed (?) aluminum filled vias. 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application

4 TECHNOLOGY DESCRIPTION Die Process and Design: The device was fabricated using a selective oxidation, N-well CMOS process in a P- substrate. No epi was used. Passivation consisted of a layer of nitride over a layer of silicon-dioxide. Three levels of metal interconnect were used. Metal 3 and metal 2 consisted of aluminum with a titanium-nitride (TiN) cap and titanium (Ti) barrier. Metal 1 consisted of aluminum with a titanium-nitride (TiN) cap and barrier. A thin titanium (Ti) adhesion layer was used under metal 1. Aluminum filled vias were used under both metal 3 and metal 2 and tungsten (W) plugs were used for contacts under metal 1. A titanium nitride (TiN) layer was present under the plugs. Interlevel dielectrics consisted of three layers of glass. The first layer was quite thin. The second layer was an SOG subjected to an etchback for planarization. A thick third layer covered these. Pre-metal glass consisted of a layer of reflow glass over various densified oxides. Glass was reflowed prior to contact cuts only. A single layer of polycide (poly with tungsten silicide) was used to form all the gates on the die. Definition was by a dry etch of normal quality. Implanted N+ and P+ diffusions formed the sources/drains of the CMOS transistors. The process used oxide sidewall spacers that were left in place. Local oxide (LOCOS) isolation. No step was present in the oxide at the edge of the well, and no other signs of the use of P-wells was found

5 TECHNOLOGY DESCRIPTION (continued) The memory cell array utilized a 5T SRAM cell design. Metal 3 was used to form the word lines. Metal 2 was used to form the bit lines and distribute GND and Vcc (via metal 1). Metal 1 provided cell interconnect. Poly was used to form all gates. Variations in the metal interconnect layout were observed

6 ANALYSIS RESULTS I Die Process : Figures 1-32 Questionable Items: 1 None. As mentioned, we found no quality concerns whatsoever. Special Features: Sub-micron gate lengths (0.45 micron N-channel and 0.5 micron P-channel). 5T SRAM (select-ram) cells for programming. Reflowed (?) aluminum filled vias. General items: Fabrication process: Devices were fabricated using a selective oxidation, N-well CMOS process in a P-substrate. No epi was used. Process implementation: Die layout was clean and efficient. Alignment was good at all levels. No damage or contamination was found. Die coat: No die coat was present. Overlay passivation: A layer of nitride over a layer of silicon-dioxide. Overlay integrity test indicated defect-free passivation. Edge seal was good. Metal interconnect employed three levels of metal. Metal 3 and metal 2 consisted of aluminum with a titanium-nitride (TiN) cap and titanium (Ti) barrier. Metal 1 consisted of aluminum with a titanium-nitride (TiN) cap and barrier on a thin 1 These items present possible quality or reliability concerns. They should be discussed with the manufacturer to determine their possible impact on the intended application

7 ANALYSIS RESULTS I (continued) titanium (Ti) adhesion layer. Aluminum filled vias were used under both metal 3 and metal 2, and tungsten (W) plugs were used for contacts under metal 1. Metal patterning: All three metal levels were patterned by a dry etch of normal quality. Metal defects: No voiding, notching, or neckdown was noted in the metal 3 or metal 2. No silicon nodules were noted following removal of either metal layer. No problems were noted in any of the layers. Metal step coverage: Vias under metal 3 and metal 2 were completely surrounded by metal. Metal 1 used plugs at contacts. Metal 3 and metal 2 had virtually no thinning due to the use of the aluminum filled vias. No thinning was present in metal 1 because of the use of tungsten (W) plugs at contacts. Interlevel dielectrics consisted of three layers of glass. The first layer was a thin even thickness, not planarized in any way. The second layer was an SOG subjected to an etchback for planarization. The third covering layer was of even and substantial thickness, and in fact may have been a triple layer rather than a single homogeneous layer. No problems were noted. Pre-metal glass: A layer of reflow glass (BPSG) over various densified oxides was used under metal 1. Reflow was performed prior to contact cuts only. No problems were found. Vias and contacts: Via cuts were defined by a two-step process. Vias appeared to have been patterned using a controlled overetch to just penetrate the titanium nitride cap to the aluminum underneath. Contacts used an apparent single etch step, lined with the titanium-nitride barrier and then filled with tungsten. No problems were found

8 ANALYSIS RESULTS I (continued) A single layer of polycide (poly and tungsten silicide) was used to form all gates on the die. Definition was by a dry-etch of normal quality. Standard implanted N+ and P+ diffusions formed the sources/drains of the CMOS transistors. The process used oxide sidewall spacers that were left in place. No problems were found. Local oxide (LOCOS) isolation was used. No step was present in the oxide at the well boundaries, nor did we find any other evidence of the use of P-wells. The memory cell array utilized a 5T SRAM cell design. Metal 3 was used to form the word lines. Metal 2 was used to form the bit lines and distribute GND and Vcc (via metal 1). Metal 1 provided cell interconnect. Poly was used to form all gates. Cell pitch was 8.7 x 9.5 microns. Process in the array appeared identical to the rest of the die. Redundancy fuses were not present on the die

9 PROCEDURE The devices were subjected to the following analysis procedures: Internal optical inspection SEM of passivation Passivation integrity test Passivation removal SEM inspection of metal 3 Metal 3 removal and inspect barrier Delayer to metal 2 and inspect SEM inspection of metal 2 Metal 2 removal and inspect barrier Delayer to metal 1 and inspect Metal 1 removal and inspect barrier Delayer to silicon and inspect poly and die surface Die sectioning (90 for SEM) * Die material analysis Measure horizontal dimensions Measure vertical dimensions * Delineation of cross-sections is by silicon etch unless otherwise indicated

10 OVERALL QUALITY EVALUATION : Overall Rating: Good DETAIL OF EVALUATION Die surface integrity: Toolmarks (absence) Particles (absence) Contamination (absence) Process defects General workmanship Passivation integrity Metal definition Metal integrity Metal registration Contact coverage Contact registration G G G G G G N G N G N G = Good, P = Poor, N = Normal, NP = Normal/Poor - 8 -

11 DIE MATERIAL ANALYSIS Final passivation: A layer of silicon-nitride over a layer of glass. Metallization 3: * Aluminum (Al) with a titanium-nitride (TiN) cap and titanium (Ti) barrier. Metallization 2: * Aluminum (Al) with a titanium-nitride (TiN) cap and titanium (Ti) barrier. Metallization 1: * Aluminum (Al) with a titanium-nitride (TiN) cap and barrier on a thin titanium (Ti) adhesion layer. Silicide (poly): Tungsten (W). * No evidence of silicon or copper doping was found but amounts less than 0.5 wt. percent may have been present

12 HORIZONTAL DIMENSIONS Die size: 15.8 x 17.5 mm (620 x 690 mils) Die area: 277 mm 2 (427,800 mils 2 ) Min pad size: Min pad window: Min pad space: Min metal 3 width: Min metal 3 space: Min metal 3 pitch: Min via size (M3-to-M2): Min metal 2 width: Min metal 2 space: Min metal 2 pitch: Min via size (M2-to-M1): Min metal 1 width: Min metal 1 space: Min metal 1 pitch: Min contact: Min poly width: Min poly space: Min gate length * - (N-channel): 0.1 x 0.1 mm (3.8 x 3.8 mils) 0.08 x 0.08 mm (3.25 x 3.25 mils) 4 mils 0.8 micron 0.7 micron 1.5 micron 0.55 micron (diameter) 0.75 micron 0.6 micron 1.4 micron 0.5 micron (diameter) 0.65 micron 0.55 micron 1.2 micron 0.55 micron (diameter) 0.45 micron 0.55 micron 0.45 micron - (P-channel): 0.5 micron Cell pitch: 8.7 x 9.5 microns Cell size: 83 microns 2 * Physical gate length

13 VERTICAL DIMENSIONS Die thickness: 0.4 mm (15 mils) Layers: Passivation 2: 0.6 micron Passivation 1: 0.4 micron Metal 3 - cap: 0.06 micron (approximate) - aluminum: 1.0 micron - barrier: 0.08 micron (approximate) Interlevel dielectric 2 - glass 3: 0.45 micron - glass 2: 0.6 micron - glass 1: 0.08 micron (approximate) Metal 2 - cap: 0.06 micron (approximate) - aluminum: 0.45 micron - barrier: 0.08 micron (approximate) Interlevel dielectric 1- glass 3: 0.5 micron - glass 2: 0.65 micron - glass 1: 0.09 micron (approximate) Metal 1 - cap: 0.05 micron (approximate) - aluminum: 0.5 micron - barrier: 0.1 micron Pre-metal dielectric: 0.3 micron (average) Oxide on poly: 0.11 micron Poly - silicide: 0.1 micron - poly: 0.15 micron Local oxide: 0.4 micron N+ S/D: 0.22 micron P+ S/D: 0.15 micron N-well: 3.75 microns

14 INDEX TO FIGURES DIE LAYOUT AND IDENTIFICATION Figures 1-3 PHYSICAL DIE STRUCTURES Figures 4-28 COLOR DRAWING OF DIE STRUCTURE Figure 22 SRAM CELL ARRAY Figures INPUT PROTECTION CIRCUIT Figure 28 GENERAL CIRCUIT LAYOUT Figure 28 - ii -

15 Figure 1. Portion of the whole die photograph of the Xilinx XC4036EX. Mag. 10x.

16 Figure 1a. Portion of the whole die photograph of the Xilinx XC4036EX. Mag. 10x.

17 Figure 1b. Portion of the whole die photograph of the Xilinx XC4036EX. Mag. 10x.

18 Figure 1c. Remaining portion of the whole die photograph of the Xilinx XC4036EX. Mag. 10x.

19 Mag. 200x Mag. 500x Mag. 500x Figure 2. Markings from the die surface.

20 Figure 3. Optical views of the die corners. Mag. 80x.

21 EDGE OF DIE Mag. 810x Mag. 1600x CUT-OUT METAL 3 Mag. 3200x METAL 2 METAL 1 Figure 4. SEM section views of the edge seal.

22 Au BALL BOND Mag. 810x Au BALL BOND METAL 2 METAL 3 METAL 1 Mag. 3200x Figure 5. SEM section views of the bond pad structure.

23 METAL 3 METAL 2 METAL 1 W PLUG LOCOS N+ S/D POLY METAL 3 METAL 2 W PLUG METAL 1 LOCOS POLY N+ S/D Figure 6. SEM section views of general structure (silicon etch). Mag. 10,000x.

24 Mag. 3200x Mag. 10,000x Figure 7. Perspective SEM views of the overlay passivation coverage. 60.

25 PASSIVATION 2 PASSIVATION 1 TiN CAP ALUMINUM 3 Ti BARRIER Mag. 26,000x TiN CAP ALUMINUM 3 VOID Ti BARRIER Mag. 40,000x Figure 8. SEM section views of metal 3 line profiles.

26 METAL 3 Mag. 3200x METAL 3 Mag. 6500x Figure 9. Topological SEM views of metal 3 patterning. 0.

27 METAL 3 Mag. 5000x TiN CAP ALUMINUM 3 Mag. 20,000x Ti BARRIER PASSIVATION METAL 3 Mag. 26,000x METAL 2 Figure 10. SEM views of metal 3 coverage and via.

28 METAL 3 INTERLEVEL DIELECTRIC 2 ALUMINUM 2 INTERLEVEL DIELECTRIC 1 Mag. 26,000x TiN CAP INTERLEVEL DIELECTRIC 2 ALUMINUM 2 Ti BARRIER INTERLEVEL DIELECTRIC 1 Mag. 40,000x Figure 11. SEM section views of metal 2 line profiles.

29 METAL 2 VIA 2 VIA 1 Mag. 4000x METAL 1 VIA 2 VIA 1 METAL 2 Mag. 8100x Figure 12. Topological SEM views of metal 2 patterning. 0.

30 METAL 2 Mag. 6500x, 60 METAL 2 Mag. 26,000x, 60 VIA 1 METAL 2 INTERLEVEL DIELECTRIC 1 Mag. 26,000x METAL 1 Figure 13. SEM views of metal 2 coverage and via.

31 SOG METAL 2 ALUMINUM 1 INTERLEVEL DIELECTRIC 1 SOG PRE-METAL DIELECTRIC LOCOS Mag. 26,000x TiN CAP SOG ALUMINUM 1 TiN BARRIER Ti ADHESION LAYER Mag. 52,000x Figure 14. SEM section views of metal 1 line profiles.

32 CONTACT VIA 1 POLY METAL 1 Mag. 5000x VIA 1 CONTACT POLY METAL 1 Mag. 7400x Figure 15. Topological SEM views of metal 1 patterning. 0.

33 VIA 1 METAL 1 Mag. 6500x CONTACT TiN CAP ALUMINUM 1 Mag. 26,000x TiN BARRIER W PLUG TiN BARRIER Mag. 40,000x W PLUG Figure 16. Perspective SEM views of metal 1 coverage and barrier. 60.

34 METAL 1 metal 1-to-P+ W PLUG P+ S/D POLY PRE-METAL DIELECTRIC P+ S/D METAL 2 INTERLEVEL DIELECTRIC 1 METAL 1 metal 1-to-N+ W PLUG POLY N+ S/D N+ S/D PRE-METAL DIELECTRIC LOCOS METAL 1 metal 1-to-poly W PLUG POLY LOCOS Figure 17. SEM section views of typical metal 1 contacts. Mag. 26,000x.

35 POLY Mag. 3200x POLY DIFFUSION Mag. 6500x Figure 18. Topological SEM views of poly patterning. 0.

36 Mag. 8800x POLY DIFFUSION CONTACT Mag. 52,000x POLY GATE Mag. 52,000x SILICIDE POLY LOCAL OXIDE Figure 19. Perspective SEM views of poly coverage. 60.

37 PRE-METAL DIELECTRIC SILICIDE POLY P-channel, silicon etch P+ S/D P+ S/D METAL 1 PRE-METAL DIELECTRIC SILICIDE POLY W PLUG N-channel, silicon etch N+ S/D N+ S/D GATE OXIDE SIDEWALL SPACER Ti LINER SILICIDE glass etch POLY GATE OXIDE Figure 20. SEM section views of typical transistors. Mag. 52,000x.

38 METAL 1 PRE-METAL DIELECTRIC POLY SILICIDE LOCAL OXIDE BIRDSBEAK Figure 21. SEM section view of a local oxide birdsbeak. Mag. 40,000x. N-WELL P-SUBSTRATE Figure 21a. Optical view of the well structure. Mag. 800x.

39 TiN CAP Ti BARRIER TiN CAP Ti BARRIER TiN CAP TiN BARRIER W PLUG SILICIDE Xilinx XC4036EX ALUMINUM 3 PASSIVATION 2 PASSIVATION 1 INTERLEVEL DIELECTRIC 2 ALUMINUM 2 INTERLEVEL DIELECTRIC 1 Ti BARRIER,,,,,,,,,, ALUMINUM 1 PRE-METAL DIELECTRIC,,,,,,,,,, POLY N+ S/D P+ S/D N WELL P-SUBSTRATE Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly, Red = Diffusion, and Gray = Substrate Figure 22. Color cross section drawing illustrating device structure.

40 WORD metal 3 V CC BIT GND metal 2 Figure 23. SEM views of the SRAM cell. Mag. 3200x, 60.

41 metal 1 poly Figure 24. SEM views of the SRAM cell. Mag. 3200x, 60.

42 WORD metal 3 V CC BIT GND metal 2 Figure 25. Topological SEM views of the SRAM cell. Mag. 3200x, 0.

43 V CC metal 1 DELAYERING ARTIFACTS BIT poly WORD 2 4 BIT 1 BIT 3 5 Figure 26. Topological views and schematic of the SRAM cell. Mag. 3200x, 0.

44 METAL 3 METAL 2 Mag. 13,000x METAL 1 SELECT GATE LOCOS POLY N+ S/D SILICIDE Mag. 32,000x POLY N+ S/D N+ S/D SOG PRE-METAL DIELECTRIC POLY SELECT GATE Mag. 52,000x N+ S/D N+ S/D Figure 27. SEM section views of the SRAM cell.

45 Mag. 300x Mag. 800x Figure 28. Optical views of the I/O structure and general circuitry.