Demonstration of enhanced system-level reliability of ultra-thin BGA packages with circumferential polymer collars and doped solder alloys

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1 2016 IEEE 66th Electronic Components and Technology Conference Demonstration of enhanced system-level reliability of ultra-thin BGA packages with circumferential polymer collars and doped solder alloys Bhupender Singh, Ting-Chia Huang, Venky Sundaram, Raj Pulugurtha, Vanessa Smet, Rao Tummala 3D Systems Packaging Research Center Georgia Institute of Technology Atlanta, GA, USA Abstract - The trend towards ultra-miniaturization, high interconnection densities with minimal power consumption at low cost is driving the need for large, thin, high-stiffness substrate technologies. Glass substrates have emerged as a promising alternative to organic and silicon interposer packages due to their tunable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability. This paper presents a comprehensive study of the effect of glass CTE on board-level reliability of 100μm-thick glass ball grid array (BGA) packages, 18.5 mm x 18.5 mm in body size, with considerations of yield, warpage and thermal cycling performance. Polymer collars and novel doped solder alloys were also introduced to further enhance board-level reliability, and subsequently demonstrate the extendibility of direct SMT assembly of glass BGA packages to even larger body sizes. The test vehicle used in this study was an emulator of a single-chip application processor package. Daisy chain test dies, 10mm x 10mm in size and μm in thickness, were assembled onto the fabricated glass substrates with Si-matching CTE (3.8ppm/K) and board-matching CTE (9.8ppm/K) by dipflux thermo-compression bonding with capillary underfill, at panel level. A stencil-based paste printing process was developed and optimized for panel-level balling of the glass packages with 250μm BGA at 400μm pitch. Variations in solder alloys were considered, including standard SAC105 and SAC305 used as reference, and the novel Mn-doped SACm by Indium Corporation. After singulation by laser dicing, the glass packages were finally mounted on mother boards by standard SMT reflow, after optimization of the heating profile to minimize solder voiding. Board-level yield was evaluated to 91%, and explained based on Shadow-Moiré warpage measurements, showing a strong dependence to the chip-level underfill fillet size. Initial thermal cycling reliability was conducted on the glass BGA packages with and without polymer collars. All samples passed 600 cycles with stable daisy chain resistances, regardless of the glass CTE and solder alloy composition. Keywords Board-level reliability; glass BGA packages; doped solders; polymer collars; stencil printing; warpage; thermal cycling I. INTRODUCTION Emerging consumer applications and their increasing need for high bandwidth and transmission speed at low power have been driving high-density system integration with 2.5D Satomi Kawamoto Namics Corporation Niigata, Japan skawamoto7@mail.gatech.edu and 3D packages with large body sizes. This level of integration requires ultra-thin substrate technologies which are capable of lithographic design rules below 5μm and induce low stresses on ultra-low K dielectrics, while retaining high dimensional stability. Low-CTE organic and silicon interposers have been proposed to address some of these challenges, to achieve chip-level reliability at larger die sizes and reduced I/O pitches, below 40μm. However, such substrate technologies face critical reliability challenges at board-level due to the large CTE mismatch with the organic printed circuit boards (PCBs). Concerns over board-level thermomechanical reliability are further aggravated by the recent trends towards SMT pitch scaling, below 400μm, reduced substrate thicknesses and larger body sizes, exceeding 20mm x 20mm, with subsequent increases in solder strains and warpage. Traditional underfills, commonly used to improve the fatigue life of solders at chip-level, would compromise reworkability at board level, and are therefore not a desirable solution. Reinforced polymer collars, acting as partial underfills, have recently been demonstrated as a promising stress-relief solution to increase thermal cycling reliability by 30-50% [1]. Varying the solder composition can also be used to improve fatigue life, as it affects the ability of the solder to plastically deform. Hard solders like SAC305, with higher Ag content, are more favorable to thermal cycling than soft solders like SAC105, with low Ag content, on account of their higher yield strength and modulus [2]. However, soft solders can better absorb shock energy, yielding superior drop test performance. With standard SAC alloys, improvements in fatigue life thus come at the cost of the drop performance, which is equally critical in consumer products. Advances in solder materials are required to achieve balanced thermomechanical and drop reliability. To that end, Indium Corporation has recently developed the Mn-doped SACm TM solder alloy which inhibits rapid intermetallics (IMCs) growth and enables finer microstructure, achieving higher drop test performance than SAC 105 with similar fatigue life of SAC305 [3, 4]. The SACm alloy is currently commercially available in paste form only, thus limiting its applicability to pitches above 500μm in manufacturing. Beyond solders, extensive research has also been carried out on compliant interconnections, including bump-onpolymer structures [5], double-ball wafer-level packaging [6], embedded solder balls [7], printed silicone bumps [8], multi-path shaped interconnects [9], and copper micro-wire /16 $ IEEE DOI /ECTC

2 array [10]. However, wide-scale adoption of these technologies in high-volume manufacturing is hindered by limited manufacturability of the fabrication processes, incompatibility with standard SMT assembly processes, and not fully established drop test reliability. The current approach to achieving board-level reliability with large, low-cte interposers consists in the addition of a package layer between interposer and PCB. This three-level hierarchy adding to the overall thickness and cost, and degrading the electrical performance. A two-level solution with reliable, direct interposer package-to-board interconnection, maintaining SMT compatibility and reworkability, is thus highly sought after by the semiconductor industry to meet emerging miniaturization and performance requirements. Glass substrates have recently been pursued as a new integration platform addressing the aforementioned grand challenge. They offer high interconnection densities enabled by sub-5μm lithographic design rules, large area panel-based processability at low cost, high dimensional stability, tunable-cte for warpage and reliability mitigation, and lower insertion losses compared to Si interposers. Previous research by Georgia Tech Packaging Research Center (GT- PRC) and its industry partners demonstrated drop test reliability of 18.5mm x 18.5mm glass SAC105 BGA packages, 100μm-thick in thickness, at 400μm SMT pitch. While the CTE of glass had little effect on the drop performance, polymer collars showed a 2X improvement due to compressive stresses they induce on locations of critical stress concentration [11]. In addition, the glass packages passed thermal cycling test by JEDEC standards, with a fatigue life averaging 1140 cycles with low-cte glass, and exceeding 4300 cycles for high-cte glass. Polymer collars again yielded in a 30% improvement in the fatigue life of the BGA joints. This paper aims at evaluating how far glass substrates, with their tunable CTE, can extend the applicability of conventional solders for reliable, direct glass package-toboard interconnections, and goes beyond with the following innovations: 1) use of Mn-doped SAC solder (Indium Corp.) with expected longer fatigue life than standard SAC alloys, enabled by its unique interfacial reaction and resulting microstructure; and 2) circumferential polymer collars acting as a partial, reworkable underfill. These innovations provide a unique combination of strain relief and warpage mitigation, improving board-level reliability without degrading chiplevel reliability. The design, fabrication, assembly, warpage and board-level thermomechanical reliability characterizations of 18.5mm single-chip glass BGA packages, emulating an application processor package are discussed in detail. II. TEST VEHICLE DESIGN AND FABRICATION A. Daisy Chain Test Die The daisy chain test die of Fig. 1, 10mm x 10mm in size, featured 5448 I/Os, distributed in four staggered peripheral rows at 80/40 μm pitch, and a central area array at 150μm pitch. Silicon test wafers, 300mm in size, were fabricated, plated with Cu dogbone wiring structures, and bumped with standard Cu pillars by Advanced Semiconductor Engineering Inc. (ASE). The copper pillar interconnections, 28μm in diameter, are composed of a 17μm copper height, a 3μm Ni barrier layer, and a 17μm SnAg solder cap. Figure 1. First-level interconnect design (left) of the die with peripheral and internal dog-bone structures with bumps magnified (right) (Image courtesy of ASE). B. Glass Substrate Fabrication Glass substrates were designed to accommodate the die footprint on the top side, and a 45 x 45 area array of daisychained BGA interconnections on the backside, as shown in Fig. 2. Figure 2. Glass substrate test vehicle design on (left) the die side, and (right) the BGA side. The chip- and board-level daisy chains are not connected in the absence of through-package-vias (TPVs) and can be tested independently. The design includes a total of four metal layers, with a dummy mesh pattern implemented in the inner layers to provide sufficient Cu coverage for accurate warpage representation. The glass substrates were fabricated using standard semi-additive processes. Low- and high-cte glass substrates, 6 inch x 6 inch in size, and 100μm in thickness, were first laminated with 17.5μm-thick dielectric layers of ZEONIF TM ZS-100 (ZIF), which were cured in a furnace at 180 C. Double-side lithography processes using dry-film photoresist were applied to define the copper dog bone structures, 10-12μm thick formed by electrodeposition. After photoresist stripping and etching of the electroless copper seed layer, the double-side process was repeated again 1378

3 with lamination of dielectric build-up layers of ZIF ZS-100 (17.5 m). The daisy chain patterns on die and BGA sides were simultaneously formed by double-side Cu electrolytic plating. An additional layer of ZS-100 was applied as passivation to define landing and probing pads. Electroless palladium autocatalytic gold (EPAG) surface finish was finally plated on the exposed pads by ATOTECH GmBH with a production-controlled process. A cross-sectional expanded view of the four-metal layer fabricated substrates is shown in Fig. 3, while Table I provides a summary of the test vehicle design rules, materials and stack-up. Figure 4. Daisy-chain interconnection design of the PCB with probing pads. Figure 3. Expanded view of 18.5mm x18.5mm 4-metal layer glass substrate. C. PCB Board Design The BGA area array patterned on the back side of the glass substrates consists of 2025 solder balls at 400μm pitch, divided in a network of 52 daisy chains. A single-layer PCB board was designed with matching daisy chain structures, including four corner circuits comprising six BGAs each, and 48 inner chains, as indicated by the circles in Fig. 4. The copper pads are non-solder mask defined (NSMD), and were plated with electroless nickel electroless palladium immersion gold (ENEPIG) surface finish. TABLE I: SUMMARY OF TEST VEHICLE MATERIALS AND DESIGN RULES III. ASSEMBLY AND YIELD EVALUATION A. Chip-level Assembly To fully understand the effect of warpage on board-level assembly yield and reliability, variations in die thickness were introduced. Test dies, 100μm and 200μm in thickness, were assembled on glass substrates with a dip-flux die-to-panel thermocompression bonding process, using a Finetech FINEPLACER Matrix semi-automatic flip-chip bonder with a placement accuracy of ±3μm. Bonding was achieved with a constant stage temperature of 100 C, a tool head peak temperature of 360 C on the die side at a heating rate of 6K/s, and an applied pressure of 0.9MPa throughout the process. A fully populated 6 inch x 6 inch glass panel is pictured in Fig. 5 to illustrate this process. The assemblies were then underfilled with the Namics Corporation material by manual dispensing using a single dot pattern, followed by curing at 165 C for one hour. Chip-level assembly was completed on two low-cte and half of a high- CTE glass panel, for a total of 90 parts, with excellent yield. Parameters Substrate core Build-up layers Solder resist Metal layers Surface finish BGA Solder Description Low- & high-cte glass ZIF 17.5μm/ZIF 17.5μm 15μm SMD 4ML with 80% Cu coverage on inner dummy EPAG (Atotech Germany) 400μm pitch (Paste printed) SACm TM, SAC305, SAC105 (Indium) Die thickness 100μm, 200μm Underfill (FLI) 50μm Figure 5. Chip-level assembly low-cte on glass substrate by thermocompression bonding at panel-level. 1379

4 B. BGA Balling Process Development and Optimization For evaluation of the new Mn-doped SACm TM solder, only available in paste form, and its comparison to the performance of SAC305 and SAC105 alloys, a BGA balling process by solder paste printing was first developed and optimized. Paste printing is seldom applied at such fine SMT pitch of 400μm, considered too challenging in achieving adequate paste release rates, good solder volume uniformity and high balling yields. Stencil design, paste printing procedure, optimization of the reflow profile as well as systematic characterization of the balling yield were critically carried out to establish a baseline process that could be trusted for this reliability study. 1) Stencil design BGA balling was performed with a nickel electroformed (Ni-E) stencil with a proprietary nano-coat TM from MET Technology Inc. The stencil design (Fig. 6) was completed in accordance with IPC-7525A standard [12]. Figure 6. Schematic of the stencil for BGA balling by paste printing. Figure 7. Optical inspection of as-printed samples indicating that good paste release was achieved with a uniform deposit, good paste-to-pad alignment and no observed bridging. 3) Reflow optimization Use of a linear ramp rate or ramp-to-spike type reflow profiles (Fig. 8) is known to reduce reflow-based defects such as solder beading, and aggravated hot slump leading to solder bridging [13]. To achieve acceptable wetting and solderability, a peak temperature 15 to 30 C higher than the solder melting point and a time of seconds above liquidus temperature are considered ideal. A five-zone Electrovert Omniflow reflow oven was programmed to meet the aforementioned conditions recommended by Indium, as confirmed by wireless thermocouple measurements. The reflow conditions were optimized to minimize solder voiding using Cu-clad FR-4 boards, patterned with solder mask passivation to match the glass test vehicle BGA design. The temperature profile and conveyor speed were varied, and the formed solder balls were subsequently observed by X-ray microscopy. Results from this evaluation are reported in Table III. A gradual reduction in the occurrence and size of voids can be observed from Board 1 through 4. Considering the metal loading in the solder pastes of 88.5%, calculations were adjusted with considerations of the solder paste flux shrinkage during reflow. The designed stencil thickness was of 5 mils (127.4 μm) with apertures of mils (300 μm), yielding an aspect ratio of 2.42 and an area ratio of ) Paste printing and reflow Paste printing was accomplished with a semi-automatic MPM manufactured SPM Screen Printer, and a standard 12- inch metal squeegee after optimizing parameters for the stencil height, the squeegee pressure and the print stroke length. Table II lists the recommended print parameters by Indium for the printer operation [16]. Optical inspection (Fig. 7.) confirmed excellent paste transfer efficiency with a uniform deposit and good paste to pad alignment and no observed bridging. Figure 8. Recommended reflow profile for SAC305 solder paste [13]. TABLE II: SUGGESTED PARAMETERS FOR STENCIL BASED PASTE PRINTING Parameter Print speed Squeegee pressure Underside wipe Value mm/sec kg/mm of blade length At least every 5 prints 1380

5 TABLE III. REFLOW OPTIMIZATION FOR MINIMIZATION OF SOLDER VOIDING Optical inspection was carried out to further assess uniformity in BGA size, misalignments, and bridging or missing solder balls. The solder balls diameter and height were precisely measured by 3D profilometry as shown in Fig. 10. Figure 10. Optical inspection (top) and 3D profilometry (bottom) indicating precise dimensions of the paste printed solder balls after reflow. The achieved ball diameter, averaged over 20 measurements from three different samples, was in the range of μm as reported in Table IV, within 2% tolerance of the stencil calculations. TABLE IV. BALL DIAMETER OF PASTE PRINTED BGAS: DESIGN VS. ACTUAL Ball diameter Value BGA balling was performed on individual test glass coupons with optimized reflow conditions and were imaged again by X-ray microscopy to verify for solder voiding, beading or bridging, with no observable defects as indicated in Fig. 9. Target Stencil calculation (300μm opening with 5 mil thickness) Measured Variation 250 μm 248 μm μm 1-5 μm 4) Ball shear evaluation To confirm good wetting and solderability, ball shear tests were conducted on balled glass test coupons. The ball shear force was compared to that of SAC105 BGAs, formed in a standard industry based ball-drop process. Solder balls from the corners of the sample, edges and the center region were sheared, with an average strength of 5.4 kgf/mm 2, as reported in Fig. 11. The shear force was found comparable to that of the ball-drop BGAs with minor discrepancies that can be explained by variations in alloy composition, surface finish, and subsequent interfacial reaction. Figure 9. X-ray characterization after BGA balling and reflow showing no solder voids, bridging or beading 1381

6 6) Shadow-Moiré warpage response To confirm this theory, after BGA balling, Shadow-Moiré interferometry measurements were taken on both low- and high-cte glass substrates, from 30 C to 150 C, to study their warpage behavior as shown in Fig. 13. Figure 11. Measured ball shear strength for the paste-printed vs. ball-drop BGA solder balls. 5) BGA balling and yield evaluation To allow for evaluation of the three target solder alloys, the glass panels were quartered by CO 2 laser by Micron Laser Technology, after chip-level assembly, as shown in Fig. 12. Figure 12. Laser dicing of glass panels into quarters and BGA balling with SACm, SAC305 and SAC105. BGA balling was completed on the two low-cte and one-half high-cte panels with SACm TM, SAC305 and SAC105 solders using optimized paste printing and reflow parameters. A quarter of each of the low-cte panels balled with SACm was reserved for polymer collar fabrication to investigate its combined effectiveness to the doped solder alloy on further improving thermal cycling reliability. The BGA balled substrates were finally laser diced for singulation into individual glass BGA packages, ready for SMT assembly. Evaluation of the BGA balling yield is reported in Table V. On the low-cte samples, excellent yield was achieved, apart from minor non-uniformities in BGA size near the corners of the panels. On the high-cte samples, the observed yield loss was caused by massive solder bridging. The latter can be attributed to the aggravated warpage as a result of higher-cte mismatch between the low-cte (2.7 ppm/ C) die and the high-cte glass substrate (9.8 ppm/ C). TABLE V. BGA BALLING YIELD ON PARTS FROM QUARTER PANELS Type Solder Balling yield SACM 18/18 Low-CTE panel (with SAC305 8/9 100μm die) SAC105 6/9 Low-CTE panel (with 200μm die) SACM 18/18 SAC305 7/9 SAC105 9/9 High-CTE panel (with SACM 11/18 100μm die) % Total BGA balling yield 86% Figure 13. Warpage behavior by Shadow-Moiré interferometry on a low- CTE glass package with a 100μm-thick die. JEDEC-defined full-field warpage signatures along the diagonals of the measured packages are plotted in Fig. 14. The warpage results indicate an expected higher net warpage of high-cte samples compared to their low-cte counterparts. Warpage of a poorly yielded high-cte sample was found significantly greater than that of a yielded sample, with 263μm instead of 198μm at room temperature, demonstrating the prevalent role of warpage in degradation of the BGA balling yield. These discrepancies in warpage response can be attributed to visible variations in underfill fillet size, as reported in [14]. Figure 14. Net warpage temperature response of low- and high-cte glass packages with considerations of BGA balling yield. 7) Solder paste flux residue removal After reflow, low amounts of paste flux residue was noticed on the surface of substrates, around the solder balls. Although, the solder paste from Indium is no-clean rated, any surface contamination would impede fabrication of the circumferential polymer collars. Flux residue cleaning was therefore necessary. Cleaning by ultra-sonication in an acetone bath produced the best results of all tested methods, 1382

7 as illustrated in Fig. 15. The samples were cleaned again with isopropyl alcohol and baked at 150 C for one hour to remove any moisture, prior to board-level assembly. Figure 15. BGA before (left) and after (right) paste flux residue removal Polymer collars were fabricated by spin coating process and drying at 70 C for 1 hour. Polymer collar development and optimization is further discussed and detailed in [15]. C. Board-level Interconnections 1) Board-level assembly and characterization The BGA balled packages were then assembled onto the dedicated PCBs with ENEPIG surface finish, using a Finetech Matrix fineplacer with a 10 mm x 10 mm preleveled vacuum-locked spring gimbal tool, using no-clean tacky flux. Consistent with the reflow profile of standard SMT processes, the optimized reflow conditions were used to minimize BGA voiding. X-ray characterization was performed again to confirm that all joints were well formed, with no non-wet, unformed solders and no head-on-pillow defects as confirmed in Fig. 16. Suitable intermetallic formation was confirmed by crosssectioning and scanning electron microscopy and energy dispersive spectrometry (SEM/EDS) elemental analysis of the joints composition. In the case of SAC305 interconnections shown in Fig. 17 as an example, expected formation of Cu 6Sn 5 was confirmed on the package side with ultra-thin nickel-free EPAG surface finish, while both (Cu,Ni) 6Sn 5 and Ni 3Sn 4 were formed with ENEPIG finish on PCB side. Glass Package Die PCB Figure 16. Single-chip glass package mounted on PCB: (left) optical imaging, and (right) X-ray imaging. Figure 17. Optical and SEM/EDS characterization of paste-printed BGA after board-level assembly 2) Yield evaluation A total of 56 samples were assembled. After SMT assembly, electrical measurements of the daisy chain resistances confirmed a 91% yield, with two out of 50 nonyielded samples from the low-cte batch due to insufficient fluxing, while three of the high-cte packages encountered warpage-related challenges during pick-and-place assembly. Detailed yield results as well as the thermomechanical reliability evaluation plan, considering variations in die thickness, solder alloy and polymer collars, are recapped in Table VI. TABLE VI. SUMMARY OF SMT ASSEMBLY YIELD AND THERMAL CYCLING TEST PLAN Package Type Interconnection Assembly No. of TCT Yield Samples SACM 7/7 5 SACM Low-CTE glass 6/6 5 with collar (with 100μm die) SAC305 5/6 3 SAC105 4/5 3 SACm 7/7 5 SACm Low-CTE glass 7/7 5 with collar (with 200μm die) SAC305 6/6 3 SAC105 6/6 3 High-CTE glass (with 100μm die) SACM 3/6 3 % Total SMT assembly yield 51/56 = 91% 35 Shadow-Moiré interferometry measurements were taken again after board-level assembly (Fig. 18). These measurements were taken from the backside of the PCB. The results indicate lowest net warpage on the high-cte samples, due to lower CTE mismatch between the package and the organic PCB. The low-cte packages with polymer collars, both with 100 and 200 m-thick dies show lower net warpage, compared to samples without collars in the evaluated temperature range of 30 C to 150 C, presumably hinting at better board-level reliability performance. A maximum difference in net warpage of 119μm was measured on the low-cte glass samples with 100μm-thick die, which should not be significant enough for a noticeable system-level reliability impact. 1383

8 Figure 20. Resistance measurements for corner daisy chain #1 sample configurations with the 100μm-thick die. Figure 18. Net warpage response after board-level assembly, measured from PCB backside. To address the warpage-related yield loss experienced with high-cte samples, the assembly sequence may be modified as described in Fig. 19, with a chip-last approach. Such assembly sequence, combined to optimized thermocompression bonding profiles, has been proven efficient for warpage mitigation of 30 mm x 40mm of 2.5D silicon interposers in high-performance computing [16]. Figure 19. Assembly sequence modification from chip-first (left) to chiplast (right) for high-cte glass BGA packages. IV. THERMAL CYCLING RELIABILITY TEST Thermal cycling test was conducted following JEDEC JESD22-A104D standards, between temperatures of -40 C and 125 C with a dwell time of 15 minutes at each temperature extreme, completing one cycle per hour. The resistance of each daisy chain of the test vehicles in test was monitored every 100 cycles. The failure criteria were either an increase in the chain resistance by 20% or an electrically open daisy chain. All samples have passed 600 thermal cycles to date, with stable daisy-chain resistance values. Electrical measurements for corner circuit #1 are plotted in Fig. 20. This test is still ongoing and will be pursed until failure. V. SUMMARY AND CONCLUSIONS Thermomechanical board-level reliability of large, single-chip glass BGA packages, emulating an application processor, was investigated in this paper, with considerations of assembly yield and warpage. Beyond conventional solders, the novel Mn-doped SACm alloy developed by Indium corporation was introduced in conjunction to reworkable polymer collars to further enhance the reliability performance with a combination of strain relief and warpage mitigation, with minimum system-level impact. Daisy chain test vehicles were designed and fabricated with 100μm-thick low- and high-cte glass substrates, 18.5mm in body size. Silicon test dies, 10mm in size and μm in thickness, were assembled by thermocompression bonding, followed by capillary underfilling. BGA balling with stencil printing was developed and optimized at 400μm pitch to enable evaluation of the SACm alloy, only available in paste form, and its comparison to standard SAC105 and SAC305. Optical, X-ray and SEM/EDS characterizations were performed to optimize the reflow profile to achieve excellent solderability, suitable intermetallic formation and minimal voiding. Shadow-Moiré warpage measurements were used to characterize and analyze the BGA balling and board-level assembly yields of 86% and 91%, respectively. As expected, more significant warpage was observed on high-cte glass packages after chip-level assembly, highly conditioned by the underfill fillet size, degrading the BGA balling yield due to bridging of the solder paste. At boardlevel, low-cte packages predictably presented greater warpage than high-cte packages. The application of polymer collars was however found to reduce warpage by 9-16μm, with subsequent reliability improvements. This work also highlighted the significance of the assembly sequence in warpage mitigation, with considerations for a chip-lastassembly approach for high-cte packages. The assemblies were then subjected to thermal cycling at -40/125 C, and passed 600 cycles with stable daisy chains. This reliability evaluation is still ongoing and will be pursued until failure to demonstrate glass substrates as an ideal system integration platform, ACKNOWLEDGMENTS This study was supported by the Interconnections and Assembly program at the GT-PRC. The authors also thank 1384

9 Asahi Glass Company for providing glass panels, ASE for wafer fabrication and bumping, Namics Corporation for their polymer collar material, Atotech for surface finish processing, and Indium Corporation for supplying the solder pastes, and Zeon Corporation and Rogers Corporation for providing dielectric build-up materials. The authors would also like to acknowledge Gaëtan Delétoille, and Laura Wambera for their experimental contributions. REFERENCES [1] Kim, Deok-Hoon, et al. "Solder joint reliability of a polymer reinforced wafer level package." Microelectronics Reliability (2002): [2] Shnawah, Dhafer Abdulameer, Mohd Faizul Mohd Sabri, and Irfan Anjum Badruddin. "A review on thermal cycling and drop impact reliability of SAC solder joint in portable electronic products." Microelectronics Reliability 52.1 (2012): [3] Liu, Weiping, et al. "Achieving high reliability low cost lead-free SAC solder joints via Mn or Ce doping." Electronic Components and Technology Conference, ECTC th. IEEE, [4] Liu, Weiping, and Ning-Cheng Lee. "The effects of additives to SnAgCu alloys on microstructure and drop impact reliability of solder joints." JOM 59.7 (2007): [5] Reche, John JH, and Deok-Hoon Kim. "Wafer level packaging having bump-on-polymer structure." Microelectronics Reliability 43.6 (2003): [6] Topper, M., et al. "Wafer level package using double balls." Advanced Packaging Materials: Processes, Properties and Interfaces, Proceedings. International Symposium on. IEEE, [7] Brunnbauer, Markus, et al. "Embedded wafer level ball grid array (ewlb)." Electronic Manufacturing Technology Symposium (IEMT), rd IEEE/CPMT International. IEEE, [8] Meynen, H., et al. "Ultra low stress and low temperature patternable silicone materials for applications within microelectronics." Microelectronic engineering 76.1 (2004): [9] Bhat, Anirudh. "Response of multi-path compliant interconnects subjected to drop and impact loading." (2012). [10] Qin, Xian, et al. "Large silicon, glass and low CTE organic interposers to printed wiring board SMT interconnections using copper microwire arrays." Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd. IEEE, [11] Singh, Bhupender, et al. "First demonstration of drop-test reliability of ultra-thin glass BGA packages directly assembled on boards for smartphone applications." Electronic Components and Technology Conference (ECTC), 2015 IEEE 65th. IEEE, [12] Standard IPC, I. P. C. "7525 Stencil Design Guidelines." Stencil Design Task Group (5-21e) of the Assembly and Joining Process Committee of IPC (2000): 3. [13] Product Data Sheet. Indium Corporation, Indium8.9 Pb-Free Solder Paste SACm TM [14] McCann, Scott R., et al. "Flip-chip on glass (FCOG) package for low warpage." Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th. IEEE, [15] Menezes, Gary, et al. "Large low-cte glass package-to-pcb interconnections with solder strain-relief using polymer collars." Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th. IEEE, [16] Mirkarimi, Laura, et al. "Analytical and Experimental Studies of 2.5 D Silicon Interposer Warpage: Impact of Assembly Sequences, Materials Selection and Process Parameters." (2014). 1385