Fabrication and Manufacturing (Basics) Batch processes

Transcription

1 Fbriction nd Mnufcturing (Bsics) Btch processes Fbriction time independent of design complexity Stndrd process Customiztion by msks Ech msk defines geometry on one lyer Lower-level msks define trnsistors Higher-level msks define wiring Silicon is net stuff Oxide protects things from impurities Cn be etched selectively on silicon or metl Cn be doped Add P or As impurities EE 261 Krish Chkrbrty 1 CMOS Fbriction CMOS trnsistors re fbricted on silicon wfer Lithogrphy process similr to printing press On ech step, different mterils re deposited or etched Esiest to understnd by viewing both top nd cross-section of wfer in simplified mnufcturing process EE 261 Krish Chkrbrty 2 1

2 Mking Chips Msks Chemicls Processing Processed wfer Chips Wfers EE 261 Krish Chkrbrty 3 Inverter Cross-section Typiclly use p-type substrte for nmos trnsistors Requires n-well for body of pmos trnsistors A GND Y V DD SiO 2 n+ diffusion n+ n+ p+ n well p+ p+ diffusion polysilicon metl1 nmos trnsistor pmos trnsistor EE 261 Krish Chkrbrty 4 2

3 Well nd Substrte Tps Substrte must be tied to GND nd n-well to V DD Metl to lightly-doped semiconductor forms poor connection clled Shottky Diode Use hevily doped well nd substrte contcts / tps GND A Y V DD p+ n+ n+ p+ p+ n+ n well substrte tp well tp EE 261 Krish Chkrbrty 5 Inverter Msk Set Trnsistors nd wires re defined by msks Cross-section tken long dshed line A Y GND V DD substrte tp nmos trnsistor pmos trnsistor well tp EE 261 Krish Chkrbrty 6 3

4 Detiled Msk Views Six msks n-well Polysilicon n+ diffusion p+ diffusion Contct Metl n well Polysilicon n+ Diffusion p+ Diffusion Contct Metl EE 261 Krish Chkrbrty 7 Bsic Processing Steps N-diffusion creted by doping regions of the substrte Poly nd metl re lid over the substrte, with oxide to insulte them from substrte nd ech other Wires re dded in lyers, lternting with oxide Vis re cut in the oxide EE 261 Krish Chkrbrty 8 4

5 Fbriction Steps Fetures re ptterned on wfer by photolithogrphic process Photo-light lithogrphy, n. process of printing from plne surfce on which imge to be printed is ink-receptive nd the blnk re is ink-repellnt Cover the wfer with light-sensitive, orgnic mteril clled photoresist Expose to light with the proper pttern (msk) Ptterns left by photoresist cn be used to control where oxide is grown or mterils re plced on surfce of wfer EE 261 Krish Chkrbrty 9 Fbriction Steps Lyout contins informtion on wht ptterns hve to mde on the wfer Msks re creted using the lyout informtion provided by the designer Procedure involves selective removl of the oxide Cot the oxide with photoresist, polymerized by UV light (pplied through msk) Polymerized photoresist dissolves in cid Photoresist itself is cid-resistnt EE 261 Krish Chkrbrty 10 5

6 Fbriction Steps Strt with blnk wfer Build inverter from the bottom up First step will be to form the n-well Cover wfer with protective lyer of SiO 2 (oxide) Remove lyer where n-well should be built Implnt or diffuse n dopnts into exposed wfer Strip off SiO 2 EE 261 Krish Chkrbrty 11 Oxidtion Grow SiO 2 on top of Si wfer C with H 2 O or O 2 in oxidtion furnce SiO 2 EE 261 Krish Chkrbrty 12 6

7 Photoresist Spin on photoresist Photoresist is light-sensitive orgnic polymer Softens where exposed to light Photoresist SiO 2 EE 261 Krish Chkrbrty 13 Lithogrphy Expose photoresist through n-well msk Strip off exposed photoresist Photoresist SiO 2 EE 261 Krish Chkrbrty 14 7

8 Etch Etch oxide with hydrofluoric cid (HF) Seeps through skin nd ets bone; nsty stuff!!! Only ttcks oxide where resist hs been exposed Photoresist SiO 2 EE 261 Krish Chkrbrty 15 Strip Photoresist Strip off remining photoresist Use mixture of cids clled pirnh etch Necessry so resist doesn t melt in next step SiO 2 EE 261 Krish Chkrbrty 16 8

9 n-well n-well is formed with diffusion or ion implnttion Diffusion Plce wfer in furnce with rsenic gs Het until As toms diffuse into exposed Si Ion Implnttion Blst wfer with bem of As ions Ions blocked by SiO 2, only enter exposed Si SiO 2 n well EE 261 Krish Chkrbrty 17 Strip Oxide Strip off the remining oxide using HF Bck to bre wfer with n-well Subsequent steps involve similr series of steps n well EE 261 Krish Chkrbrty 18 9

10 Polysilicon Deposit very thin lyer of gte oxide < 20 Å (6-7 tomic lyers) Chemicl Vpor Deposition (CVD) of silicon lyer Plce wfer in furnce with Silne gs (SiH 4 ) Forms mny smll crystls clled polysilicon Hevily doped to be good conductor Polysilicon Thin gte oxide n well EE 261 Krish Chkrbrty 19 Polysilicon Ptterning Use sme lithogrphy process to pttern polysilicon Polysilicon Polysilicon Thin gte oxide n well EE 261 Krish Chkrbrty 20 10

11 Self-Aligned Process Use oxide nd msking to expose where n+ dopnts should be diffused or implnted N-diffusion forms nmos source, drin, nd n-well contct n well EE 261 Krish Chkrbrty 21 N-diffusion Pttern oxide nd form n+ regions Self-ligned process where gte blocks diffusion Polysilicon is better thn metl for self-ligned gtes becuse it doesn t melt during lter processing n+ Diffusion n well EE 261 Krish Chkrbrty 22 11

12 N-diffusion cont. Historiclly dopnts were diffused Usully ion implnttion tody But regions re still clled diffusion n+ n+ n+ n well EE 261 Krish Chkrbrty 23 N-diffusion cont. Strip off oxide to complete ptterning step n+ n+ n+ n well EE 261 Krish Chkrbrty 24 12

13 P-Diffusion Similr set of steps form p+ diffusion regions for pmos source nd drin nd substrte contct p+ Diffusion p+ n+ n+ p+ p+ n+ n well EE 261 Krish Chkrbrty 25 Contcts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contct cuts re needed Contct p+ n+ n+ p+ p+ n+ Thick field oxide n well EE 261 Krish Chkrbrty 26 13

14 Metliztion Sputter on luminum (copper) over whole wfer Pttern to remove excess metl, leving wires Metl Metl p+ n+ n+ p+ p+ n+ Thick field oxide n well EE 261 Krish Chkrbrty 27 Bsic Processing Steps (Summry) Strt with wfer t current step Add photoresist Pttern photoresist with msk Step-specific etch, implnt, etc. Wsh off resist EE 261 Krish Chkrbrty 28 14

15 Lyout Chips re specified with set of msks Minimum dimensions of msks determine trnsistor size (nd hence speed, cost, nd power) Feture size f = distnce between source nd drin Set by minimum width of polysilicon Feture size improves 30% every 3 yers or so Normlize for feture size when describing design rules Express rules in terms of λ = f/2 E.g. λ = 0.3 μm in 0.6 μm process EE 261 Krish Chkrbrty 29 Design Rules Design rules govern the lyout of individul components: trnsistors, wires, contcts, vis How smll cn the gtes be, nd how smll cn the wires be mde? Conflicting Demnds: component pcking: more functionlity, higher speed Chip yield: smller sizes cn reduce yield (frction of good chips) Conservtive vs ggressive design rules EE 261 Krish Chkrbrty 30 15

16 Foundry Interfce Lyout (msk set) Designer Foundry Design Rules Process Prmeters EE 261 Krish Chkrbrty 31 Geometric Design Rules Resolution Width nd spcing of lines on one lyer Alignment mke sure intercting lyers overlp (or don t) Contct surround Poly overlp of diffusion Well surround of diffusion EE 261 Krish Chkrbrty 32 16

17 SCMOS Design Rules Sclble CMOS design rules Feture size λ= hlf the drwn gte length (poly width) Mentor Grphics IC tool hs built-in design rule checker (DRC) Exmple design rules: Lyer Minimum Width Seprtion Metl 1 3 λ 3 λ Metl 2 3 λ 4 λ Poly 2 λ poly-poly: 2 λ poly-diff: 1 λ EE 261 Krish Chkrbrty 33 Simplified Design Rules Conservtive rules to get you strted EE 261 Krish Chkrbrty 34 17

18 Tub Ties nd Ltchup Substrte must be connected to power supply p-tub for nmos to V SS (Gnd) N-tub for pmos to V DD Connections mde by specil vis clled tub ties Conservtive design rule: plce tub ties for every one or two trnsistors Why not plce one tie in ech tub tht hs 50 trnsistors? EE 261 Krish Chkrbrty 35 Ltchup Too few ties: high resistnce between tub nd power supply, leds to prsitic bipolr trnsistors inhibiting norml chip opertion Prsitic silicon-controlled rectifier (SCR) When both bipolr trnsistors re off, SCR conducts no current SCR turns on: high current short-circuit between V DD nd Gnd. V DD V DD p + n + n + p + p + n + R nwell p-source n-well R nwell R psubs p-substrte n-source R psubs () Origin of ltchup (b) Equivlent circuit EE 261 Krish Chkrbrty 36 18

19 Gte Lyout Lyout cn be very time consuming Design gtes to fit together nicely Build librry of stndrd cells Stndrd cell design methodology V DD nd GND should but (stndrd height) Adjcent gtes should stisfy design rules nmos t bottom nd pmos t top All gtes include well nd substrte contcts EE 261 Krish Chkrbrty 37 Inverter Lyout Trnsistor dimensions specified s Width / Length Minimum size is 4λ / 2λ, sometimes clled 1 unit In f = 0.6 μm process, this is 1.2 μm wide, 0.6 μm long EE 261 Krish Chkrbrty 38 19

20 Exmple: Inverter EE 261 Krish Chkrbrty 39 Exmple: NAND3 Horizontl N-diffusion nd p-diffusion strips Verticl polysilicon gtes Metl1 V DD ril t top Metl1 GND ril t bottom 32 λ by 40 λ EE 261 Krish Chkrbrty 40 20

21 Stick Digrms Stick digrms help pln lyout quickly Need not be to scle Drw with color pencils or dry-erse mrkers EE 261 Krish Chkrbrty 41 Stick Digrms Designing complete lyout in terms of rectngles cn be overwhelming Stick digrm: bstrction between trnsistor schemtic nd lyout Crtoon of chip lyout Replce rectngles by lines V DD trnsistor V DD (blue) p-type diffusion (yellow) Gnd Poly (red) n-type diffusion (green) Metl 1 (blue) V SS (Gnd) EE 261 Krish Chkrbrty 42 21

22 Stick Digrm V DD Metl 1 V DD z b p-diffusion b b Gnd Poly n-diffusion Metl 1 Gnd EE 261 Krish Chkrbrty 43 Wiring Trcks A wiring trck is the spce required for wire 4 λ width, 4 λ spcing from neighbor = 8 λ pitch Trnsistors lso consume one wiring trck EE 261 Krish Chkrbrty 44 22

23 Well spcing Wells must surround trnsistors by 6 λ Implies 12 λ between opposite trnsistor flvors Leves room for one wire trck EE 261 Krish Chkrbrty 45 Are Estimtion Estimte re by counting wiring trcks Multiply by 8 to express in λ EE 261 Krish Chkrbrty 46 23

24 Exmple: O3AI Sketch stick digrm for O3AI nd estimte re Y = ( A+ B+ C) D EE 261 Krish Chkrbrty 47 Exmple: O3AI ( ) Y = A+ B+ C D Sketch stick digrm for O3AI nd estimte re EE 261 Krish Chkrbrty 48 24

25 Exmple: O3AI Y = A+ B+ C D Sketch stick digrm for O3AI nd estimte re ( ) EE 261 Krish Chkrbrty 49 Some Lyout Hints Pln the globl structure ( big picture ), then design cells Floorpln Wiring strtegy Power nd ground distribution Systemtic plcement Keep ll pmos/nmos together Plce trnsistors in rows: shre source/drin diffusion Wiring on orthogonl metl lyers Assign preferred directions to M1 nd M2 Use diffusion only for devices, not for interconnect Use poly only for very locl interconnect EE 261 Krish Chkrbrty 50 25

26 Cell Minimiztion Chip re (cell size) must be minimized crefully Impct of die size/chip re on cost (unpckged dies) Nominl 1% increse 15% increse Pentium die in die size in die size Wfer cost $1,460 $1,460 $1,460 Die size mm mm mm 2 Die cost $84.06 $85.33 $ Chips 1% increse in die size leds to 3% fbricted decrese in stock price for Intel! per week K K K Added nnul cost $63.5 M $961 M EE 261 Krish Chkrbrty 51 Minimize number of diffusion strips How do we order the gte inputs (poly)? More diffusion strips more spcing, more re V DD Try, b, c, d, e: e d V DD x x x x x b c F F d e b c x x x x x x x b c d e Gnd Two n-diff gps, zero p-diff gps EE 261 Krish Chkrbrty 52 26

27 V DD e b e d b c d d e c b c pmos grph nmos grph b d e c Gnd EE 261 Krish Chkrbrty 53 Euler pth: Visit every edge exctly once Find ll Euler pths for nmos nd pmos grphs Find p- nd n-pth tht hve identicl lbeling For exmple: d, e,, b, c If no such pth exists, then brek diffusion into strips EE 261 Krish Chkrbrty 54 27

28 V DD pmos grph e b e d b c d d e c b c nmos grph V DD b F x x x x x d e c Gnd F Ordering: d, e,, b, c: Zero n-diff gps, zero p-diff gps x x x x x Gnd d e b c EE 261 Krish Chkrbrty 55 Summry MOS Trnsistors re stck of gte, oxide, silicon Cn be viewed s electriclly controlled switches Build logic gtes out of switches Drw msks to specify lyout of trnsistors Now you know everything necessry to strt designing schemtics nd lyout for simple chip! EE 261 Krish Chkrbrty 56 28