Solder Joint Reliability Design Implications From Finite Element Modeling and Experimental Testing

Transcription

1 Solder Joint Reliability Design mplications From Finite Element Modeling and Experimental Testing H. K. Charles, Jr. G. V. Clatterbaugh The Johns Hopkins University, Applied Physics Laboratory, Laurel, Maryland An extensive finite element modeling and experimental testing program has been carried out to determine the most optimum design parameters for solder joints in surface mount applications. Although the analysis and testing (power cycling and thermal cycling) has been carried out for a variety of package styles, particular attention will be paid to the result for leadless ceramic chip carriers. This package is particularly useful in certain high performance military and commercial applications. Analysis and experimentation indicate that increased fatigue life under power cycling can be attained by fabricating solder joints with large fillets and low standoff heights. The large fillet geometry significantly reduces harmful stress concentrations while increasing the net cross-sectional area within the joint. Both factors tend to improve the fracture toughness of the joint. The temperature and frequency dependencies of solder joint fatigue life under power cycling testing is discussed. The observed frequency dependence can be minimized by eliminating harmful tensile strain components thus reducing harmful stress relaxation and tensile induced oxygen embrittlement of grain boundaries. Temperature cycling studies indicate joints with slightly higher standoffs and low fillet angles are more resistant to cyclic fatigue than pillar type joints which tend to focus shear strains at the interfaces. Solder joints can be tapered to improve overall reliability but, in most cases, tapering will provide only a small increase in fracture toughness of the joint through the elimination of stress concentrations. Additional fatigue life increases can be obtained only through an enlargement of the joint cross-sectional area. Aspects of the above results will be presented in detail along with design guidelines for creating high reliability solder joints for various application scenarios. ntroduction The trend in microelectronics since its inception has been to extend the applications of electronic devices into areas where stringent requirements in size, density, speed, reliability and complexity have forced the need to develop innovative techniques in microminiaturization. With the advent of Very Large Scale ntegrated (VLS) circuits and Very High Speed ntegrated Circuits (VHSC), electronic packaging engineers are faced with the task of designing packages and assemblies that can accommodate increased power dissipation, number of pin outs, and circuit densities while at the same time reducing weight, package dimensions, and production costs. n particular, the area of thermal design analysis of electronic packages, interconnects and assemblies is a key activity in the development of improved technology and reliability for electronic system integration. Thermal (thermomechanical) design represents a critical preproduction step necessary to ensure Contributed by the Electrical and Electronics Packaging Division and presented at the Winter Annual Meeting, San Francisco, Calif. December 0-5,989 of THE AMERCAN SOCETY OF MECHANCAL ENGNEERS. Manuscript received at ASME headquarters April, 990. Paper No. 90-WA/EEP-22. adequate thermal management and system reliability prior to actual fabrication. The Finite Element Method (FEM) was chosen for the thermal analysis presented in this study because of its straightforward implementation and the availability of both pre- and post-processor computer-aided engineering tools, which allowed rapid construction, automatic data generation, and subsequent analysis of complex thermal models. The NASTRAN finite element method code [] was chosen because of its availability and its proven ability to provide reliable approximate solutions to both thermal and thermomechanical problems. The study will focus on five primary subject areas: The thermal analysis of VLS circuit packages, surface mount assemblies, and hybrid microcircuits; 2 Thermomechanical stress and low cycle fatigue in softsoldered interconnections; 3 Accelerated testing and reliability of soft soldered interconnection for surface mounted components; Journal of Electronic Packaging JUNE 990, Vol. 2/ Copyright 990 by ASME Downloaded From: on 02/8/20 Terms of Use:

2 Chip carrier Solder AiiiiiJaSiiiiiiiii joints \ Substrate V////^ix Die attach y alloy/adhesive A ^'A//////////////A R j-[ ' Tj (Junction) TDA (Die attach) nu R eda-c D < \ TC (Carrier) R 8c Rfls Ts (Solder) Tss (Substrate) R %S-HS THSA (Heat sink) fl 0HSA-HS ^ attach) THS (Heat sink) TA (Ambient)! R e=i Rem Ambient i Fig. Typical thermal resistance (R e) path from the semiconductor junction to the ambient (reference temperature of the environment, etc.) for a surface-mounted chip carrier assembly Specific techniques for surface mount solder joint fabrication; and 5 Design guidelines for reliable surface mount assemblies. FEM Analysis The thermal analysis of a complex microcircuit assembly using the FEM technique is most expediently and economically done by dividing the overall problem into several smaller, more tractable ones. An attempt to construct a model that incorporates an entire microcircuit assembly consisting of many components would require the use of a large high speed computer with vast memory allocation. On the other hand, although individual components can be modeled quite accurately and economically with small computers, care must be exercised not to over simplify the model because unacceptable inaccuracies may result. Reducing surface mounted components and packages into equivalent lumped heat-transfer elements through individual, detailed FEM models can be a useful method in transforming large, complex circuit boards into relatively simple thermal networks. The first step in such a procedure requires the numerical estimation of the lumped element thermal parameters (e.g., thermal resistances, heat capacitances, etc.) for the individual circuit board components. This is accomplished by dividing the component into finite elements and specifying the boundary conditions such as temperatures, heat gradients, etc. Passive elements (such as capacitors) can often be assigned thermal heat capacitance values (mass times heat capacity), and hand-calculated thermal resistance estimates are sufficient. Components or packages that involve internal heat dissipation or active device heat generation require sufficiently detailed thermal models to adequately capture the large thermal gradients present. Historically, detailed temperature models were required only for individual transistor or integrated circuit packages, since junction temperature estimates were of primary concern. However, for surface-mount applications, where significant thermal stress at solder joints may occur, more complete temperature information is required to accurately assess interconnection reliability for all soldered components. All linearized conductive and convective heat-transfer mechanisms can be included at the component level of analysis. The resulting estimates for component thermal resistance used in the lumped element formulation of the final analysis will reflect the assumed heat-transfer mechanisms built into each component. After each individual component or package is replaced by its lumped thermal equivalent, the substrate (printed wiring board, thick film ceramic, etc.) can then be divided into finite elements, each bounded by nodal points to which the 3/Vol. 2, JUNE 990 Castellation Solder fillet Heat-dissipating device Chip carrier Ceramic"\ ^multilayer circuit board ^Vi^JN? 5^^, Solder / XJs^ Substrate, Heat sink Heat sink Eightfold Chip carrier symmetrical wedge Fig. 2 A finite element model for the thermal analysis of a leadless ceramic chip carrier solder mounted to a multilayer board with an integral heat sink. Because of the carrier's symmetry, only one-eighth of the package has to be modeled in detail previously estimated lumped component and package elements are thermally connected. The basic concept behind the thermal analysis of a surface mounted assembly is shown schematically in Fig.. The temperature of interest is the device junction temperature which can be found by summing all the thermal resistances along the heat path from the source (the chip) to the sink (the ambient, lead frame, cold plate, etc.). Each of the thermal resistances can be estimated by using FEM techniques. The FEM models can depend on complex loss mechanisms such as convection (natural and forced air) and radiation which tend to be non-linear and thus require iterative solutions. n many practical surface-mount implementations, some or all of these effects can be neglected thus simplifying calculation complexity and reducing computer time and cost. The Component Model The analysis of a particular component of interest begins with the geometrical model construction by dividing the component into a -, 2-, or 3-dimensional mesh containing grid points or nodes. The grid points serve as the demarcation for the finite element which occupies the space bounded by a particular set of grid points. Figure 2 shows a FEM model of a -pin leadless chip carrier. Only one-eighth of the part is divided into finite elements because of the symmetry of the carrier and the assumed square die located at the center of the carrier. Three-dimensional rectangular and wedge shaped elements are used in this model. The substrate or board is included in the calculation to allow for radiation and convective cooling from the bottom of the substrate. Another reason for including the board is to address the situations shown in Fig. 3 where the chip carrier footprint does not correspond to the symmetrical grid pattern chosen to represent the board. n order to treat the chip carrier as a lumped element in the board calculation - a precise method for connecting thermally the component to the substrate (i.e., to a grid point or set of board grid points) must be developed. Distributing the elements thermal load via a thermal resistor (Fig. 3) requires a knowledge of the thermal resistance between the device (package) and a particular location (grid point or points) on the board. Most finite element codes with a thermal analysis capability contain thermal resistance elements. These elements, when coupled with an estimation of thermal resistance from the chip to specific board grid point locations (via individual device thermal models, e.g., Fig. and 2), allow the final lumped element board model to be completed. The model may include the entire circuit board or only a portion, depending upon board size and component density. Attached heat sinks or cold plates may be included at this point in the analysis as shown in Fig.. f the heat sink is in thermal equilibrium with the environment (e.g., temperature of heat sink should be relatively constant in Transactions of the ASME Downloaded From: on 02/8/20 Terms of Use:

3 A () (2) (3) () (5) t ( ( > () mi -Chip carrier'-^ [2 vz m # (2) (8) Substrate (9) (3) () (0) (5) Castellation FEM joint under package determines height () ^ < () R2- y (7) (8) (9) ) > i R^' 2 i a) M J/ R 2-7jf f() U)J l\ l3> R2-2 > R 2-8 (8) () (5) Tl \ (9) A! 0 ' Substrate B Vol.=.9x0- cm 3 D - Re =.87-C/W C ~ E _Vol.=.9x0- cm 3 - Re = 9. C/W Vol. =.x0""cm J Re = 8.90 C/W Vol. = 8.2x0- cm 3 Re = 8.88-C/W rv () (7) (8) (9) (20) /<) M2) Fig. 3 Schematic representation of the procedure for distributing power from a component generating heat to the underlying substrate. View A illustrates an asymmetrical component position with respect to an arbitrarily chosen FEM nodal or grid pattern for the underlying substrate. View B uses the junction temperature of the chip carrier packaged integrated circuit as a point power source located at nodal point 2. Resistors then distribute power to the various substrate grid point locations Substrate < (3) Heat sink Fig. Typical thermal analysis model for a 0-component [A to J] surface mounted hybrid assembly with a substrate mounted heat sink. both power-on and power-off conditions), the analysis is complete. f this is not the case, the analysis is extended to the circuit housing or the next larger heat sink. Thermal Resistance Figure 5 is the finite element model used to estimate thermal resistance of a surface mount solder joint. Thermal conductivities for eutectic tin lead Sn3 (3 wt. % Sn, 37 wt. % Pb) and Sn2 (2 wt. % Sn, 3 wt. % Pb, and 2% wt % Ag) solder were used in the analysis. Various joint geometries, as shown in Fig. 5, were considered with the result that even for a 250 /urn height, low volume joint (using Sn2 alloy) with a net thermal resistance of 9. C/W per joint the joint thermal resistance represents only 2 percent (when all joints in parallel are considered) of the total thermal resistance of a -piri leadless chip carrier. Thus, the effect of solder joint geometry, standoff height, and solder alloy are relatively insignificant from a thermal resistance point of view in most chip carrier applications. As the number of leads decreases, the effect of the solder joints, however, becomes a more significant contribution to overall thermal resistance - yet the analysis indicates that material selection and joint design should be based primarily on their mechanical and fatique properties rather Fig. 5 Finite element model thermal analysis to estimate thermal resistance [Re] for several surface mount package joining geometries. View A: basic joint FEM schematic representation. View B: 25pm high joint with nominal solder volume. View C: 250 jim high joint with solder volume equal to B. Views C & D: 250pm height increasing solder volume. than on their heat transfer characteristics. Similar statements can be made for most other surface mount package styles under normal operating conditions. Thermomechanical Behavior Typical soft solders (e.g., Sn3) are low work-hardening materials which exhibit non-linear viscoelastic behavior at typical surface mount system operating temperatures. They are usually quite ductile, with a tendency to creep at very low strain rates and exhibit some work-hardening at higher strain rates. Mechanical properties vary widely with respect to temperature [2], strain rate [3], and grain size []. Because their operating temperatures are relatively close to their low melting temperatures, soft solders exhibit fatigue and fracture properties similar to higher melting point materials (e. g., steel, nickel, etc.) operating at elevated temperatures. Many of the empirical results for high temperature, low-cycle fatigue can be applied to soft solder alloys operating near room temperatures. Low-cycle fatigue in surface-mounted soldered interconnections is observed primarily under conditions of power or temperature cycling when there is a large coefficient of thermal expansion (CTE) mismatch between the surface mount package and the substrate. More recently, the effect of strains induced by differential thermal expansion resulting from power cycling for matched coefficient of thermal expansion surface mount packages (chip carriers) and substrate materials has led to speculation concerning the reliability of soldered interconnections [5]. To date, however, there has been little evidence from either actual or simulated operational environmental power cycle testing [] to support such concerns. However, solder joints subject to sufficiently large mechanical strains from either temperature or power cycling environments will ultimately fail due to high temperature, low cycle fatigue. These failures can occur in the solder itself or in (or near) the usually brittle, intermetallic, solder joint-substrate metallization interface regions. The mechanical strains may result from the transient and steady-state thermal gradients that exist between a surface mount package and the substrate, as is the case for power cycling, or from the large differential thermal expansion of the package (ceramic or metal), the substrate Journal of Electronic Packaging JUNE 990, Vol. 2/37 Downloaded From: on 02/8/20 Terms of Use:

4 material, and the solder alloy. During temperature and powercycling dwell periods, creep and other temperature-dependent relaxation phenomena can occur, decreasing the amount of recoverable strain per cycle depending on both dwell and temperature. Simultaneously, cyclic softening [7] can occur which results in a lowering of the amount of stress required on each succeeding cycle to produce a given amount of strain (i.e., cyclic decrease in the elastic strain). n addition to these processes, temperature and stressinduced diffusion and intermetallic formation can occur at the solder joint-substrate metallization interface. n situations where bonding pads contain sufficient quantities of gold (or copper), tin diffusion into the pad metallization can result in the formation of weak intermetallic interfaces that may be incapable of withstanding additional stress cycling. Even in cases where strong joint-to-metal interfaces are formed, tin migration can leave a lead-rich solder with reduced fatigue and creep properties [8]. Oxygen embrittlement [9], observed in many fatigue specimens at elevated temperature, can enhance crack propagation by oxidizing cracks and grain boundaries while in tension, thus preventing partial rewelding while under compression. For example, one experimenter investigating the low cycle fatigue properties of high-lead-content solders used for die attach [0] reported crack initiation was rapid (nominally 300 cycles) in air and retarded (no cracking after 3000 cycles) for identical samples cycled in a vacuum. High temperature-low cycle fatigue failure mechanisms include pure fatigue, creep, stress relaxation, recovery, thermally aided diffusion, and corrosion. The ultimate number of cycles that a soldered interconnection can endure will be a function to varying degrees of all these competing mechanisms and their interrelationships to solder the alloy, joint geometry, reflow kinetics and both the package and board materials and geometries. The complex interaction between the competing failure mechanisms in soft soldered interconnections is not clearly understood; however, in order to accurately predict useful service life, it is necessary to identify which mechanism(s) predominate under a given set of operating or test conditions. Several fatigue models have been proposed by various authors [5,, 2] based on Coffin-Manson [3] or modified Coffin-Manson equations [3]. n particular, Englemaier [] derived a thermal fatigue model for eutectic tin-lead solder joints based on the frequency independent Coffin-Manson equation of the form: r FAy W "'= - 5 [-*r] where Nf is the number of cycles to failure, e f is the fatigue ductility coefficient, /3 is the fatigue ductility exponent, A7 is the shear strain range and F is an empirical factor. Working with this equation Engelmaier concluded that the solder fatigue data from Wild [5] could be fitted to his model if the fatigue ductility coefficient was related to the mean cycle solder joint temperature T s (in C) and the cyclic frequency v (in cycles/day) (i.e., (3=-0.2-(x 0~ ) r s n ( + P)), and the fatigue ductility coefficient was 2^=0.5. This formulation assumes that there are cylindrical solder joints with no stress concentrations in the solder or at the bond interface and that the applied stress is predominately shear stress. t excludes second order effects which may result in significant tensile or compressive strains, but the formula does have an empirical factor which takes into account variation in the physical and processing parameters that may affect joint reliability. Clearly, in cases where failure results from thermally enhanced diffusion processes, equations based on experimentally obtained isothermal fatigue data for solder would result in gross inaccuracies in reliability estimates (cycles to failure). 38/Vol. 2, JUNE 990 () Fig. FEM analysis of a leadless chip carrier solder joint under temperature cycling [23 to 25 C]. Contours with numbers less than or equal to 2 indicate regions where the Von Mises stress exceeds the 0.2% yield strength [~MPa at 25 C]. The maximum Von Mises stress is approximately 3.5 MPa. n diffusion kinetic dominated cases, solder fatigue relations should be abandoned in favor of rate equations of the Arrhenius type []. The Coffin-Manson type formalisms are based on crack propagation along slip planes. When these expressions are modified for high temperature, they appear quite similar to a creep relation based on a triple point cracking model. n situations where modified Coffin-Manson equations are valid - experimental determination of actual shear strains may be impossible for practical surface mount geometries. Simple flat plate (average temperature) models grossly overestimate [7] shears strains. n addition, how is an a priori determination made of the significant stress concentration factors which influence ultimate joint life? One approach is to formulate numerical computer solutions that can provide some data that are not readily assessable by experimental methods. The versatility of the FEM technique for solving complex thermomechanical stress problems of the type encountered in soldered interconnections provides an important alternate approach for obtaining critical strain in addition to a wealth of qualitative data. FEM Joint Analysis Temperature Cycled Solder Joints. Bond interfaces for temperature cycled solder joints can experience large strains due to mismatches between the coefficients of thermal expansion for the solder, and substrate, and the package. For example, large strains in chip carrier solder joints have been observed to cause thick film pad metallization delaminations from underlying thick film dielectric materials during wide temperature cycling extremes [8]. These CTE differences can also induce additional strains during power cycling environments in cases where power-on temperatures vary significantly from power-off temperatures. The following analysis' will evaluate the influence of solder joint design parameters on bond interface stresses produced by temperature cycling. A typical geometrical model is shown in Fig.. n order to account for differences in CTEs among the solder joint, the package, and the substrate, it is necessary to include all these elements in the model. Figure illustrates the case for a ceramic chip carrier, surface mounted to a thick film ceramic substrate. Because of the size and complexity of the model, the following assumptions were made: ) linear elastic Transactions of the ASME Downloaded From: on 02/8/20 Terms of Use:

5 X 7 >>$ o v = 90.7 MPa o h = 02.9 MPa h = 50.8 ^m L = 77.8^m h L Oh h L 92. MPa 0.0 MPa 50.8 urn 77.8 Mm 9.7 MPa 0.0 MPa 50.8 um 77.8 Mm o v =.8 MPa o h = 79. MPa h = 20.3 ^m L = 228.^m o v =.3 MPa o h = 7.0 MPa h = 25. urn L = 77.8/jm Fig. 7 FEM stress analysis results on five different chip carrier joint geometries under temperature cycling. A. High fillet angle with no side castellations B. High fillet angle with short side castellations C. High fillet angle with typical side castellations D. Low fillet angle, long pad length with typical side castellation D. Typical fillet angle with reduced standoff height analysis (neglecting plastic flow and time dependent effects); 2) a time averaged Young's modulus value over half the temperature cycle [7]; and 3) a Poisson's ratio of 0. [2]. Calculated approximate stresses should be somewhat higher than those actually observed due to localized plastic flow mechanism which are not accounted for in the FEM model; however, valuable information relating the influence of geometry on the degree of stress concentrated can be gained. n Fig., stress contours for the geometry and material conditions shown indicate areas of significant stress concentration. The largest stresses are seen to occur in the castellation region of the solder joint and reports of stress fracture here have appeared in the literature [9]. Other areas of high stress occur at the heel and toe of the solder joint. Multiple geometric models were constructed to estimate the tensile stress at the toe of the solder fillet when the joint was cooled from +25 C to -55 C. Again the material conditions assumed in Figure were utilized resulting in the typical configurations illustrated in Fig. 7. The calculated vertical and horizontal stress component values (a v and a H, respectively) at the toe are shown alongside the various models in Fig. 7. Joint C of Fig. 7 is further considered in Fig. 8 where the vertical stress (tensile stress) acting on the joint as a function of position along the joint are plotted. The resultant analyses point to the following conclusions: ncreases in the fillet angle F result in increases in both vertical and horizontal stress. 2 Additional solder in the side castellations (for castellated chip carriers) has little or no effect on pad-joint interface stresses. 3 Decreasing the pad length external to the package bottom will reduce the horizontal stress (a H ) assuming that oy (i.e., the fillet angle) does not increase. n addition, it was observed that the effect of stress relief at \ / \ / \ / \ / \ / \ /o 2(x) \s s"\ / \ / \ \ "' i Position along joint, ^m > ' 80 Fig. 8 Tensile stress acting on pad metallization as a function of position along the joint. [Reference Joint C, Fig. 7.J Dashed outline indicates joint profile. the bond interface due to increases in the amount of solder required to produce increased standoff height (height from board surface to package bottom) was a maximum at 200 /xm. At this height, the stress was found to be uniformly distributed throughout the heel portion of the joint. Below 200 /xm, the shear stress at the bond interfaces (joint-pad and packagejoint) begins to increase significantly while above this value no further significant changes in calculated stress were found to occur. Since higher joints increase the fillet angle and hence o> and lower joint heights increase bond interface stress (a H ), 200 jim probably represents a near optimum standoff height (provided sufficient solder volume is maintained). The examples above for chip carrier with side castellations by no means exhaust the geometrical possibilities for surface mount solder joints. style joints, for example, have negligible tensile strains [7, 8]; however, the interface shear stresses (and thus the von Mises stress) are quite large near the periphery of the bond interface due to the bulge that usually results in joint. This bulge varies according to the joint cross section and the amount of weight the molten solder must support during reflow. Stress concentration factors of 2 to 3 have been estimated for this effect simply by changing the radius of curvature for the bulge. For pillar-style geometry, it is possible to optimize the joint by choosing a large standoff (>200 /urn) and reducing the bulge to zero (i.e., vertical edges on the joint). n practice this is quite difficult to do with standard reflow techniques because the pillar wall shape is highly influenced by pad geometry, component weight, solder volume, and surface tension of molten solder. Special reflow or masking techniques [20] are needed to achieve a truly vertical pillar. Power Cycled Joints. n the case of thermal cycling, simple analytical models to estimate the shear strain range may be sufficient to develop a first order reliability prediction for surface mount assemblies. For the case of power cycling, the situation is entirely different due to the possibility of obtaining large temperature and thermal stress gradients across the surface mount packages and possibly the substrate. Estimates that call for package displacements (e.g., using ceramic chip carriers) to be given as the product of the coefficient of thermal expansion, the length from the center of the package to the corner and the substrate can result in large deviations from actual displacements. The major reasons for these discrepancies results from deviations from a thin, flatplate model typically used for surface mount packages especially chip carriers. Thermal analysis of properly designed cavity packages (without heat spreaders) will reveal that in most applications involving larger packages, thermal gradients across the assemblies can result in relatively low temperatures at the periphery of the frame which surrounds the cavity with Journal of Electronic Packaging JUNE 990, Vol. 2/39 Downloaded From: on 02/8/20 Terms of Use:

6 ~A~.~ Chip carrier Displacement direction dm9 l B ;(> Fig.9 Stress contours lor power-cycled solder joints [0 walts, power). Contours with numbers less than or equal to 2 indicate regions where the Von Mises stress is greater than the 0.2 percent yield stress [- MPa at 25'C). Sn3 solder with a joint at 30'C. A: Rectangular geometry, maximum Von Mises stress is 5.5 MPa. B: Extended illet geometry, maximum Von Mises stress is 3. MPa. respect to temperatures underneath the device. The cooler more massive frame acts to constrain the thermal expansion, thereby reducing the stress on the solder joints at the expense of increasing the strain within the ceramic itself. n some experiments with ceramic chip carriers at high power levels, the ceramic has actually cracked due to these high internal strains [7]. An extensive finite element model was developed for solder joints under power cycling. The results are shown in Fig. 9 for both a rectangular joint and a rectangular joint with an extended fillet. The maximum von Mises stress is listed for both cases along with the 0.2 percent yield strength limit. Plastic flow will occur once the von Mises stress exceeds the yield strength limit [2]. For a mean solder temperature of 30 C, the yield strength for Sn2 is given as 3.8 MPa. n Fig. 9, the stress contours numbered and 2 indicate the regions where plastic flow should occur for power cycling under the modeling conditions described. The stress contours for the extended fillet model show a significant amount of stress relief at the fillet portion of the solder joint during compression. n Figure 0, the effect of power cycle induced displacements are emphasized to show the warpage associated with each joint type (pillar, extended fillet, extended fillet with castellations). mplicit in this illustration and the related calculations was the assumption that the substrate is sufficiently stiff to resist any significant bending. n most actual surface mount applications, this bending behavior will be shared between the surface mount package and the substrate. Additional tensile strains introduced through substrate warpage can result in a shift from shear to tensile fatigue failure, thus increasing the rate at which cracks can propagate through the joint. A Maximum tensile stress W/,///~/,///0; Maximum tensile stress. Fig.0 Schematic representation 0 warpage experienced by chip carriers during power cycling [power-up conditionllor various style solder joints. A: pillar style joints; B: pillar styie joints with extended fillets; C; Castellation type solder lillets. Power lead Thermocouple :----: Substrate Thermocouple Maximum tensile stress CW~& Surface mount package W/////////////~///////////////l///////////////////////l//////////l//////ll/. Thermal grease A heat sink Fig. Schematic representation 0 surlace mount package test fix ture. Assembly used for power cycling experiments to investigate the in luence 0 joint geometry on latigue ile. As configured the test lixture can dissipate up to walts. Experimental Results Experimental Design. The major purpose of both the power cycling and temperature cycling experiments was to determine what factors (parameters) are significant in accelerating failures in surface mount solder joints. For example, various size chip carriers (-pin, -pin, and 8-pin mounted to ceramic circuit boards with gold-plated, copper metallized, thin film, solder pads were used in the initial power cycling studies. The solder joint temperatures were monitored by thermocouples embedded (soldered) into one of the solder joints for each package type. A special electronic test circuit was designed to permit the selection and control of the joint temperature. The test samples Uoints) in air, shown schematically in Fig., were power stored at 80 C (.5 watts continuous) for 000 hours followed by power cycling at 5 to 0 watts with a frequency of cycles/hour. Joint height for these samples ranged from 50 to 375!-tm. All samples endured 000 power cycles, a few samples failed at approximately 500 Fig. 2 Sn2 soider joint lor a pin leadless Chip carrier aller 000 hours 0 power storage at 80 C and 00 power cycles at 5W cycles due to overheating caused by increased thermal resistance at the die-package epoxy interface. The solder joints for the remaining intact samples show little effect from the power cycling even under scanning electron microscope (SEM) inspection. A typical joint from this series after 00 power cycles at 5 watts is shown in Fig. 2. Additional experiments were conducted to determine whether actual joint geometry had a significant effect on solder joint reliability (as indicated in the FEM analysis). Four basic solder joint styles or types were considered: high joints (0!-tm with small (Type A) or large (Type B) fillets, and low joints (50-75!-tm) with small (Type C) or large (Type D) fillets. Power cycling was carried out using a configuration similar to Fig., except the silver epoxy was replaced with a high temperature (2 C) thermally die attach medium conductive Vol. 2, JUNE 990 Transactions of the ASME Downloaded From: on 02/8/20 Terms of Use:

7 No heat sink Table Summary of torque shear test results for temperature cycled chip carriers on platinum-gold thick film metallization Solder joint nitial Torque strength Percentage height torque strength 200 cycles reduction in \im (N-m) (N-m) torque strength Fig. 3 The effect of the isothermal heat sink on the differential thermal expansion for power-cycled ceramic chip carriers on ceramic substrates. The heat sink versus non-heat sink cases also illustrate the strain ranges than can be expected from high frequency-large transient strain [Ay t] and low frequency-steady state [small] strain [A7SS]. Phi Vacuum clutch Force Hot air manifold QEEiffl Solder bumps '///////77//////////////y77/////// V777, ^ 77 Hot air Molten joint oint pulled to desired height Solidified shaped joint Fig. Controlled standoff height air reflow method. A. Package placed on substrate with vacuum clutch surrounded by manifold B. Heated air produces initial joint reflow. C. Molten joint is pulled to desired height. D. Airflow stopped, joint solidifies, and vacuum disengaged. epoxy and the resistor leads were soldered with gold tin (80 wt. % Au, 20 wt. % Sn) eutectic solder instead of the tin-lead used previously. These measures were necessary to allow for high power dissipations without any significant degradation of the resistor terminal leads or the thermal resistance path from the chip (die) to package. The chip carrier packages were soldered to ceramic substrates which, in turn, were attached to a large aluminum heat sink using a high thermal conductivity compound. The thermocouple on the resistor chip was used to detect thermal resistance changes from the substrate to the resistor surface. t has been shown previously that the occurrence of cracking just prior to failure brings about a significant increase in thermal resistance [7]. Changes in thermal resistance have been shown to provide a much more sensitive measure of solder joint cracking than are electrical resistance measurements [22]. The isothermal heat sink (28 C) served two primary functions in the experiment: ) the heat sink permitted the dissipation of powers up to watts (without any serious degradation to the resistors, epoxies, and solders used in the test assembly); 2) the heat sink reduced shear strain calculations to a relative steady state condition, as shown in Fig. 3. Thermal cycling experiments were conducted with similar package samples mounted to both ceramic and organic circuit (without heat sink). Cycling was carried out in a nitrogen purged convection oven following ML-STD 883C Test Method 00.7 between -55 C and + 50 C. Joint quality was determined by visual and SEM inspection, mechanical strength measurement, and continuous monitoring of electrical and/or thermal resistance changes. Joint Processing. n order to achieve the wide range of heights and joint shapes described in this study, it was typically necessary to pre-bump both the packages and the corresponding substrate pads. This pre-bumping or tinning ensured that sufficient solder was available for any practical joint configuration. The variable joint heights and geometries was achieved by two primary techniques: ) inverted reflow and 2) hot air reflow. The inverted reflow is a two step process. Packages are initially attached to the board by standard reflow methods (e.g., by hand, hot plate, furnace, vapor phase system) and then the package-board assemblies were inverted and reflowed a second time; thus, allowing gravity, surface tension, and the amount of solder to determine the ultimate stand-off height. Standoffs as large as 375 /*m were obtained by this method. The hot air reflow method is the most flexible and reliable scheme for controlled height reflow. The process is easily automated and can be adopted for use with many of the commerically available rework stations for surface mount applications. Figure illustrates the technique. The process involves a hot air solder reflow device similar to those used for surface mount package removal, with the addition of a mechanism on the vacuum chuck to allow the operator to adjust the height. Step, the vacuum pick-up fixture positions the chip carrier on the substrate. Step 2, heated air then flows through a manifold that directs the heat to the package-joint interface, causing the solder bumps to reflow. Step 3, while the solder is still molten, the vacuum fixture is raised (or lowered) to achieve the desired joint height (and shaped). Step, the hot Journal of Electronic Packaging JUNE 990, Vol. 2/ Downloaded From: on 02/8/20 Terms of Use:

8 Table 2 Power-cycied chip carrier test results and fatigue life summary Sample no. Carrier type (pins) No. of soldered leads Joint type Joint height (ym) Solder temperature ( C> Cycle frequency (cycles/hour) Estimated differential expansion (^m) FEM-estimated shear-strain (%) Observed fatigue life (cycles x 03) Predicted fatigue life** (cycles x 03) A B B B C C D D >.* >. >3.2 >. >. >5.3 > *> ndicates that tests terminated at this number of cycles with no observed signs of damage. * * Estimated from equation with F =. air is stopped, the vacuum is released, and the tool moves away from the in-place package with the desired standoff height. Test Data. Temperature cycling tests were performed on various surface mount package-substrate (board) combinations. A typical experiment consisted of temperature cycling the samples in a convection over between - 55 C and various high temperatures ranging from + 00 C to + 50 C. Each cycle had 30 minute dwells at the extremes with a 0 to 5 minute ramp in between the end points (i.e., ramp time depended upon the temperature difference between the extremes). The choice of upper-end temperature depended on the particular board and package materials of the sample set. Nominally + 00 C was used for organic boards (epoxy glass and polyimide) and +50 C for ceramic (A and AN). Samples were evaluated initially and at various points during the cycling program by visual inspection, electrical resistance measurement and mechanical strength testing. A representative experiment in the temperature cycling series used leadless ceramic chip carriers on a large ceramic multilayer circuit board (appoximately 3cm x 8cm). The carrier substrate bonding pads were platinum-gold thick film and the substrate was 9 percent alumina (A ). Chip carriers with up to 8-leads were considered and they were soldered with Sn2 alloy using a controlled height reflow technique which produced joints of 50 (jm, 25 pm and 250 li,m. The test was designed to investigate the effect of temperature cycling on joints with differing stand-off heights. The solder bond integrity prior to and after temperature cycling was evaluated using the techniques described above. Prior to the cycling, a representative set of various height samples was evaluated and the torque shear strength results for 20-lead carriers are shown in Table. The next column has strength data after 200 temperatures cycles. Prior to torque testing all samples were visually inspected for signs of cracking or adhesion loss at the joint-pad interface or the carrier-joint interface. After 200 cycles none of the specimens exhibited any cracking or pad lifting. The results (after 200 cycles) indicated that the 25 fim standoff height suffered no loss in shear strength from the cycling while both the 50 /tm specimens suffered roughly a 5 percent loss in shear strength. should be noted, however, that the small standoff solder joints had a larger shear strength both initially and after temperature cycling. Further cycling tended to reduce the torque strength even further, but a change in the mode of torque failure clouded the additional strength reductions (see isothermal aging below). nitially, the primary location for the fractures from the torque test occurred at either the solder joint-pad interface or the conductor pad-ceramic layer interface, with a small minority occuring at the chip carrier-joint interface. Examination of the temperature cycled bonding pads after torque testing showed that separation occurred exclusively at the conductor-ceramic interface. This indicates that some reduction in the adhesion of the platinum-gold thick film bonding pad to the underlying ceramic had occurred as a result of the temperature cycling. As mentioned in the experimental design section four different solder joint geometries were studied for various surface mount packages and in particular for both - and -lead leadless ceramic chip-carriers under power cycling conditions. The results for the four joint geometries as shown in Fig. 5 are summarized in Table 2. All of the samples tested showed no thermal resistance changes prior to completion of 3,000 power cycles at a level of 0 watts. The first failure occurred at approximately 3200 cycles in a -lead carrier when an increase in the temperature differential across the solder joint was observed. Within a 20 cycle time period the temperature differential increased approximately 20 C. Following this failure the power was increased to watts causing one high standoff, large fillet sample (Type B) to crack. All of the remaining specimens survived at least an additional 200 power cycles (at watts) at which time the test was terminated except on one low standoff, large fillet sample (Type D) which endured an additional 200 cycles without affect. As visible in Fig. 5 solder joint appearances after power cycling was 2/Vol. 2, JUNE 990 Transactions of the ASME Downloaded From: on 02/8/20 Terms of Use:

9 Fig.5 Power cycled solder joints. A. Type A joint- pin carrier after 0 power cycles B. Type B joint- pin carrier showing fatigue failure after 3200 power cycles C. Type C jolnt- pin carrier after 0 power cycles D. Type 0 jolnt- pin carrier after 500 power cycles Fig. Micro Yold formation nside the the solder joint castellatlon region due to the large stresses and temperatures that occur there. Compare location of Yold with high stress contours in Fig.. generally found to be significantly better for the low standoff, large fillet joint (Type D). Joints with large standoffs and large fillets were also generally good. Those joints which most closely approximated the idealized high standoff, pillar style geometry displayed the most severe cases of fatigue wear. n addition, with these joints, fatigue cracking did not appear to be localized at the corner joints as was predicted by the FEM stress analysis. Some of the poorer samples exhibited significant micropore formation with large voids in the castellation region (Figure ). Significant intermetallic formulation was also noted at the bond interfaces due mainly to the presence of gold in these regions. Since solder temperatures did not exceed C throughout the entire test «000 hours), stress-assisted diffusion appears to be the dominant factor for any additional intermetallic growth. Also, at strain rates typical in powercycling applications, cyclic creep is probably the dominate contributor to void formation and grain recrystallization. The important conclusion from these tests indicate that Journal of Electronic Packaging small standoff solder joints on ceramic substrate materials (see Fig. 7) would provide a reliable interconnection connection for use in a power cycled environment. This knowledge allowed the fabrication of solder joints possessing a relatively small fillet angle, which in turn requires that the solder joint standoff height be relatively low. Joints with this geometry have been successfully fabricated on large multilevel thick film ceramic boards used in a space borne radar signal processor (23). Additional studies were undertaken to observe the effect of frequency, temperature and FEM-estimated strain range on the number of cycles to failure. n a typical experiment, pillarstyle solder joints were fabricated using pre-bump - and -lead ceramic chip carriers and special hot air reflow technique. The standoff height for specimen solder joints was approximately 25 /Lm. Two temperature levels, C and 5 C, and two frequency levels cycles/hour and 2 cycles/hour were used. Strain levels varied somewhat between samples, and subsequent strain estimates were based on FEM-estimated differential thermal expansion and independent temperature measurements for each of the test specimens. The results are summarized in Table 2. A primary observation from this experiment is the effect of power cycling frequency on the number of cycles to failure as shown in Fig. 8. Predictably the effect of temperature at the higher cycle frequency (2 cycles/hour) was less pronounced than that for the lower frequency ( cycles/hour). This would be due to the increased plastic strain resulting from creep and other time dependent relaxation phenomena. These results can be correlated with those expected for actual surface mount packages on nonisothermal substrates at reduced power levels by comparing Fig. 3 with Fig. 9. For example, Fig. 3 illustrates the solder strain profile during heat-up, steady-state operation, and subsequent cool-down of a ceramic chip carrier when mounted to an isothermal heat sink. n Fig. 9 the strain profile is illustrated for a more conventional situation in which the shear strain range is composed of a high, transient strain of limited time duration and a low, steady-state strain. The high frequency data such as that shown in Figure 8 should correlate with the corresponding heat-up and cool-down for real situations JUNE 990, Vol. 2/3 Downloaded From: on 02/8/20 Terms of Use:

10 ---~ 2 Nt T Ntss + Nt, Flg.9 Predicting total number of cycles to failure from high frequen cy and low frequency isothermal power cycllng data. See Fig. 3 for definition of 0y and 'ss' Fig. 7 Cross section of Type 0 (low helght large filletl Sn3 solder joint after 00 power cycles. Upper photomicrograph illustrates basic geometry and fillet ntegrity. Lower photomicrograph s close up of metalllzalions and solder at the critical corner region. Ol Cl c 0.3 r: c.~ ll- ~ '# 0.2 ro Ol <- "fii<l E 0. ~ r , o 0 20 Number of cycles to failure Nt( x 0 3 Fig. 8 Number of cycles to failure versus estimated shear strain range for power cycled leadless chip carrier solder joints. cycles/hour: T= C;.T=S C. 2 cycles/hour: 0 T= C;.T=S C. involving device dissipations greater than watt. The data provided at low frequency establish a lower bound for the number of useful power cycles involving more than power cycles/hour. Assuming that both the transient strain range (Nt and the steady-state strain range (N ss ) are known then the total number of cycles to failure (N f ) can be estimated from the relation -=-+- (2) N f N ss Nt where the N ss (steady-state cycles to failure) and the Nt (transient cycles to failure) can be estimated experimentally from Fig. 20 SEM photomicrograph of a 5n3 solder ball test sample on a plallnum gold thick film metallizallon pad (90!'m x 90!,ml. Fig. 8. For power cycling frequencies less than cycles/hour further testing would be necessary [2]. Solder Ball Shear Test The solder ball shear test has been developed [25] to characterize solder bond parameters, investigate metallization solderability, and evaluate the effects of temperature cycling, thermal shock and isothermal aging on the formed jointmetallization system. The ball is formed by placing a premeasured amount of solder on a special test substrate containing pads of predetermined shape and size as shown in Fig. 20. Following reflow (by the same technique used for actual surface mount circuit assembly), the substrate-ball combinations are experimentally treated (i.e., thermal cycling, shock testing or high temperature aging). After the treatment, the solder balls were sheared from the pad metallization using a conventional ball shear testing device [25]. To determine whether solder balls actually simulate soldered interconnections, a FEM thermal stress analysis was performed [7]. Calculated stress levels (at the ball-bonding pad interface) were determined to be similar to those calculated for actual surface mount joint-pad geometries. Location and intensity of the various stress contours will depend on the ball height, pad geometry, a curvature of the solder ball. For example, solder ball shear test results for isothermally aged SN3 solder balls on platinum-gold thick film bonding pads are shown in Fig. 2. Similar results were obtained for both Sn0 and Sn2. As indicated, the rate of change in the shear force required to remove the solder balls was initially large and then dropped rapidly towards zero as the aging time increased. / Vol. 2, JUNE 990 Transactions of the ASME Downloaded From: on 02/8/20 Terms of Use:

11 & \ > k^_ Q_ O a ' u a l l a 50 C 0 25 C a 0 C 90 C a yr Time (hr) Fig. 2 Shear strength of isothermally aged Sn3 solder balls as illustrated in Fig. 20. t is believed that the rejection of lead at the interface and its subsequent buildup in the gold-tin intermetallic slowed the growth rate of the weak intermetallics, hence, the stabilization of the solder ball shear strength with age. Similar effects were noted in isothermally aged tin-lead alloy cladding on copper leads soldered to thick film substrates [2]. Another interesting feature was the decline in steady state shear strength (long time-flattened portion of curve) with increased aging temperature. We expected that the equilibrium condition would approach the same ultimate shear strength value for each of the temperature groups, differing only in the time it took to reach the condition. However, it appears that the diffusion barrier formation is relatively insensitive to temperature and the percentage reduction in strength depends solely on the aging temperature and not the temperature-time product. This suggests that excessive temperature storage or temperature cycling testing of solder joints could significantly reduce the fracture strength of the soldered interconnections. Discussion Power Cycling. Both the experimental and FEM thermal stress analysis indicate that relatively large device power dissipation levels are required to produce sufficient strain in surface mount package solder joints to induce failure when mounted to stiff (non-bending) high thermal conductivity and CTE compatible substrates. The reason for the ceramic chip carrier's good power cycling fatigue properties is the rigid cooler side walls which constrain the chip carrier from expanding, thus concentrating most of the strain in the ceramic package rather than in the solder joints. The large thermal gradient which exists between the side walls and the die cavity also limits the amount of power which can be dissipated by the active device. n thermal analyses using the FEM chip carrier model shown in Fig. 2, a thermal resistance of C/W was calculated for a -ead chip carrier assuming heat conduction through the leads only. This thermal resistance is larger for higher lead count chip carriers despite the increased number of leads due to increased package width and the reduced amounts of power which can be dissipated (due to an even larger thermal gradient)-thus reducing power cycling effects even further for larger packages. Solder joint geometry plays a significant role in power cycling fatigue resistance. ncreased fatigue life can be experimentally obtained by fabricating solder joints with large fillets and low standoff heights (Type D joints). FEM studies indicate that large fillet geometries reduce carrier-substrate warpage and thus help limit harmful tensile strains. Large fillets significantly reduce harmful stress concentrations while rf increasing net joint cross-sectional area. Both these factors tend to improve joint fracture toughness. The dramatic dependence of power-cycled joint fatique life on both temperature and frequency is illustrated in this study. Frequency dependence can be minimized by eliminating tensile strain. Such tensile strain reductions are probably the most effective means of reducing frequency and temperature effects in low cycle solder fatigue. Studies on tin-lead solder alloys indicate that harmful stress relaxation can occur much more rapidly during tensile strain holds than during periods of pure compressive- strain. n addition, oxygen embrittlement of grain boundaries during tensile dwell periods can prevent partial rewelding during compressive strain cycles, thus contributing significantly to the rapidity of crack propagation. Temperature Cycling. Torque test results on temperature cycled samples indicated high standoffs (25-50 /im) produced the greatest resistance to joint strength reduction due to thermal cycling. Both low (50 /xm) and excessively high standoffs (>250 itm) produced reduced mechanical strength after a few hundred temperature cycles. Microscopic examinations typically revealed no joint fatigue cracking; however, evidence of added intermetallic formation at joint-pad interfaces was routinely observed. n our thick film examples the fillet angles were slighly less than 5 and the bonding pads were partially covered with a dielectric overlay that was used as a solder dam. Both techniques are useful in reducing pad delamination. The resultant 25 /xm high joint produced no deterioration in interface shear strength while providing sufficiently high standoff for flux removal. FEM analysis also suggested that pillar style solder joints with a truncated spherical geometry tend to focus strains at the interfaces near the bond edges rather than in the bond itself. For pillar-shaped rectangular joints these stress concentration factors can be as high as 3. Analysis of standard chip carrier solder joints suggest longer pads are preferable to shorter ones and that slightly elevated standoff's (nominally 25 /xm) are preferred. The longer pad allows a joint to have a low fillet angle while maintaining sufficient height for flux removal. As indicated in the power cycling test, increasing the fillet volume will increase the joints resistance to power cycling fatigue. For cases where solder joints are attached to flexible or low-modulus substrate materials, tapered solder joints have been shown to improve overal fatigue resistance [27]. Many flexible substrates have CTE's which are incompatible with large leadless ceramic packages. n these cases, tapering will provide only a small increase in fracture toughness. Additional increases can be achieved by increasing joint cross-sectional area. n addition, elimination of tensile strains (by heat sink lamination, etc.) produced by substrate warpage will further extend the fatigue life. Solder Ball Shear Test. The solder ball shear test has proven to be a simple, effective means to gain solder-substrate materials interaction data including; solderability of conductors; conductor adhesion; bond integrity under thermal aging, thermal shock, etc.; and intermetallic growth studies. Summary The use of finite-element analysis techniques in fatigueresistant solder joint design and in the estimation of shear strains in power-cycled surface mount packages has been discussed. The method has been shown to qualitatively predict thermally induced stress concentrations for various geometrical solder joint configurations. Typically, however, insufficient data on the physical properties of the various material systems of interest for surface mount applications make accurate determination of fatigue and other processes Journal of Electronic Packaging JUNE 990, Vol. 2/5 Downloaded From: on 02/8/20 Terms of Use: