3D Stacking of Chips with Electrical and Microfluidic I/O Interconnects

Transcription

1 3D Stacking of Chips with Electrical and Microfluidic I/O Interconnects Calvin R. King, Jr., Deepak Sekar, Muhannad S. Bakir, Bing Dang #, Joel Pikarsky, and James D. Meindl Georgia Institute of Technology, # IBM T.J. Watson Research Center calvin.king@gatech.edu Abstract Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such technologies are not suitable for highperformance chips due to ineffective power delivery and heat removal. This is important because high performance chips are projected to dissipate more than 100W/cm 2 and require more than 100A of supply current. Consequently, when such chips are stacked, the challenges in power delivery and cooling become greatly exacerbated. Thus, revolutionary interconnection and packaging technologies will be needed to address these limits [1]. This paper reports, for the first time, the configuration, fabrication, and experimental results of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for high-performance chips. The key behind this 3D platform is the ability to process integrate, at the wafer-level, electrical and microfluidic interconnection networks on the wafer containing the electrical circuitry and assemble such chips using conventional flip-chip technology. Introduction Three-dimensional (3D) die stacking increases transistor density and chip functionality by vertically integrating two or more dice. Furthermore, 3D integration also improves interconnect speed by decreasing interconnect wire length, enables smaller system form factor, and reduces power dissipation and crosstalk. As transistor technology continues to scale and integration density increases, one of the main performance limiters of an IC chip will be heat removal. Because the reliability and performance of transistors and interconnects depend on operating temperature, the need to cool electronics and diminish hot spots has never been greater. With the continued scaling of device features and increased power density, chip cooling has become increasingly more difficult and costly. The International Technology Roadmap for Semiconductors (ITRS) projects that power dissipation will reach 151 W and 198 W for cost performance and highperformance applications, respectively, by 2018 at the 18 nm technology node [2]. Consequently, it is not likely that conventional heat removal techniques will meet the power density, heat flux, and thermal resistance needs of future high performance microprocessors. Power (W) Current Drain (A) Technology (nm) Figure 1. ITRS projections for power dissipation, supply voltage, and current drain as a function of technology [2]. Liquid cooling using microchannels is promising to meet the thermal management requirements of future highperformance microprocessors due to its high heat transfer coefficient [3]. Although a number of researchers have explored the advantages of using liquid cooling to mitigate future thermal management problems [4-8], there are many unknowns for its implementation, especially for 3D integrated systems. Some of these unknowns include fabrication of an on-chip microfluidic heat sink and integration of electrical through-silicon vias (TSVs), where to place fluidic I/O interconnects for 3D chips, how to supply fluid to and extract fluid from microchannels embedded in a 3D stack, and how to assemble 3D ICs with microfluidic functionality. This paper outlines process integration and assembly technologies for a proposed microfluidic liquid cooling configuration to cool three-dimensional ICs. The paper is organized as follows: Section II of this paper presents a novel microfluidic cooling scheme for 3D ICs and outlines the fabrication process of the system components. In Section III, chip stacking, chip to substrate assembly, and fluidic sealing are discussed. Section IV outlines the testing of the system. Section V presents concluding remarks Supply Voltage (V) /08/$ IEEE Electronic Components and Technology Conference

2 Section II: Novel Microfluidic Network Configuration for 3D ICs A. 3D Microfluidic Network Cooling Scheme We investigate, for the first time, microchannel heat sink integration into each stratum of a 3D stack to enable cooling of >100W/cm 2 of each high power density chip. Figure 2 shows a proposed microfluidic network cooling scheme that has the potential to be used for cooling threedimensional ICs. Each silicon die of the 3D stack contains the following features: 1) a monolithically integrated microchannel heat sink, 2) through-silicon electrical (copper) vias (TSEV) and through-silicon fluidic (hollow) vias (TSFV), the latter used for fluidic routing in the 3D stack, and 3) solder bumps (electrical I/Os) and microscale polymer pipes (fluidic I/Os) on the side of the chip opposite to the microchannel heat sink [9]. Microscale fluidic interconnection between strata is enabled by through-wafer fluidic vias and polymer pipe I/O interconnects. The chips are designed such that when they are stacked, each chip makes electrical and fluidic interconnection to the dice above and below. Consequently, power delivery and signaling can be supported by the electrical interconnects (solder bumps and copper TSVs), and heat removal for each stratum can be supported by the fluidic I/Os and microchannel heat sinks. Figure 2. Schematic of proposed chip-scale microchannel heat sink for 3D integrated circuits. The following sections report the details of the 3D configuration and fabrication processes used to enable the wafer-scale batch fabrication of all interconnection modes described above. B. Integrated Microchannel Heat Sink and Electrical TSVs B. Dang et al [9-11] recently explored novel fabrication approaches for developing a CMOS-compatible, on-chip microchannel heat sink and thermofludic I/O interconnection and packaging methods needed to implement chip-level microfluidic cooling. For 3D technology, electrical TSVs are needed for power delivery to chips in the 3D and to enable communication between chips in the 3D stack. The following schematic (Figure 3) outlines the process flow for integrating microchannels with electrical TSVs. Figure 3. Schematic of wafer-level integration of microchannels, through-silicon fluidic vias, and electrical through-silicon vias to enable 3D system integration using liquid cooling. (a) Deposit oxide on frontside of wafer. (b) Pattern and etch through-silicon vias. (c) Cu seed layer evaporation and electroplating. (d) Fluidic TSVs and microchannel trenches are etched into the back side of the wafer (e) Spin coat and polish Unity sacrificial polymer. (f) Spin coat and pattern Avatrel polymer sockets. (g) Simultaneous curing of Avatrel polymer and thermally decomposition of sacrificial polymer. The process begins by depositing a 3µm thick layer of silicon-oxide on the front side of the wafer as a through-silicon via etch-stop layer (Figure 3a). TSVs are patterned and anisotropically etched into the back side of the silicon wafer in an inductive coupled plasma (ICP) etching tool (Figure 3b). After thermally growing a 1µm layer of oxide on the TSV sidewalls, a Ti/Cu seed layer is evaporated on the front-side of the wafer. After which, copper is electroplated in the TSVs (Figure 3c). Next, using two lithography steps, fluidic TSVs and microchannel trenches are etched into the back side of the wafer (Figure 3d). Subsequently, Unity sacrificial polymer (Promerus, LLC) is spin-coated on the wafer, filling the fluidic TSVs and microchannels. Afterwards, mechanical polishing is performed to planarize the surface (Figure 3e). Next, 15 µm of Avatrel 2090P polymer (Promerus, LLC) is spin-coated onto the wafer and polymer sockets are patterned (Figure 3f). Finally, the Avatrel polymer is cured, and the Unity sacrificial polymer is thermally decomposed simultaneously, making the process CMOS-compatible (Figure 3g). Figure 4 shows a cross-sectional optical image of a sample after the previously described processing steps are completed. The non-optimized microchannels are 200µm tall and 100µm wide (Figure 5), and the copper TSVs have a 50µm diameter. Platinum resistors are fabricated on the front-side of the wafer to facilitate heating and temperature sensing, as shown in Figure Electronic Components and Technology Conference

3 Figure 4. Cross-sectional optical image and schematic of integrated microchannel heat sink and electrical through-silicon vias. are stacked and a coolant is circulated from the top chip, through the 3D stack, and out of the bottom of the substrate. Figure 7 shows a schematic of the fabrication process flow for a silicon die with integrated polymer sockets, through-wafer fluidic interconnects, thermofluidic I/O interconnects, and electrical I/O interconnects. The process begins by sputtering a 300/10000/300Å titanium/ copper/titanium (Ti/Cu/Ti) metal layer, where Ti serves as an adhesion promoter between Cu and silicon (Figure 7a). The metal is patterned using a wet etch process (Figure 7b). Next, 1µm of oxide is deposited on the back side of the wafer as a polymer adhesion layer (Figure 7c), and 3µm of oxide is deposited on the front side as a throughsilicon via etch-stop layer (Figure 7d). Next, 15µm of Avatrel 2090P polymer is spin coated onto the wafer (Figure 7e). Afterwards, polymer sockets are patterned on top of the metal (Figure 7f, Figure 8). The first layer of Ti is removed using a wet-etching process. Through-wafer fluidic vias are patterned and anisotropically etched into the back side of the silicon wafer in an ICP etching tool (Figure 7g, Figure 8); the etching stops at the etch-stop layer on the front side of the wafer. Next, a 12µm layer of Avatrel polymer is spin coated and patterned on the front side of the wafer and used as a passivation layer (Figure 7h). After sputtering a 300/2000/300Å Ti/Cu/Ti seed layer and electroplating a Figure 5. SEM image of integrated microchannel heat sink and fluidic through-silicon vias. Figure 6. SEM image of platinum heaters fabricated on a chip for heating and temperature sensing. C. Fabrication of Chips with Polymer Sockets, Electrical I/O Interconnects, Fluidic Through Wafer Vias, and Fluidic Input/Output Interconnects To address the unknowns of where to place fluidic I/O interconnects for 3D chips, how to supply fluid to each die in the 3D stack, how to assemble 3D ICs with microfluidic functionality and to demonstrate the capability of supplying fluid to each die in the 3D stack, a prototype 3D stack is demonstrated in which chips with electrical and fluidic I/Os Figure 7. Schematic of wafer-level integration of polymer sockets, electrical I/O and fluidic I/O interconnects for a 3D flip-chip package. (a) Sputter metal on back side of wafer. (b) Pattern metal. (c) Back side oxide deposition and patterning. (d) Front side oxide deposition. (e) Spin polymer. (f) Pattern polymer sockets. (g) Etch through-silicon vias. (h) Spin and pattern polymer passivation layer. (i) Sputter Ti/Cu seed layer and electroplate Ni UBM and solder bumps. (j) Fabricate polymer micropipes Electronic Components and Technology Conference

4 Figure 8. SEM image of 15µm tall, 270µm and 60µm diameter polymer sockets Figure 9. SEM image of 100µm diameter through-wafer fluidic interconnects. Figure 10. SEM image of 50µm tall solder bumps used as electrical I/O interconnects. Figure 11. SEM image of 60µm tall polymer pipes used as I/O fluidic interconnects. 2µm nickel under-bump metallurgy layer, 50 µm C4 solder bumps are electroplated for area-array electrical interconnects (Figure 7i, Figure 10). Afterwards, a 60 µm layer of Avatrel polymer is spin coated onto the front side of the wafer and used to pattern polymer pipes, which serve as thermofluidic I/O interconnects (Figure 7j, Figure 11). Finally, the oxide layer covering the through-wafer fluidic vias on the front side of the wafer is removed using a wet etch process to allow fluidic circulation. sockets on the back side of the dice, as shown in Figure 12. The silicon substrate contains copper pads, polymer sockets, and integrated fluidic TSVs. Section III: Assembly of 3D Prototype Chips A. Flip-chip Assembly Process A challenge in such a 3D configuration is the flip-chip bonding process, especially since one must be able to provide fluidic sealing to prevent leakage. This section discusses the flip-chip die-to-die bonding processes that enable such integration of the components of the prototype 3D stack discussed in Section II.C. Fabrication and assembly of the prototype 3D chip stack allow the issues of 1) where to place fluidic I/O interconnects for 3D chips, 2) how to supply fluid to each die in the 3D stack, and 3) how to assemble 3D ICs with microfluidic functionality to be investigated. The 3D prototype contains silicon dice with integrated through-wafer fluidic interconnects, thermofluidic polymer pipe I/O interconnects and high density solder bump electrical I/O interconnects on the front side of the dice, and polymer Figure 12. Characterization and assembly of 3D Prototype. Using this configuration, dice are aligned, stacked, and assembled on a silicon substrate using a flip-chip bonder with an alignment accuracy of <2µm. The process used for assembly involves preheating the die and the substrate to temperatures of 180 C and 140 C, respectively, bringing the Electronic Components and Technology Conference

5 two into contact with a compression force of 200g, and elevating the temperature of the chip and the substrate to 230 C and 150 C, respectively. The bonding process parameters are listed in Table 1. The fluidic I/Os and electrical I/Os are assembled simultaneously. The 250µm diameter polymer pipes are aligned to the 270µm diameter polymer sockets on the substrate, and the 50µm diameter solder bumps are aligned to the copper traces and 60µm polymer sockets on the substrate (Figure 12). In addition to serving as electrical and fluidic I/Os, the solder bumps and polymer pipes provide mechanical interconnection between the bottom die and the substrate and between the dice in the 3D stack. Because copper traces and polymer sockets are fabricated onto the back side of the first die, the second die is assembled onto the back side of the first die using the same bonding recipe (temperature and force). The self-alignment property of solder increases the alignment accuracy of the die to the substrate. Patterned silicon dioxide on the substrate contains the solder during reflow. The process used for assembly of the 3D prototype is thus compatible with conventional flip-chip bonding. Figure 13 shows an SEM cross-sectional image of a 3D stack of two microfluidic chips. Figures 14a and 14b show infrared microscope images of through-silicon fluidic via alignment of the two chips. Figure 15 shows a 3D stack of two chips assembled to a substrate and a 3D stack of four chips assembled to a substrate. Assembly Parameters and Sequence of Steps Value Pre-heating Temperature of Substrate 140 C Pre-heating Temperature of Die C Compression Force 200g Bonding Temperature of Substrate 150 C Bonding Temperature of Die C Pre-heating Temperature of Substrate and Die C Pre-heating Temperature of Die C Compression Force 200g Bonding Temperature of Substrate and Die C Bonding Temperature of Die C Table 1. Bonding Process Parameters Figure 13. Cross-sectional SEM image of 3D microfludic chip-to-chip bonding. Figure 14a. Top-view IR-microscope image of 3D stack. Figure 14b. Tilted IR-microscope image of 3D stack Electronic Components and Technology Conference

6 Figure 15: SEM images of 2-chip and 4-chip 3D stacks. B. Fluidic Sealing After assembly, to seal the 80 fluidic I/Os on the front side of each chip, an epoxy-based underfill is applied at the edges of chip (Figure 16). The underfill provides a stronger mechanical connection between each interface. For this application, most importantly, underfill is used for the purpose of sealing the fluidic interconnect interfaces between the die and the substrate and between the dice in the 3D stack. Figure 17. Schematic of 3D chip assembly and encapsulation. Figure 16. 3D assembly and encapsulation. Section IV: Testing To test the reliability of the fluidic sealant, a mechanical pump and fluid inlet pipe can be attached to the back side of the top-most die in the 3D stack and used to pass fluid through the chip stack (Figure 17-18). This fluid delivery method is an alternative to the fluid delivery method described in Figure 2. Fluid can be delivered from the top chip, through the 3D stack, and out of the bottom of the substrate with no leakage at the chip-to-chip and chip-to-substrate interfaces. Figure 18. Optical image of 3D chip stack after tube attachment Electronic Components and Technology Conference

7 Section V: Conclusions Heat removal technologies are among the most critical needs for 3D integration of high-performance microprocessors. Liquid cooling represents a promising solution for meeting future thermal management requirements of high-performance 3D chip stacks. In this work, we outline the configuration, fabrication, and experimental results of a 3D integration platform that can support the power delivery, signaling, and heat removal requirements for highperformance chips. The core technologies behind this 3D platform, the ability to process integrate, at the wafer-level, electrical and microfluidic interconnects and assemble microfluidic chips using conventional flip-chip technology are demonstrated. Acknowledgements This work has been carried out as part of the Interconnect Focus Center Research Program at the Georgia Institute of Technology, and is supported in part by the Microelectronics Advanced Research Corporation (MARCO), its participating companies, and DARPA under contract 2003-IT-674, and in part is based upon work supported by the National Science Foundation under Grant No References [1] M. S. Bakir, B. Dang, and J. D. Meindl, Revolutionary nanosilicon ancillary technologies for ultimateperformance gigascale systems, IEEE Custom Integrated Circuits Conference, [2] International Technology Roadmap for Semiconductors, 2006 Edition, Semiconductor Industry Association, 4300 Stevens Suite Boulevard, Suite 271, San Jose, CA [3] S. P. Gurrum, S. K. Suman, Y. K. Joshi, and A.G. Fedorov, "Thermal issues in next-generation integrated circuits," IEEE Transactions on Device and Materials Reliability, vol. 4, pp , [4] J. Koo, S. Im, and L. Jiang, Integrated microchannel cooling for three-dimensional electronic circuit architectures, Journal of Heat Transfer, Volume 127, January [5] D. B. Tuckerman and R. F. W. Pease, High performance heat sinking for VLSI, IEEE Electron Device Letter, vol. EDL-2, pp , [6] R. Viswanath, V. Wakharkar, A. Watwe, V. Lebonheur, Thermal performance challenges from silicon to systems, Intel Technology Journal, vol. 8 no. 4, pp.1-16, [7] Z. J. Zhou, L. R. Hoover, and A. L. Philips, An integrated thermal architecture for thermal management of high power electronics, in Proc. of the International Conference on THERMES, pp , [8] T. Thompson. Exploring options for keeping the heat out. Chipscale Review: Thermal Management, August/September [9] B. Dang, M. Bakir, J. Meindl, Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink, IEEE Electron Device Letters, vol. 27, no. 2, pp , [10] B. Dang, P. J. Joseph, M. S. Bakir, T. Spencer, P. Kohl, J. Meindl, Wafer-level microfluidic cooling interconnects for GSI, Proc. IEEE International Interconnect Technology Conference (IITC), pp , 2005 [11] B. Dang Integrated Input/Output Interconnection and Packaging for GSI, Ph.D. Dissertation Georgia Institute of Technology, Electronic Components and Technology Conference