THE SCALING of transistors to smaller dimension has

Transcription

1 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 33, NO. 3, SEPTEMBER Thermal-Mechanical Stress Modeling of Copper Chip-to-Substrate Pillar Connections Ping Nicole An and Paul A. Kohl Abstract The thermal stress induced by the coefficient of thermal expansion mismatch between a silicon integrated circuit and an organic substrate is an important reliability issue for chip-to-substrate connections. Copper pillar chip-to-substrate connections, including solder-capped and all-copper pillars, are potential replacements for solder balls with underfill in flipchip applications. The thermal stresses associated with copper pillar connections are a function of the shape, dimensions, and materials for copper pillars and their associated chip and substrate terminations. In this paper, the design of the copper pillar, chip-to-substrate connections has been studied using finite element analysis. A 3-D, half generalized plane deformation slice model is used to study the static thermal stress at elevated temperature. The design parameters include the shape and material of the pads at the terminus of the copper pillars and the nature of supporting collar around the pillar. The modeling results show that a chip-pad helps to lower the maximum thermal stress within the silicon die. Moreover, a supporting collar around the copper pillars serves to decrease the maximum thermal stress on the silicon die. A high-modulus polymer collar around the copper pillar serves to lower the stress at the pillar-to-chip-pad junction and increase the stress within the center of the pillar. The maximum thermal stress within the die was lowered from 160 MPa to 100 MPa by increasing the elastic modulus of the collar from 1.2 GPa to 11.8 GPa. Index Terms Flip-chip, modeling, thermal-mechanical analysis. I. Introduction THE SCALING of transistors to smaller dimension has increased the density of input/output (I/O) connections on integrated circuits. According to the International Technology Roadmap for Semiconductors [1], the maximum package pin count for a high performance FPGA in 2011 is 5094 with a chip area of 804 mm 2, which gives a maximum I/O pitch of 397 µm. By 2020, the maximum I/O pitch is reduced to 308 µm. In addition, the off-chip bandwidth is increasing for signal I/O. Thus, I/O with a finer pitch and superior electrical properties (e.g. resistance, capacitance, and induc- Manuscript received January 14, 2010; revised April 14, 2010; accepted May 4, Date of current version October 1, This work was supported by the Global Research Collaboration of the Semiconductor Research Corporation, under Project # Recommended for publication by Associate Editor A. Chandra upon evaluation of reviewers comments. P. N. An is with the Institute of Microelectronics, Peking University, Beijing , China ( anping@pku.edu.cn). P. A. Kohl is with the School of Chemical and Biomolecular Engineering, Georgia Institute of Technology, Atlanta, GA USA ( kohl@gatech.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCAPT /$26.00 c 2010 IEEE tance) are needed. In addition, reliability improvements, especially for electromigration and thermalmigration, are desired [2], [3]. Area array, flip-chip solder connections currently offer the highest performance chip-to-substrate connections. However, the solder ball pitch is limited by the small off-set between chip and substrate because solder balls have a one-to-one (height-to-width) aspect ratio [4]. The electrical performance of solder is less than optimal because of the lower conductivity of solder, compared to copper, and the need for underfill to improve the solder reliability [3], [5], [6]. The epoxy-based underfill significantly raises the permittivity and loss of the region between the solder I/O. In addition, the brittle coppertin intermetallics formed at the joint between solder and the chip-pad is a reliability concern. Recently, copper pillar based chip-to-substrate connections, including copper pillars with a thin solder-cap and all-copper pillars, have been shown to have an improved aspect ratio compared to solder flip-chip interconnections [1], [7] [11]. The all-copper I/O can be fabricated into a variety of aspectratio shapes [9], [10]. Direct bonding of two copper pillars has been achieved by electroless copper plating. It was found that the electroless plating process can form pillar-to-pillar bonds at conditions much less extreme than the high temperature and pressure copper thermo-compression wafer bonding or surface activated copper bonding [12], [13]. The electroless process has been shown to be able to compensate for z-axis, non-planarity, and in-plane misalignment between the chip and substrate [9], [14], [15]. Previously, it was found that stress in the copper pillars and within the chip resulting from the mismatch in coefficient of thermal expansion (CTE) between the chip and substrate decreased with pillar aspect ratio (higher aspect ratio structures resulting in lower stress) [10]. The flexibility and compliance of the pillars can be increased by making them taller with higher aspect ratio (height-to-diameter). However, high aspect ratio copper pillars (e.g. structures with aspect ratio greater than 10) can be challenging to fabricate. In addition, high aspect ratio pillars result in higher inductance and capacitance. Thus, it is desirable to lower the thermally induced stress by optimizing the shape and size of the pillars. It is also desirable to have bond pads on the chip and substrate at the base of the pillars and have supporting polymer collars around the pillars. Even with a high aspect ratio pillar design, the stress in the silicon die at the base of the pillar could be improved by achieving lower values. The stress in the silicon affects the

2 622 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 33, NO. 3, SEPTEMBER 2010 reliability of the relatively fragile, low-k, on-chip, interlayer dielectric material. In this paper, the thermo-mechanical properties of the package are characterized by evaluating the von Mises stress distribution within both the pillars and the silicon die as a function of position on the chip and pillar structure. The focus of this paper is on the magnitude of the stress and stress distribution at the pillar-to-silicon interface since the on-chip, interlayer dielectrics are vulnerable to fracture. Copper pillars are used in the modeling. Several approaches to lowering the stress in the silicon die are explored. II. Finite Element Model Three kinds of 3-D models are widely used to investigate the properties and reliability of high-density, I/O connections: quarter model, octant model, and general plane deformation (GPD) model [10], [16] [19]. The 3-D models often require an enormous number of nodes to achieve convergence or mesh-independent results. The GPD slice model relies on symmetry planes within the chip and substrate. It also requires the minimum number of nodes to evaluate the mechanical deformation of the components. The GPD model is particularly valuable for packages with a high number of I/O and high stress gradients [10]. In this paper, a half GPD model, which uses a symmetry plane along the diagonal line of the chip outward from the center to the corner, is used to investigate the thermal-mechanical stress in the silicon die. A schematic diagram of the model along with boundary conditions is shown in Figs. 1 and 2. In Figs. 1 and 2, ten uniformly-spaced I/O pillars are shown corresponding to a I/O array of pillars on a chip. Each pillar has a 5-µm-thick copper pad at the termination of each pillar on the silicon chip and FR4 substrate. Each pillar is a cylinder (250 µm tall and 50 µm diameter) bonded to the 5-µm-thick copper pad. The pillars are used to attach a 70-µm-thick silicon die to a 1-µm-thick FR4 board. The pillar pitch is 200 µm forming a regular rectangular grid. The pitch along the diagonal line of the GPD model (Fig. 2) is µm. Thus, this half GPD model describes the thermal mechanical stress and the deformation of a 4 4 µm module with 400 copper pillars. All the boundary conditions (Fig. 2) are defined to limit the module movement and permit the free expansion in all directions, X, Y, and Z [16], [19], [20]. First, the center point of the chip, defined as the center of the bottom surface of the FR4 substrate, is fixed by restricting movement of this point. The module can expand and bend in any direction, keeping the center point fixed. In this paper, the FR4 board expands more than the silicon chip when the temperature is raised causing bending of the module in the XZ direction. Second, the crosssectional plane of the slice at X = 0 (YZ area) at the center of the module is restrained from moving in the X direction. That is, the area of the module defined by the YZ surface at the center of the module can expand in the Y and Z directions, but the plane cannot move in the X direction. Third, the plane defined by the surface at the outside of the slice (Y = 70.1 mm) can bend in the XZ direction, but cannot bend in the XY, or YZ direction. This is done by setting the area defined by Fig. 1. Schematic diagram of half GPD model for a 4 mm 4 mm die with 200 µm pitch. Fig. 2. Boundary conditions (UX is the displacement in the X direction and UY is the displacement in the Y direction) and two stress characterization lines. Dashed line Line(a) is parallel to X direction and Line(b) is parallel to Z direction. the outside surface of the slice to have zero movement in the Y direction. Finally, the slice symmetry requires that the XZ plane cannot expand or bend in the XY direction. Thus, the module can expand freely in the +X, Z directions and bend in the XZ direction. The half GPD model was meshed by all hexahedral elements shown in Fig. 3. The finite element analysis was carried out using ANSYS software. The element independence was studied for each design by evaluating the maximum thermal stress in the silicon die at 100 C as a function of the number of nodes used (Fig. 4). Convergence is established at nodes and the maximum thermal stress in the silicon was 175 MPa, data point 4 in Fig. 4. The relative error at this point is less than 1% compared with the final point 6 where nodes were used. The stress resulting from a 100 C static temperature excursion from the stress-free state was analyzed. Thermal mechanical properties of the materials at 100 C are listed in Table I. III. Results Thermally induced stress is a key issue in first-level packaging. Stress induced defects, such as cracks, can occur

3 AN AND KOHL: THERMAL-MECHANICAL STRESS MODELING OF COPPER CHIP-TO-SUBSTRATE PILLAR CONNECTIONS 623 Fig. 5. Schematic diagram of deformed half GPD model under at high temperature. (a) Neutral stress situation. (b) High temperature situation. Fig. 3. Hexahedral mesh elements. Fig. 4. Mesh dependence on node count. TABLE I Linear Thermoelastic Properties for Materials of Interconnection (100 C) Material Si [21] Cu [22] FR4 board [23] Modulus (GPa) EXY: EZ: 1.16 CTE (ppm/ C) Poisson s Ratio v YZv ZX: v XY :0.002 within the inter-layer dielectric on a silicon die. Therefore, in this paper, the stress distribution just within the silicon die designated by Line(a) in Fig. 2, and the stress distribution along the length of the copper pillar, as designated by Line(b) in Fig. 2 are characterized. Line(a) is a center-line along the diagonal of the silicon die, 1 µm deep into the silicon. Line(b) is the line in the Z direction at the right side of the last pillar farthest from the center of the die where the maximum strain occurs. The 100 C thermal loading causes a greater thermal expansion in the FR4 board compared to the silicon die resulting in a deformation of the full chip-package structure. A drawing of pillar deformation (not drawn to scale) is shown in Fig. 5. The left side of Fig. 5 corresponds to the center of the device and the components expand outward toward the right side. The higher CTE of the FR4 board, compared to the silicon substrate, causes it to expand more at elevated temperature. As a result, the right side of the structure in Fig. 5 curves upward and the pillars deform accordingly. The resulting stress distributions of Line(a) and Line(b) are shown in Figs. 6 and 7, respectively. In this particular analysis, the cylindrical copper pillars were terminated directly on the silicon and FR4 substrates with a contact-pad which has twice the diameter of the pillar. In the next section, the benefits of a contact-pad on each substrate will be shown. Fig. 6 shows the von Mises stress distribution along Line(a) (as shown in Fig. 2) from the center of the die outward to the diagonal corner of the die. The peaks in the stress in Fig. 6 correspond to the leading and trailing edge of each of the ten pillars. A peak is seen at each side (i.e., the side closest to the chip center and the side farthest from the chip center) of each pillar. The magnitude of the stress becomes progressively greater with distance from the center of the chip because the greater expansion of the FR4 board forces the pillars to distort more toward the edge of the chip. The accumulated expansion and deformation in X direction, as shown in Fig. 2 near the outer edge of the components, are different with the CTE of the FR4 being larger than that of silicon. Thus, the stress in the last several pillars is higher than that of the center pillars. In addition, the stress at right side of each pillar is higher than the stress at the left side of the pillar. The stress level within the chip is in tension at the left side of each pillar and in compression at the right side of each pillar. The maximum stress in the silicon occurred in the ninth pillar (not the tenth and last pillar) due to the unconstrained edge of the substrate acting on the last pillar. The maximum von Mises stress in the silicon die without a bond pad on the die at 100 C is about 175 MPa at the interface between the copper pillar and the silicon die. The stress along the length of the last pillar, given by Line(b), is shown in Fig. 7. The x-axis of Fig. 7 corresponds to stress along the length of the pillar (Z-axis value in Fig. 2). The zero value distance in the x-axis of Fig. 7 corresponds to the pillar-to-fr4 board interface and extends along the length of the copper pillar (distances from 0 µm to 250 µm), and finally extending into the silicon die (values > 250 µm). Within the FR4 board (i.e., 200 µm to 0 µm in Fig. 7), the stress level is less than 50 MPa. At the interface of the

4 624 Fig. 6. Fig. 7. IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 33, NO. 3, SEPTEMBER 2010 Stress distribution along Line(a) in the X direction. Stress distribution along Line(b) in the Z direction. FR4 board and the pillar, Z = 0 in Fig. 7, a peak in the von Mises stress is observed. At the interface of the pad and the pillar (Z = 250 µm), a second peak in stress is observed. The maximum stress occurred at the joint between the cylindrical pillar and the chip-pad. Without the chip-pad, the maximum stress at the interface between the pillar and the silicon die is more than 350 MPa. However, with the chip-pad, the maximum stress is 175 MPa (5-µm-thick pad, 100 µm in diameter), Although the maximum stress (450 MPa) occurred at the interface of the pillar and the chip-pad, the stress within the silicon (Z = 255 µm in Fig. 7) is only 175 MPa. In the next section, it will be shown how a copper pad on the silicon chip helps to distribute this stress over a larger area. Within the silicon die (Z > 255 µm) the stress decreases sharply with distance. Fig. 8 is a nodal contour plot of the von Mises stress on the side of the outermost, tenth pillar. The maximum stress (450 MPa to 515 MPa corresponds to the red color in the scale in Fig. 8) occurs at the corner between the pillar and the chippad at the last two pillars. The maximum deformation for a 4 4 mm2 die at 100 C is 21 µm. The effect of a contact pad on the silicon and FR4 substrates on the stress distribution within the silicon die was investigated. Contact pads, 0.5 µm to 10-µm-thick, are generally fabricated on a chip during back-end chip processing and on an FR4 substrate during board manufacturing [9]. Chip I/O which terminate with a buried via on the silicon die were not evaluated here, but are expected to be more favorable since the stress can be distributed over a larger area, although sharp corners are not desirable. It was found that the thermal-mechanical stress Fig. 8. Nodal contour results for the von Mises stress for the tenth pillar. Fig. 9. Schematic diagram of the copper pad. in the silicon die was affected by the presence and size of the contact pad. Circular chip pads with diameters of 50 µm, 60 µm, 70 µm, 80 µm, 90 µm, 110 µm, and 120 µm, and square pads µm and µm on a side (I/O halfpitch and full surface metallization for comparison purposes) were investigated, as shown in Fig. 9. Other parts in this model, including mesh, boundary conditions, and loading, are the same as the previous model. The stress peak at the pillar-to-silicon interface for the last pillar along Line(a) is shown in Fig. 10 for the different size pads. Without the chip-pad (i.e., 50 µm pad in Fig. 10 pad being the same size as the pillar), the force on the chip due to the bending pillar caused high stress at the edge of the pillar. The pad helps to spread this force over a larger area (area of the chip-pad). Thus, the stress at this corner in the pillar without a pad is much higher than that of a structure with a pad. In addition, as the surface area of the pad increased, the stress in the silicon decreased because the force is spread over a wider area pad. Fig. 11 shows the value of the maximum stress (such as Fig. 10) for the last three pillars along Line(a) at the inside edge and outside edge of the pillar as a function of the pad size. The maximum stress at the inside edge of each pillar decreased with pad size and then increased to a steady value of 120 ± 20 MPa as the pad size approached µm. The maximum stress at the outside edge of each pillar decreased to a value of 130 ± 20 MPa. These values of the von Mises stress, such as in Fig. 11, are related to ( σ1 σ2, σ2 σ3, σ3 σ1 ), the maximum absolute value of the difference in the principal stresses. The

5 AN AND KOHL: THERMAL-MECHANICAL STRESS MODELING OF COPPER CHIP-TO-SUBSTRATE PILLAR CONNECTIONS 625 Fig. 10. Peak in the stress distribution along Line(a) in the X direction as a function of pad size. Fig. 13. Schematic diagrams of the principal stresses along Line(a) for the inner and outer sides of the tenth pillar at high temperature. Stresses at the inside of the pillar: (1) with no chip-pad, (2) with a small area chip-pad, and (3) with a large chip-pad. Stresses at the outside of the pillar: (4) without a chip-pad, (5) with a small chip-pad, and (6) with a large chip-pad. Fig. 11. Maximum stress at the top of the last three pillars 1 µm deep in the silicon substrate as a function of pad size. Fig. 12. Principal stresses along Line(a) for the inner and outer sides of the tenth pillar vs. pad size. principal stresses vary with the pad size as shown in Fig. 12. From Fig. 12, the maximum of the difference between the principles is shown to decrease at the outer side of the pillar. Fig. 13 is a schematic diagram of the principal stresses and an aid to viewing the principal stresses listed in Fig. 12. In Fig. 13, S1, S2, and S3 are the principal stresses of the node at the corner of the pillar. The principle stress S1 (inside of pillar) is the main stretching stress whose direction is nearly vertical in Fig. 13. The exact directions of the principal stresses are determined by the value of the stress components and the shear stresses. The stresses on the left side of the pillar are all tensile (red color) when loading high temperature, regardless of the size of the chip-pad because the pad is stretched by the bending pillar [see Fig. 13, parts (1), (2), and (3)]. The tensile stress S1 decreases when the 70 µm chip-pad is used. On the other hand, the horizontal stresses, S2 and S3, decrease slightly for larger pads because the larger pad serves to distribute the stretching force over a larger pad area resulting in lower stress. The von Mises stress in Fig. 11, inside the last pillar (dashed lines in Fig. 11), is determined by σ1 σ3. Thus, the von Mises stress decreased with increasing pad size. The same mechanism can be used to explain the stresses in the outside of pillar. The principal stresses at the outside corner of the pillar are given in Fig. 12 (solid lines), with the schematic drawing shown in Fig. 13 [parts (4), (5), and (6)]. In this case, S3 becomes the main stress because of the changing shear stresses. The vertical stress at the outside of the pillar is always compressive (blue color in Fig. 13) because of the force from the bending pillar. However, the horizontal stresses become tensile (red color in Fig. 13) from the compressive stress with larger pads. The vertical compressive stress S3 shows lower values because the pad is inserted in the structure and distributes the force over a wider area, while the horizontal stresses, S1 and S2, become tensile because to the CTE of copper is larger than that of the silicon. When the chip-pads are enlarged, the stress caused by the CTE mismatch between silicon chip and copper pad exceeds the stress caused by the bending pillar. Therefore, the von Mises stress at the outside of the pillar, which is proportional to σ1 σ3, decreases substantially with pad size. Pad diameters 1.5 to 2 times that of the pillar footprint are an effective means to lowering the stress within the substrate at the terminus of the pillar. In an effort to improve the reliability of copper pillars and silicon die, the use of a polymer support around the copper pillars was considered. The half GPD model was used to

6 626 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 33, NO. 3, SEPTEMBER 2010 Fig. 14. No collar, one collar, and two collars models. compare pillars with collars: 1) on both the silicon and FR4 sides; 2) only the silicon side; and 3) without a collar support, as shown in Fig. 14. Generally, it was found that collars provide mechanical support for the pillars by distributing the thermally induced forces across a greater volume element in the I/O structure. In Fig. 14, the diameter of full pillar-collar structure was designed to be 100 µm with a 50µm diameter copper pillar at the core. The properties of the collar material were chosen to be consistent with available materials, such as epoxy, for investigating the collar s function. The length of the collar originating from each substrate was 115 µm. Thus, there was a gap of 20 µm between the ends of the two collars at the center of the pillar for case 1), where there is a collar originating from each substrate. This case corresponds to the situation where a polymer plating mold (called collar here) was used to fabricate each of the pillars on the silicon substrate and FR4 substrate. The von Mises stress along Line(a) for the pillar farthest from the center of the chip is shown in Fig. 15 for all three collar structures: no collar, one collar, and two collars. The x-axis value in Fig. 15 corresponds to the distance from the center of the chip where the highest von Mises stress occurred. As seen in Fig. 15, the value of the maximum stress decreased when a supporting collar was added to the copper pillar. The mechanical properties of the collar are shown in Table II, and are similar to that of epoxy. Since the highest stress point occurred at the silicon interface, the polymer collar originating from the silicon substrate was the most important of the two collars. Thus, the one-collar case and two-collar case (see Fig. 14) are similar. There was a 34% decrease in stress when a collar was added to the pillar. The stress decreased from 175 MPa, for the no-collar model, to 115 MPa, for the onecollar and two-collar models. Thus, a polymer collar used to help create the copper pillars, can serve to help decrease the stress in the silicon die. This also shows that a single pillar with a collar fabricated on the silicon chip and terminating on the FR4 board should be just as effective two pillars, each with a collar, bonded in the middle. The stress along Line(b) shows that the maximum stress decreased from 450 MPa in the case of no collar, to less than 200 MPa in the case of one or two collars. The model also shows that the point of maximum stress in the copper pillar occurs at different locations along the length of the copper pillar when collars are used. The location of maximum stress in the copper pillar for the onecollar and two-collar models is in the center of the pillar where Fig. 15. Stress distribution along Line(a) in the X direction for the three models: no collar, one collar, and two collars. Fig. 16. Stress distribution along Line(b) in the Z direction of three models: no collar, one collar, and two collars. TABLE II Linear Thermoelastic Material Properties for Collars (100 C) Material Modulus CTE (ppm/ C) Poisson s (MPa) Ratio 1 A high-modulus-material Epoxy [24] Polymide [25] SU8 [26] Avatrel [27] the collar ends, and not at the end of the pillar where it meets the silicon substrate, as shown in Fig. 16. The stress increased in the center of the pillar which led to a reduction in the stress at the end of pillar close to the silicon die. The maximum stress at the pillar-silicon joint decreased from 450 MPa to 50 MPa by adding one or two collars around the copper pillar. Although the collar support helps to decrease the stress within the silicon die, the degree of improvement depends on the mechanical properties of the collar. The effectiveness of the collar support was investigated by using materials with different elastic modulus as listed in Table II. The one-collar, half GPD model was used to assess the effect of collar modulus on the magnitude of the stress. The same size elements, boundary conditions, and thermal loading were used as in the studies (above) for modeling the pillars with copper pads. The von

7 AN AND KOHL: THERMAL-MECHANICAL STRESS MODELING OF COPPER CHIP-TO-SUBSTRATE PILLAR CONNECTIONS Fig. 17. Stress distribution along Line(a) at top of last pillar in the X direction for the five collar materials. Fig. 18. Stress distribution along Line(b) in the Z direction for the five collar materials. Mises stress in the silicon substrate along a portion of Line(a) corresponding to the location of the last pillar farthest from the center of the silicon die for the five different collar materials shown in Fig. 17. The thermally induced stress in the silicon substrate decreased as the collar modulus increased and the location (x-axis) of the maximum stress also changed slightly. The maximum stress decreased from 160 MPa to 100 MPa when the collar modulus increased from 1.2 GPa to 11.8 GPa. The stress along the length of the copper pillar, Line(b), is shown in Fig. 18 for the five different collar materials. When a higher modulus collar was used, a lower stress was observed at the pillar-to-silicon interface. Thus, a high modulus collar is highly advantageous in redistributing the mechanical forces to regions within the center of the pillar which are less destructive to the interlayer dielectric on the silicon die. The length of the supporting collar along the length of the copper pillar was also considered. Four different collar lengths (single-collar cases) were considered: 50 µm, 115 µm, 175 µm, and 230 µm. The high modulus epoxy material was chosen for the collar (see Table II). The same boundary conditions were used as in Fig. 2 and the temperature was changed by 100 C. The stress along Line(a) of the last pillar is shown in Fig. 19 for different length collars. The results show that the maximum stress in the silicon die varied only 627 Fig. 19. Stress distribution along Line(a) at the top of last pillar in the X direction for four different length collars. Fig. 20. Stress distribution along Line(b) in the Z direction for four different length collars. slightly as a function of collar length. However, the stress distribution in the copper pillar, Line(b), shifted a large amount by changing the length of the collar, as shown in Fig. 20. The maximum stress in the copper pillar decreased with increasing length of the collar. The stress in the center of copper pillar where the collar ends was 200 MPa for the 50-µm-long collar and dropped to less than 20 MPa for a 230-µm-long collar. However, the stress at the pillar-collar interface remained almost the same for the different length collars, as shown in Fig. 20. IV. Conclusion The effect pillar configuration and materials on the thermomechanical stress in an all-copper, silicon-to-fr4 connection have been analyzed using finite element modeling. The von Mises stress within the silicon substrate [Line(a)] and within the last (highest strain) pillar [Line(b)] were analyzed. The stress amplitude and distribution were found to be function of copper pad size, collar modulus, and collar length. The larger contact pad size served to distribute the thermally induced force over a larger area and reduced the stress. A supporting collar lowered the stress in the silicon die. The supporting collar also caused the highest stress point within the pillar to be redistributed from the pillar-to-silicon interface to the middle

8 628 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 33, NO. 3, SEPTEMBER 2010 of the pillar at the termination of the collar. The modulus of collar is the most important parameter in determining the amount of stress redistribution. A higher collar modulus was more effective at lowering the stress within the silicon die. Acknowledgment The discussions with Prof. J. Qu, Northwestern University, Evanston, IL, C. Hunter Lightsey, Georgia Institute of Technology, Atlanta, and H.-C. Koo, Georgia Institute of Technology are gratefully acknowledged. References [1] International Technology Roadmap for Semiconductors, Assembly and Packaging. (2009) [Online]. Available: [2] C. Basaran, H. Ye, D. C. Hopkins, D. Frear, and J. K. Lin, Failure modes of flip chip solder joints under high electric current density, J. Electron. Packag., vol. 127, no. 2, pp , [3] D. Yang, Y. C. Chan, B. Y. Wu, and M. Pecht, Electromigration and thermomigration behavior of flip chip solder joints in high current density packages, J. Mater. Res., vol. 23, no. 9, pp , [4] W. C. Kuan, S. W. Liang, and C. Chen, Effect of bump size on current density and temperature distributions in flip-chip solder joints, Microelectron. Reliab., vol. 49, no. 5, pp , [5] C. Yu, H. Lu, R. Z. Fan, and S. M. Li, Factors influencing current density distribution and current crowding in flip chip solder joints, Sci. Technol. Welding Joining, vol. 12, no. 5, pp , [6] M. Bigas and E. Cabruja, High density of electrodeposited Sn/Ag bumps for flip chip connection, Microelectron. Eng., vol. 83, no. 3, pp , [7] K. L. Lin, E. Y. Chang, and L. C. Shih, Evaluation of Cu-bumps with lead-free solders for flip-chip package applications, Microelectron. Eng., vol. 86, no. 12, pp , [8] K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, B. C. Webb, J. Maria, E. J. Sprogis, S. K. Kang, R. J. Polastre, R. R. Horton, and J. U. Knickerbocker, 3-D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections, IBM J. Res. Dev., vol. 52, no. 6, pp [9] T. Osborn, A. He, N. Galiba, and P. A. Kohl, All-copper chip-tosubstrate interconnects: Part I. Fabrication and characterization, J. Electrochem. Soc., vol. 155, no. 4, pp. D308 D313, [10] A. He, T. Osborn, S. A. Bidstrup, and P. A. Kohl, All-copper chip-tosubstrate interconnects: Part II. Modeling and design, J. Electrochem. Soc., vol. 155, no. 4, pp. D314 D322, [11] S. Gao and A. S. Holmes, Thermosonic flip chip interconnection using electroplated copper column arrays, IEEE Trans. Adv. Packag., vol. 29, no. 4, pp , Nov [12] A. Fan, A. Rahman, and R. Reif, Copper wafer bonding, Electrochem. Solid State Lett., vol. 2, no. 10, pp , [13] T. H. Kim, M. M. R. Howlader, T. Itoh, and T. Suga, Room temperature Cu-Cu direct bonding using surface activated bonding method, J. Vac. Sci. Technol. A, vol. 21, no. 2, pp , [14] A. He, T. Osborn, S. A. B. Allen, and P. A. Kohl, Low-temperature bonding of copper pillars for all-copper chip-to-substrate interconnections, Electrochem. Solid State Lett., vol. 9, no. 12, pp. C192 C195, [15] T. Osborn, C. H. Lightsey, and P. A. Kohl, Low-k compatible all-copper flip-chip connections, Microelectron. Eng., vol. 86, no. 3, pp , [16] A. Yeo, C. Lee, and J. Pang, Flip chip solder joint fatigue analysis using 2-D and 3-D FE models, in Proc. EuroSimE, 2004, pp [17] J. H. Lau and S.-W. R. Lee, Modeling and analysis of 96.5 Sn-3.5 Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board, IEEE Trans. Electron. Packag. Manuf., vol. 25, no. 1, pp , Jan [18] T. Y. Tee, H. S. Ng, D. Yap, X. Baraton, and Z. Zhong, Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications, Microelectron. Reliab., vol. 43, no. 7, pp , [19] R. Darveaux, Effect of simulation methodology on solder joint crack growth correlation, in Proc. Electron. Compon. Technol. Conf., 2000, pp [20] B. Zahn, Impact of ball via configurations on solder joint reliability in tape-based, chip-scale packages, in Proc. Electro. Compon. Conf., 2002, pp [21] B. Z. Hong and L. G. Burrell, Nonlinear finite-element simulation of thermoviscoplastic deformation of C4 solder joints in high-density packaging under thermal cycling, IEEE Trans. Compon. Packag. Manuf. Technol. A, vol. 18, no. 3, pp , Sep [22] D. L. Mcdowell, A bounding surface theory for cyclic thermoplasticity, J. Eng. Mater. Technol., Trans. ASME, vol. 114, no. 3, pp , [23] S. Liu, Y. Mei, S. Zhou, and J. Zhu, Effect of processing induced defects on reliability of plated through holes in PWB, in Proc. 27th Int. Symp. Microelectron., Boston, MA, Nov. 1994, pp [24] Henkel International [Online]. Available: [25] Wikipedia [Online]. Available: wikipedia.org [26] MicroChem Corp. [Online]. Available: microchem.com [27] V. Rajarathinam, C. Hunter Lightsey, T. Osborn, B. Knapp, E. Elce, S. A. B. Allen, and P. A. Kohl, Aqueous-develop, photosensitive polynorbornene dielectric: Properties and characterization, J. Electron. Mater., vol. 38, no. 6, pp , Ping Nicole An is currently pursuing the graduate degree in mechanical engineering from the Institute of Microelectronics, Peking University, Beijing, China. Her current research interests include the mechanics of materials, especially for micro-electromechanical systems and electronic applications and finite element modeling. Paul A. Kohl received the Ph.D. degree in chemistry from the University of Texas, Austin, in He is a Regents Professor and Holder of the Thomas L. Gossage/Hercules Inc. Chair, School of Chemical and Biomolecular Engineering, Georgia Institute of Technology, Atlanta. Previously, he was with AT&T Bell Laboratories, Murray Hill, NJ. His current research interests include materials and processes for electronic materials and new approaches to energy storage.