Board Level Reliability of BGA Multichip Modules

Transcription

1 Board Level Reliability of BGA Multichip Modules Robert Darveaux and Bhuvaneshwaran Vijayakumar Skyworks Solutions, Inc. Irvine, CA ABSTRACT The board level reliability of BGA multichip modules was characterized under thermal shock and drop test conditions. The variables studied were BGA pattern, substrate surface finish, solder joint size, and module size. Thermal cycle reliability was quite robust for all test vehicles since the body sizes were less than 7mm on a side. Drop test reliability improved with smaller body size, larger solder mask opening on the package, and ENEPIG surface finish. Measured test results were compared to finite element analysis predictions. Accumulated strain energy density over 30ms of board vibration correlated better to drop test reliability than peak stress level. Recommendations are made for optimizing design and material set relative to board level reliability performance. INTRODUCTION Laminate based RF modules for wireless applications typically have relatively small body size (<8mm) and LGA style package terminals. In some applications, BGA style packages are being evaluated as a way of populating both sides of the module substrate. of such intermittent discontinuity, and followed by 3 additional such events during 5 subsequent drops. Table 1 Test Vehicles (dimensions in mm) Test Vehicle Body Size 6.9 x x x x x x x 3.0 Body Thickness Ball Pitch , Package Solder Mask Opening Motherboard 0.20 x 0.20 x 0.23 x 0.20 x 0.23 x 0.30 x 0.25 Pad Size Package Pad NSMD NSMD NSMD NSMD/ NSMD/ Design SMD SMD NSMD NSMD Package Surface Finish ENEPIG OSP ENEPIG ENEPIG ENEPIG ENEPIG OSP The present study characterizes board level reliability of BGA multichip modules under thermal shock test and drop test conditions. The variables studied were BGA pattern, substrate surface finish, solder joint size, and module size. Finite element analysis was used to better understand reliability performance, and to develop a predictive model. EXPERIMENTAL PROCEDURE Seven test vehicles were used to characterize reliability of BGA multichip modules. The test vehicle descriptions are shown in Table 1. The variables included body size, body thickness, ball pitch, ball pattern, package solder mask opening, motherboard pad size, package pad design, and package surface finish. The solder alloy was SAC305. The motherboard surface finish was OSP. Drop testing was conducted per JEDEC JESD22-B111 standard. A total of 60units (4 boards x 15 units per board) were tested for each package type. The board was secured to the base plate of the drop table with screws and washers using the four corner holes. A peak impact acceleration of 1500G shaped approximately like a half-sine waveform and lasting for 0.5ms was used. The measured acceleration profile is shown in Fig 1. An event detector was used to detect any resistance greater than 1000Ohms lasting for 1microseond or longer. Failure was defined as the first event Figure 1. JEDEC drop test acceleration profile. Figure 2: -40C 125C, 2cph, thermal shock profile measured on test samples.

2 Cumulative Failures (Median Rank) The thermal shock chamber was programmed for 2 cycles per hour as follows: -40 C for 15 minutes, and +125 C for 15 minutes. Transfer of the cage takes place in less than one minute, so the thermal ramp rates are relatively fast. The measured temperature profile on samples in the chamber is shown in Figure 2. EXPERIMENTAL RESULTS The drop test results for TVs 1 through 5 are shown in Figure 3. These modules all had a body size of 6.9 x 4.8mm. A Weibull plot of the data in Figure 3 is shown in Figure 4, and the Weibull constants are given in Table 2. Table 2. Weibull Constants for Drop Test Results Leg 1 Leg 2 Leg 3 Leg 4 Leg 5 Leg 6 Leg 7 slope, b NA NA Characteristic life (drops) >> 200 >> 400 N50 (drops) >> 200 >> 400 Tests for TVs 6 and 7 were terminated without any failures after 200 drops and 400 drops, respectively. Hence, smaller body size had a significant impact in improving drop test reliability. Cross sectional pictures of failed joints are shown for TV2 and TV1 samples in Figures 5 and 6, respectively. It is seen that brittle interface fracture occurs for both cases of package substrate surface finish. TV2 had OSP finish and TV1 had ENEPIG finish. Even though they had the same failure mode, the drop test reliability of OSP finish samples was much lower Drops TV 2 TV 1 TV 4 TV 3 TV 5 Figure 5. Failure mode of solder joint from TV 2. OSP surface finish on package. Figure 3. Drop test results. Figure 6. Failure mode of solder joint from TV 1. ENEPIG surface finish on package. The effect of solder joint area can be seen by comparing results for TV1and TV3, or TV4 and TV5. It is seen that increasing solder mask opening area by 1.3x improved the mean reliability (N50) by 1.9x to 2.3x. The first failure also improved, but was not as consistent for each test (0.8x to 4.1x). Figure 4. Weibull plot of drop test results. The temperature cycle results are shown in Table 3. TV7 had the first failure at 4859 cycles. TVs 1,2,4, and 5 passed 2000 cycles before the test was terminated. Hence the BGA modules have very robust thermal cycle reliability for the body size and joint size range tested in the present evaluation.

3 Table 3 Temperature Cycle Results Test Vehicle Temp Cycle > 2000 > 2000 > 2000 > First Failure cycles cycles cycles cycles cycles SIMULATION METHODOLOGY Drop Test Simulation Finite Element Modeling was used to simulate the JEDEC drop test. The simulation methodology involves the use of direct acceleration input to the screw holes. ANSYS Finite Element Software with implicit analysis capability was used in this study. A simple package structure that includes the mold compound, PCB, solder joints and JEDEC board is shown in Figure 7. The package size was 6.9x4.8mm, and the solder joint size of 0.23 x 0.23mm. Each of the solder joints was modeled using one element in the plane of the package and with two elements along the package thickness direction. Elastic material properties used for the model are shown in Table 4. The results in Figures 9 to 13 were obtained using linear elastic properties for all materials. Table 4 Elastic material properties Young s Poisson s Modulus ratio (GPa) Density (Kg/mm 3 ) Solder Mold Compound PCB Substrate JEDEC Board Table 5. Component Grouping for Data Analysis Group Board Locations A U1, U5, U11 & U15 B U2, U4, U12 & U14 C U6 & U10 D U7 & U9 E U3 & U13 F U8 A 0.5ms long half-sine acceleration pulse with a peak acceleration of 1500G was input directly at the screw holes. The implicit time step was set at ms for the first 0.5ms duration of the acceleration pulse and then increased to 0.05ms for the rest of the simulation time duration. The element average Von Mises stress on the four corner joints were analyzed for all the fifteen package locations on the JEDEC board. The locations were grouped as shown in Table 5 and Figure 8 according to a previous study [1] by Syed et al. Figure 8. JEDEC board with component locations labeled a) Entire model. (b) Individual package. (c) Solder joint pattern. Figure 7. Finite element model for drop test. Element averaged Von Mises stress on the solder joint was used for comparison. Figure 9 shows the maximum stress on the corner joints of all the fifteen component locations. The stress values are color coded depending on the magnitude of stress. Group E shows the maximum stress among all the groups. Groups A & B show the next higher stress levels and are quiet similar. Also, this group shows the widest variation in stress between the four corner joints. The next highest stress is seen in Group F followed by Group D and then Group C. It can also be seen from Figure 9 that the stress values are almost symmetric with respect to the center line along the longer direction of the board. The minor variation is due to the unsymmetrical solder joint pattern. Simulating a pattern with full second row of solder joints on the bottom side of the package resulted in perfectly symmetrical results. This shows that package symmetry can be taken advantage of to reduce the computational time. Figure 10 shows how the stress varies with time on all the sixty corner solder joints. It can be seen that the maximum stress is reached in the vicinity of about 1.9ms for all the

4 groups. Note that the time zero is the starting of the halfsinewave acceleration pulse that lasts for duration of 0.5ms. Figure 11 is a re-plot of Figure 9 showing the stress values in descending order. This plot shows a wide range of almost 3X variation in stress across the fifteen different component locations. between the volume averaged stress of single element and fine mesh models. The stress is volume averaged over a thickness of 20um for the fine mesh model. The stress profile with respect to time is very similar although the magnitude is lower for the fine mesh case. The averaged stresses are lower because a truncated sphere joint shape is elastically more compliant than a cube shaped joint. If the maximum stress were plotted instead, the fine mesh model would show about 2x higher values than the coarse mesh model (which is more commonly seen in finite element analysis of structures with stress concentration points). Figure 9. Maximum element averaged Von Mises stress (MPa) on the corner solder joints (linear elastic model). (a) Detailed corner solder joint shape on unit U3. Figure 10. Element averaged Von Mises stress time profile on corner joints (linear elastic model). (b) Von Mises stress results (MPa). Figure 12. Refined mesh linear elastic model and results. Figure 11. Peak element averaged Von Mises stress on the corner solder joints in descending order (linear elastic model). Next, the effect of refining the mesh with a detailed solder joint shape on the corner joint was studied. Figure 12(a) shows the detailed solder joint shape and 12(b) shows the plot of Von Mises stress. Figure 13 shows the comparison Next, the creep properties for the solder material along with plasticity of copper were included in the model with single element solder joints. The material constants were taken from refs [2-4]. The accumulated viscoplastic strain energy density was used as the damage indicator. Results show that the simulation time of 5ms was not sufficient for the viscoplastic strain energy density to reach a steady state. After a couple of trails it was found that the simulation time had to be extended to 30ms or more in order to get the accumulated viscoplastic strain energy density to reach a steady state value. Also, it was found that greater

5 accumulated viscoplastic strain energy regions take more time to reach steady state. rate seen by the solder joints during the drop test is less than 110 sec -1. Hence, the deformation is in the range of the measured creep data in ref [4]. The solder behavior is definitely time dependent at these rates. Figure 13. Comparison of volume averaged stress results between two element model and fine mesh model on the corner joint of U3 (linear elastic case). Figure 14 shows the plot of steady state accumulated viscoplastic strain energy density at the end of 30ms simulation time for all the corner joints for the 15 component locations. Comparing this with stress results from the linear elastic model that showed Group E having the highest stress, the creep model shows that the maximum risk is for Group A that is located closest to the screws. Figure 15. Maximum accumulated viscoplastic strain energy density (MPa) for corner balls at each component location (non-linear model). Figure 15 shows the plot of the maximum accumulated viscoplastic strain energy density among the 4 corner balls versus time for each of the 15 component locations. The plot clearly shows that the higher strain energy values takes longer time to reach steady state. Figure 16. Von Mises strain profile on the solder joint with maximum viscoplastic strain energy density accumulation (non-linear model). Figure 14. Accumulated viscoplastic strain energy density (MPa) in the corner joints of all 15 units (non-linear model). Not many previous studies have incorporated creep properties in the solder for a drop test simulation. The stated assumption has been that strain rates are very high, and the solder does not have time dependent behavior at such high strain rates. Testing on actual solder joints shows time dependent deformation at rates over 10 sec -1 and temperatures down to -55C [4]. Figure 16 shows a plot of strain on the worst case solder joint. The derivative of this curve was calculated and plotted in Figure 17 to show the strain rate as a function of time. It can be seen that the strain Figure 17. Von Mises strain rate profile on the solder joint with maximum viscoplastic strain energy density accumulation (non-linear model).

6 Taking into account the creep properties of solder is not only critical for the accuracy of the simulation results, but it also changes the location of the high risk components on the JEDEC board. For instance the above simulations show that with linear material properties Group E was determined to have the highest stress but with creep/plasticity included, Group A was determined to have the highest accumulated viscoplastic strain energy density. The actual drop testing revealed Group A to fail much earlier than Group E. SIMULATION CORRELATION TO MEASUREMENT RESULTS The accumulated strain energy density on Group A locations was used for correlation with drop test failure rate. Test vehicles for drop test included variations in pad size, package size, and pad design as shown in Table 1. TV 6 was tested up to 200 JEDEC drops and TV 7 up to 400 drops and both of these legs had no failures. Only TVs 1 through 5 had failures when tested up to 200 drops. Most of the failures were on Group A units that are located near the screws, as was predicted by the accumulated viscoplastic strain energy density results in Figure 14 & 15. TV 2 with OSP finish had remarkably poor drop test performance compared to TV 1. TVs 1, 3, 4 & 5 had ENEPIG finish and showed much better drop test performance. In those legs, the Group C & D units never failed and correlates with the simulation results showing the lowest accumulated strain energy density in Figures 14 & 15. The simulated damage indicator for Group A from TVs 1 & 3 at different locations was plotted against the first drop test failure in Figure 18. The plot shows a good power law correlation between simulation and measurements. The data from TV s 6 and 7 are shown as open circles where the test was terminated, and closed circles where predicted performance was estimated if the testing had continued. work comparing NiAu finish to OSP finish typically yielded better reliability for Cu/OSP for the case of SAC305 solder alloy [7,8]. However, the previous work used a relatively thick Ni layer in the NiAu finish compared to the current ENEPIG finish. In addition, the Cu/OSP finish performance was shown to be sensitive to reflow conditions [8,11]. It is possible that higher reflow temperature or multiple reflows degraded the performance of TV2. Since the primary failure mode was brittle intermetallic failure TVs 1 through 5, it is likely that performance can be improved by using a lower Ag content alloy. SAC105 or SAC125Ni have been shown to improve drop test performance over SAC305 [5-9]. Ni additions in the alloy are useful in the case of Cu/OSP finish to improve the robustness of the intermetallic structure at the pad interface. Lower Ag content results in a less creep resistant alloy, so stresses on the pad interface are reduced. In the present study, the correlation between drop test life and accumulated viscoplastic strain energy density had a power law exponent of Previous work using elastoplastic properties resulted in a power exponent of -1.4 [10]. However, both studies were able to achieve a reasonable correlation with experimental results. CONCLUSIONS 1) The board level reliability of BGA multichip modules was characterized under thermal shock and drop test conditions. 2) Drop test reliability improved with smaller body size (TV6 vs. TV5, ~2x), larger solder mask opening on the package (TV3 vs. TV1, and TV5 vs. TV4, ~2x), and ENEPIG surface finish (TV1 vs. TV2, ~15x). 3) Failure location on the JEDEC board correlated better with accumulated viscoplastic strain energy density compared to peak stress level. 4) A correlation between measured drop test life and calculated accumulated viscoplastic strain energy density was achieved with a power law exponent of ACKNOWLEDGMENTS The authors would like to acknowledge valuable contributions from Howard Chen, Shaul Branchevsky, Tony LoBianco, Matt Read, Priya Sundarraman, Ben Zarkoob, Dan Sherwood, and Michael Johnson. Figure 18. Correlation of drops to first failure versus accumulated viscoplastic strain energy density using data from Group A corner locations of TVs 1 & 3. DISCUSSION In the current study, an ENEPIG surface finish on the package substrate performed better than an OSP finish (TV1 vs. TV2). This is somewhat unexpected since previous REFERENCES 1] A. Syed, S.M. Kim, W. Lin, J.Y. Kim, E.S. Sohn, J.H. Shin, A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages, IEEE Transactions on Electronics Packaging Manufacturing, Vol 30, Issue 1, Jan 2007, pp ] CINDAS Report 105, Purdue University, December ] R. Darveaux, J. Yang, R. Sheriden, B. Buella, P. Villareal, RF PA Module Substrate Via Reliability, Proc. ECTC, 2003.

7 4] R. Darveaux and C. Reichman, Solder Alloy Creep Constants for Use in Thermal Stress Analysis, Proc. SMTAI, ] R. Darveaux, C. Reichman, S. Enayet, W.S. Hsu, W.T. Swe, Board Level Reliability Comparison of Lead Free Alloys, Proc. SMTAI, ] A. Syed, T.S. Kim, S.W. Cha, J. Scanlon, C.G. Ryu, Effect of Pb free Alloy Composition on Drop/Impact Reliability of 0.4, 0.5 & 0.8mm Pitch Chip Scale Packages with NiAu Pad Finish, Proc. ECTC 2007, pp ] Syed, A., Kim, T. S., Cho, Y. M., Kim, C. W., and Yoo, M., Alloying Effect of Ni, Co, and Sb in SAC solder for Improved Drop Performance of Chip Scale Packages with Cu OSP Pad Finish, proceedings of the 8 th Electronic Packaging Technology Conference, Singapore 2006, pp ] Kim, P. W., Kim, B. S., Ahn, A. H., Chung, T. G., Improvement of Drop Reliability in OSP/Cu Pad Finished Packages, proceedings of the 8 th Electronic Packaging Technology Conference, Singapore 2006, pp ] Tanaka, M., Sasaki, T., Kobayashi, T., and Tatsumi, K., Improvement in Drop Shock Reliability of Sn-1.2Ag- 0.5Cu BGA Interconnects by Ni Addition, proceedings of the 56 th Electronic Component and Technology Conference 2006, pp ] A. Syed, W. Lin, E.S. Sohn, S.W. Cha, Plastic Deformation and Life Prediction of Solder Joints for Mechanical Shock and Drop/Impact Loading Conditions, Proc. ECTC 2007, pp ] R. Darveaux and C. Reichman, Ductile-to-Brittle Transition Strain Rate, Proc EPTC, 2006