Surface Passivation and Characterization of Germanium Channel Field Effect Transistor Together with Source/Drain Engineering

Transcription

1 Surface Passivation and Characterization of Germanium Channel Field Effect Transistor Together with Source/Drain Engineering Gaurav Thareja Nishi Group, Electrical Engineering Stanford University ERC Tele-seminar October 21, 2010

2 Outline 1. Introduction 2. Surface passivation for Ge 3. Source / Drain junctions for Ge 4. Contributions and future work 1

3 Transistor Scaling Source: Intel Production Development More non-silicon elements added to MOSFET 2

4 SPA Radical Oxidation Radical oxidation [1] Physically breaking bonds and amorphization by atomic O* Enables very low temperature oxidation Slot Plane Antenna (SPA) [2] Uniform supply of high density radicals Optical Emission Intensity (arb.unit) 4kW 5Torr Ar:O 2 =1200: [1] M.Nagamine et al, IEDM 1998, [2] T. Ohmi et al., Proc of IEEE 2001 O 2 + (525nm) O 2 + (559nm) O 2 + (597nm) O 2 + (635nm) Ar Ar Ar Ar Ar Wavelength (nm) O (3p 5 P 3s 5 S) 777nm Ar Ar Ar O (3p 3 P 3s 3 S) 845nm Ar Ar Ar 3

5 Unique Features of SPA Substrate orientation independent growth [1] Conformal oxidation enabling 3D devices [2] Low temperature processing [1] Low D it GeO 2 [3] Nitridation [1] GeO x N y Interfacial Layers (IL) [3] Oxide Thickness (A ) SNF SPA Silicon calibration data (100) (110) (111) Oxidation Time (sec) N* GeO GeO x N 2y2 N* Ge Ge N* Ge O O O Ge N* Ge N* [1] T. Ohmi et al., Proc of IEEE 2001 [2] G.Thareja et al, Trans. Elec Dev (in prep.), [3] G.Thareja et al., Dev. Res. Conf., 2008 Ge Ge 4

6 High Mobility Channel Ge Advantages High electron/hole mobility Compatibility to Si LSI Lower temperature process Possible V dd scaling Process and device Issues 1. Surface Passivation issues Loss of Q ch and μ degradation 2. Deep S/D junctions Drain induced barrier lowering (DIBL) 3. Poor N-type dopant activation High parasitic resistance 4. Small electron mobility gain 5. Band-to-band tunneling (BTBT) leakage High I off for scaled devices Si Ge Bulk μ e (cm 2 /Vs) Bulk μ Η (cm 2 /Vs) Band gap (ev, 300K) Dielectric constant S Ge G Si or SiO2 D 5

7 Ge MOS and Solutions Surface Passivation Issues Thermal [1] GeO 2, Ge 3 N 4 Interfacial Layers (IL) with High-k Ultra-thin [2] GeO 2 IL using SPA radical oxidation Ultra Shallow Junctions [2] Plasma Immersion Ion Implantation (P-III) High Dopant Activation Laser Thermal Processing (LTP) [3] Rapid Thermal Annealing (RTA) [4] Mobility Booster- Uniaxial Stress Engineering G [5] BTBT Reduction - Si-Ge-Si Hetero-structure design S D [6] Ge [1] T. Nishimura et al., VLSI Symp [ 2 ] G.Thareja et al, Dev. Res. Conf., 2010 [ 3 ] G.Thareja et al., IEDM 2010 [ 4 ] G. Thareja et al., Elec. Dev. Lett. (under prep), Si or SiO2 [ 5 ] M. Kobayashi et al, VLSI Symp. 2009, [ 6 ] T. Krishnamohan et al, VLSI Symp

8 GeO 2 Growth Rate Radical vs thermal oxidation No orientation dependence was observed in radical oxidation between (100) and (111) Ge [1] This was confirmed on silicon previously Oxide thickness (nm) Thermal oxidation Atmospheric (760Torr) (100) Ge (111) Ge Oxidation time (min) 550 o C 500 o C 450 o C Oxide thickness (nm) SPA radical oxidation 4kW 5Torr Ar:O 2 =1200:400 (100) Ge (111) Ge Oxidation time (min) 450 o C 400 o C 350 o C [1] M.Kobayashi, G.Thareja et al, J. Appl. Phys.,

9 D it of GeO 2 /Ge Comparison between GeO x N y and GeO 2 D it was measured by conductance method Significant improvement from GeON Achieved D it ~ 2x10 11 cm -2 ev -1 at midgap Interface state density (cm -2 ev -1 ) Al/Al 2 O 3 /GeON or GeO 2 /Ge GeON D it improvement 1nm GeO 2 2nm GeO Energy from midgap (ev) E c Aluminum (M) ALD high-k SPA Interfacial Layer (IL) Bulk Ge [1] G.Thareja et al., Dev. Res. Conf.,

10 Thermal Stability of Gate Stack GeO 2 /Ge Significant GeO 2 decomposition and GeO out-diffusion Al 2 O 3 /GeO 2 /Ge Al 2 O 3 works as an outdiffusion barrier and maintains GeO 2 Suboxide formation Intensity (arb. unit) GeO 2 /Ge w/o cap As grown 500 o C 1min 550 o C 1min 600 o C 1min Significant GeO 2 desorption Intensity (arb. unit) Al 2 O 3 cap/geo 2 /Ge No significant desorption As deposited 500 o C 1min 550 o C 1min 600 o C 1min Small increase of suboxide Binding energy (ev) Binding energy (ev) [1] M.Kobayashi, G.Thareja et al, J. Appl. Phys.,

11 GeO 2 : Growth Rate, D it, Scalability Capacitance ( μf / cm 2 ) D it at midgap (cm -2 /ev) Orientation / Resistivity (Ω cm) Ge(100)/0.014 Ge(110)/0.44 Ge(111)/0.025 GeO 2 IL + High-k Ge(100) Ge(110) - 40C, 1MHz Similar EOT GeO 2 IL + High-k Gate Voltage (V) Ge(111) no IL Ge(100) Substrate Orientation Gate Leakage V FB + 1 (A/cm 2 ) 6A GeO 2 No IL GeO 2 IL EOT (nm) Substrate orientation independent growth rate and D it, Ultra thin IL have be realized Capacitance ( μf / cm 2 ) Quasi-static CV Orientation / Resistivity Ge(100)/0.014 Ge(110)/0.44 Ge(111)/0.025 Gate Voltage (V) 10

12 Drive Current, Mobility Enhancement Electron Mobility (cm 2 /V-s) Drain Current (A/μm) V ds = 10 mv, W/L = 100μm/ 20μm Current Enhancement Ge (100) no IL Ge(100) Ge(111) Gate Voltage (V) GeO 2 IL; Ge (100) no IL Ge(100) GeO 2 IL; Ge(111) Effective Field (MV/cm) Transconductance (A/V) 18.0µ V ds 15.0µ 12.0µ 9.0µ 6.0µ 3.0µ 0.0 = 10 mv, W/L = 100μm/ 20μm GeO 2 IL; Ge (100) no IL Ge(100) GeO 2 IL; Ge(111) Gate Voltage (V) Ge(111) has higher mobility lower m* Samples without GeO 2 poor mobility - interface/coulomb scattering [1] G.Thareja et al., Elec. Dev. Let. (submitted),

13 S/D Junction Depth (X j ) Scaling V TH I off Short Channel Effect (SCE) L g, Source & Drain interact V TH, I off Drain Induced Barrier Lowering (DIBL) exacerbates SCE Scaling sub-10nm X j T ox, W dep, X j SCE EE311 Adv. IC Fabrication Process, Prof. Krishna Saraswat, Stanford University 12

14 USJ Route Ion Implantation (I/I) Ultra Low Energy - Deceleration mode Issues Low beam current longer implant time low throughput Energy contamination due to neutrals Beam Spreading Wafer non-uniformity issues Some respite by molecular implants Gas Cluster Ion Beam (GCIB) Plasma Immersion Ion Implantation (P-III) ANODE Plasma Region CATHODE Ionic Sheath Wafer 13

15 Plasma Immersion Ion Implantation (P-III) Applied Materials Plasma created above the wafer Pulsed voltage applied on the wafer Ion acceleration and implantation 14

16 P-III in Ge Concentration (cm -3 ) kv, 1x1015 cm kv, 1X10 15 cm SIMS P-III (Phosphorus) Depth (A ) X j < 5 x cm -3 Shallower junctions possible Scaling the voltage Using arsenic species SIMS PIII (Boron) 1.2 kv, 1x10 15 cm kv, 1x10 15 cm Depth (A ) G.Thareja et al. Ultra Shallow Junctions in Germanium for sub-22nm ITRS Technology Node, IEEE Electron Device Letters, 2010 (under preparation) 15

17 Poor Dopant Activation: Parasitic Resistance N sd x j Impact of series resistance Decrease gate overdrive g m reduction Resistance scaling Channel resistance scalable Contact resistance not scalable R sh N 1 sd x j R c Φ exp N eff B, 1 / 2 sd area J. Woo et al., TED

18 R c Φ B eff E FM Φ exp N Contact Resistance eff B, 1 / 2 sd area Doping, R c Thermionic emission (TE) Field emission (FE) E FS 1 Contact resistance (Ω-cm 2 ) Metal/Ge contact Φ B = 0.6eV 0.5eV 0.4eV 0.3eV 0.2eV 0.1eV 0eV Doping concentration (cm -3 ) 17

19 Doping in Ge P type dopant (B) has high solid solubility and low diffusivity Problems with N type dopants: Lower solid solubility High S/D resistance High diffusivity Shallow junctions?? Problems for NMOS Chui, Kulig, Moran, Tsai and Saraswat, Appl. Phys. Lett., 87, , (2005). 18

20 N-type Dopant Activation in Ge Ion implantation generates damage in Ge. Damage centers form acceptor level defects [1,2] Compensates the donor electrical activation E c E F -AV- Negatively charged acceptor state E V [1] A. Chroneos et al., J. Appl. Phys., , 2008 [2] V.P. Markevich et al., Phys. Rev. B, ,

21 Dopant Activation for USJ in Ge Laser Thermal Processing (LTP) High dopant activation Reduced diffusion Implantation damage annihilation (Melt Regrowth) 20

22 LTP Setup - I Main hardware components Monitor CCD Camera HeNe Laser 633nm Fast Digitizing Oscilloscope Nd:YAG Laser Optics X-Y Stage Doubled YAG =532nm. Computer Applied Materials 21

23 LTP Setup - II Homogenous Laser Beam Probe Laser Beam X-Y Stage Applied Materials Die by Die Laser Annealing 22

24 LTP Parameters Parameter Wavelength (λ) [532 nm] Pulse Width (t) [10s of nsec] Laser Fluence (J/cm 2 ) [variable] Effect Absorbance and Reflectivity Annealing fluence threshold Melt Depth 23

25 Concentration (cm -3 ) Sheet Resistance (Ω / ) Sheet Resistance & SIMS Fluence (J-cm -2 ) P3I - P - 1.2kV, 1x10 15 cm -2 as implanted LTP 0.3 LTP:0.4 Jcm -2 Dopant Diffusion Depth (nm) B Sb P As Laser Fluence Dopant diffusion Sheet Resistance P3I- As - 3kV, 1x10 15 cm -2 as implanted LTP 0.3 LTP:0.4 Jcm -2 Dopant Diffusion Depth (nm) I/I - Sb - 10keV, 1x10 15 cm -2 Dopant Diffusion 24 as implanted LTP:0.4 Jcm Depth (nm)

26 Sheet Resistance and TEM Sheet Resistance (Ω / ) as implanted Melt initiates (confirmed using reflectivity of HeNe laser) Melt Penetrates incompletely Polycrystalline films Melt Penetrates completely (Crystalline films) Optimized Fluence Low Fluence Poly Films Laser Fluence (J-cm -2 ) 25

27 Crystallinity of LTP Junctions Intensity (arb. units) After LTP c-ge a-ge Sb - Ion c-ge Implanted Wavenumber (cm -1 ) Crystallinity restoration confirmed using Raman [1] G.Thareja et al, IEDM,

28 Dopant Activation using LTP Concentration (cm -3 ) Post LTP 0.7 Jcm -2 P:P3I As:P3I Sb B:P3I SRP profiles Depth (nm) Annealing Technique Dopant Electrical Activation (cm -3 ) Furnace Anneal [1] P 8 x Rapid Thermal P / As / Anneal (RTA) [2] Sb / B 2 x / 8x x / 1x10 20 Flash Anneal [3] P 6x10 19 In-situ doping [4] P 1x10 19 This Work (LTP) P/ As / Sb / B > 1 x Dopant Activation > 1 x cm -3 [1] D.Kuzum, et al., IEDM, 2009, 453, [2] C.O.Chui, et al. APL, 83, 3275, 2003, [3] C. Wundisch, et al. 95, , 2009, [4]H.-Y. Yu, et al. 685, IEDM

29 High Performance N + /P Ge Diodes P : P-III As : P-III Sb: I/I 10-3 LTP J / cm Voltage (V) I on / I off > 1 x 10 5, <

30 Sheet Resistance, SRP Sheet Resistance (Ω / ) ρ s measured using Capres MicroRsp P (10 kev, 1x10 15 cm -2 ) As (20 kev, 1x10 15 cm -2 ) Sb (30 kev, 1x10 15 cm -2 ) Laser Fluence (J-cm -2 ) Sb provides the lowest R s 29

31 High Performance N + /P Diode Junction Current (A/cm 2 ) ln (JR) >10 5 η = 1.18 n + / p Diode Substrate doping ~ 0.1Ω - cm Junction Voltage (V) E a ~ 0.37 ev Junction Current (A/cm 2 ) High I on / I off, η < 1.2 I diode (A/cm 2 ) Measurement Temperature 323K 293K 273K 258K 233K 185K Junction Voltage (V) I off reduces Nsub > 30 Ω-cm Laser Fluence 0.2 J/cm J/cm J/cm J/cm /T (K -1 ) Voltage (V) E a ~ E g / 2, No defect assisted current Junction formed at 0.5 J/cm 2 30

32 Contact Resistivity (ρ c ) & Benchmark Contact Resistivity (Ω - cm 2 ) orders Ref [4] reduction in ρ c This work Resistance (Ω) Ref [4] TLM Contact Structure with isolation This work, ρ c ~ 7x10-7 Ω-cm Contact Spacing (μm) Significant reduction in Metal / N + Ge ρ c of 7 x 10-7 Ω-cm 2 [4] J. Oh et al., VLSI 2009, p. 238 [1] G.Thareja et al, IEDM,

33 Gate First MOSFET Process Gate Pad S D Aluminum (low m ) reflective across a wide wavelength range Bright Field Image: Single pulse laser shot No visible damage effect on transistor structure Laser Al Gate Oxide Source Drain [1] G.Thareja et al, IEDM, 2010 Germanium Substrate 32

34 MOSFET results I drain, I source (A/μm) V ds = 1V Drain Current Source Current N sub > 30 ohm-cm, L = 20μ m Laser Fluence = 0.5 J/cm V gate (V) I drain, I source (A/μm) N sub > 30 ohm-cm, L = 100μ Laser Fluence = 0.3 J/cm 2 V ds = 10mV I doff > I soff V gate (V) Drain Current Source Current Unoptimized laser fluence causes discrepancy between I drain and I source due to high diode leakage 33

35 Contributions First demonstration of High dopant activation (> 1x10 20 cm -3 ) using Sb dopants (n-type) in Ge Well behaved n + /p diodes (I on /I off > 1x10 5, η < 1.2) and MOSFETs. Lowest contact resistivity for metal(ti/al)-n + Ge contacts (7x10-7 Ω-cm 2 ) Ultra Shallow Junctions (X j < 10nm) for Ge Scalable GeO 2 Interfacial Layers (IL) (sub -1nm) for Ge MOS with performance enhancement for Ge NMOSFET Substrate orientation independent growth rate and D it for GeO 2 engineered using SPA oxide 34

36 Future Work Short channel MOSFETs combining P-III and laser annealing. Thermal stability of high dopant activation in Ge Alternate methods to obtain high dopant activation Reliability analysis of dielectrics for Ge with reduced EOT 35

37 Thank you for your time & patience! 36