Lect. 2: Basics of Si Technology

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1 Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing

2 1. Thin Film Deposition Layer of materials ranging from fractions of nanometer to several micro-meters in thickness - Types of Thin Film Deposition Physical Vapor Deposition (PVD) - Vaporized materials bombard onto substrate Chemical Vapor Deposition (CVD) - Gaseous materials react on substrate

3 Physical Vapor Deposition (PVD) Evaporation (Thermal, E-beam) Sputtering (DC, RF, Ion beam) Aluminum, Copper, Titanium, Tungsten silicide

4 Chemical Vapor Deposition (CVD) Gases react on the substrate to form the desired thin films LPCVD (Low Pressure) PECVD (Plasma Enhanced) LACVD (Laser Assisted) MOCVD (Metal Organic)

5 2. Etching Wet Etching Reactants Products Reaction -SiO 2 etching by HF -Si 3 N 4 etching by H 3 PO 4 - Si etching by KOH -Wet etching avoided if possible: hazard materials, undercut Film Semiconductor Solution

6 - Dry etching: chemical reaction with gases to eliminate desired material - RIE (Reactive Ion Etching), ICP (Inductive Coupled Plama), IBE (Ion Beam Etching) Typical parallel-plate reactive ion etching system

7 3. Ion Implantation Ions are accelerated by potential difference and implanted into the substrate Ion implantation for dopoing Ex) p+, n+, p-well, n-well etc. 7

8 4. Photolithography Produces patterns on substrate by transferring mask patterns onto the substrate. Basically lithographic printing PR coating Deposition Exposure PR strip Developing Etching <Flow of Photolithography>

9 5. Chemical Mechanical Polishing (CMP) Makes the wafer surface flat for better lithography Chemical Mechanical Planarization(CMP) combines chemical action with mechanical abrasion to achieve selective material removal through polishing

10 CMOS inverer Layout Invertor Source Drain Gate Metal 1

11 CMOS Structure Lect. 2: Basics of Si Technology Polysilicon Metal 1 Gate Oxide Dielectric SiN Spacer silicide P+ N+ STI N-well P-substrate

12 Shallow Trench Isolation(STI) Active region SiO Silicon dioxide P-substrate

13 Well Formation Active region N-well P-substrate

14 Gate and Source/Drain Formation Gate Drain & Source Poly Silicon Thin Gate Oxide P+ N+ N-well Gate Oxide Formation Photolithography Ion implantation P-substrate

15 Contacts and Metallization Lect. 2: Basics of Si Technology Metal 1 Metal 1 Dielectric SiN Spacer silicide N-well P-substrate

16 CMOS Fabrication Result Lect. 2: Basics of Si Technology Polysilicon Metal 1 ThinGateOxide Dielectric SiN Spacer silicide P+ N+ STI N-well P-substrate

17 - CMOS Circuit Design Process

18 Design examaple: CMOS inverter Schematic Simulation (Synopsis HSPICE, Cadence SPECTRE) <Inverter schematic>

19 Layout (Cadence VIRTUOSO) Lect. 2: Basics of Si Technology

20 Rule Checking (Mentor CALIBRE, Synopsis HERCULES, Cadence ASSURA) - Design Rule Checking (DRC) Check no design rules for a given process is violated during layout - Layout vs. Schematic (LVS) Make sure layout is identical to schematic - These rule checking must be satisfied before fabrication can start

21 Parasitic RC extraction (Synopsis StarRC) Lect. 2: Basics of Si Technology

22 Post Layout Simulation Lect. 2: Basics of Si Technology Pre-sim Po-sim Pre-sim Po-sim - Modify your design if needed

23 - Complicated Digital Circuit Design - Impossible to do transistor-level simulation - Impossible to layout by hands Behavior-level design using Hardware Description Language (Mentor ModelSim)

24 Lect. 2: Basics of Si Technology - Automatic Gate-level Synthesis (Synopsis Design_Vision) -Auto Layout (Synopsis Astro)

25 Lect. 2: Basics of Si Technology Example <Layout> <Fabricated chip>

26 SOI (Silicon on Insulator): A thin layer of silicon crystal on top of insulator on the top on insulator Thin Film Silicon Layer Buried Oxide Silicon Substrate Why SOI wafer? < SOI Wafer > MOS devices on SOI is more robust again many short channel effects, leading to faster operation with less power consumption

27 Thin Film Silicon Layer Buried Oxide Silicon Substrate < SOI Wafer > Used by IBM and Freescale for high-performance microprocessors but lost to Intel's bulk Si technology Widely used in Si Photonics

28 SIMOX (Separation by Implantation of Oxygen) 1. Deep implantation of a high dose oxygen into silicon wafer the synthesis of BOX μm thick underneath a thin silicon film 2. Low and high temperature annealing low temperature: inhomogeneous silicon film high temperature: improving and simplifying the vertical SOI structure Oxygen ion implantation Annealing Silicon overlayer Buried Oxide Silicon Substrate Silicon Substrate

29 BESOI (Bond-and-Etch-back SOI) 1. Bonding of two oxidized silicon wafer 2. Polishing/etching back of one of the wafer Two bulk wafers are required to achieve one SOI wafer Si wafer (future SOI layer) Polishing/etching SiO 2 Buried Oxide SiO 2 Si-handle wafer Silicon Substrate Bonding Etch-back

30 Combined two technology Smart-Cut process

31 Smart-Cut Process Surface Oxidation onto wafer Reuse Wafer Surface Oxidation Wafer Handle Wafer Implantation of hydrogen into wafer Deposition of a thick layer or bonding wafer to another wafer Heat treatment inducing splitting H implant Wafer Flip and bond to handle wafer Break CMP and cut SOI Wafer Polishing and cutting Handle Wafer Reuse