Various Techniques for Reliability Estimation and Failure Analysis of Electronic Products and Components

Size: px
Start display at page:

Download "Various Techniques for Reliability Estimation and Failure Analysis of Electronic Products and Components"

Transcription

1 JFE No p Various Techniques for Reliability Estimation and Failure Analysis of Electronic Products and Components BAN Mitsuyuki SHIMAUCHI Yutaka JFE JFE JFE X IC Pb Abstract: JFE Techno-Research has been working on the reliability estimation and failure analysis. In this paper, the authors introduce the failure analyses for IC products and printed circuit boards in which electronic devices are mounted with Pb free solder, using the techniques of transmission X-ray microscope, scanning electron microscope, and transmission electron microscope. 1. EU RoHS Sn-Pb Pb JFE 2. IC IC IC Fig. 1 X X Au Nondestructive inspection External observation Electric property (Open/Short, Diode characteristic) Transmission X-ray observation Scanning acoustic tomograph Destructive inspection Package open Chip surface observation Liquid crystal method Emission microscope ex. Layer removing FIB machining-sem observation TEM observation Cross-section observation Delamination between resin and Chip Au wire bonding Die bonding, etc. Fig. 1 Flow of failure analysis on IC 97

2 Lead frame Broken Au wire Al corrosion Au wire bonding Chip Au wire bonding 100 µm Photo 1 Transmission X-ray image of broken Au wire Photo 3 Optical microscope image for corrosion part of Al wiring Lead frame Chip FIB focused ion beam SEM scanning electron microscopy TEM transmission electron microscopy Delaminate area 3 mm Photo 2 SAT image of delamination between chip and resin 3. Photo 1 Au Au Au SAT scanning acoustic tomograph Photo C 1 Au IC 2 Photo 3 Al 3.1 JIS Z Fig Sn Sn-Cu Sn-Bi Sn-Ag Sn-Pb Sn Ni Au 98

3 Specimen State of getting wet Sueface of solder liquid Period when it begin to get wet Period when it gets wet Action power Heating beginning 2 3 F max Amount of solder adhesion Maximum wet power (F max ) Final wet power (F end ) FIg. 2 Minimum wet power Wet period Time Schematic diagram of methods for solerbility test by a wetting balance method SEM Photo 4 Cu Ni Sn 150 C 40 h 120 h 120 h Sn Ni 3 Sn Au Au SIM scanning ion microscopy Photo 5 Cu Ni Au Au 50 nm Au Au Ni Au Ni 4 Ni Sn plate Sn plate Intermetallic compound Intermetallic compound Intermetallic compound Ni plate Ni plate Ni plate Cu alloy Cu alloy Cu alloy (a) As plated (b) After heating (150 C 40 h) (c) After heating (150 C 120 h) Photo 4 SEM image of cross section for Sn plate 2 µm Corrrosion product W coating Au plating Corrrosion products of Ni plating Ni plating Cu alloy Corrrosion products of Ni plating 1 µm 1 µm (a) Top view (b) Cross section (45 Tilt observation) Photo 5 SIM image of corrosion products of Au plating on Ni plating 99

4 Au JIS Z JIS Z Fig. 3 4 QFP quad fl at package IC SEM Photo 6 Pb FIg Pull Hook jig QFP (Quad flat package) Lead joint Substrate Schematic diagram of method for 45 pull test of solder joints on QFP lead Diameter 0.5 mm Boad electrode FIg. 4 External electlode Shearing jig Chip components Top view Shearing jig Substrate Shearing speed 5 30 mm/min Substrate Interval between jig and substrate: less of part thickness Side view Schematic diagram of methods for shear strength of solder joints chip components 1 4 Package Lead Crack Substrate 375 µm Photo 6 SEM image of cross section of solder joint after heat-cycle examination of 500 cycles Sn-3.5%Ag-0.5%Cu 40 C 125 C 30 min SEM SIM SEM SIM Photo 7 SEM SIM SIM Ni 6, TEM TEM Photo 8 Ni Au Sn- 3.5%Ag-0.5Cu 150 C 240 h Ni-P P Ni-P Au- Ni-Cu-Sn 8,9 P Ni-P Pb

5 SEM image SIM image Intermetallic compund Ni plating Cu Refined 3 µm 1 µm Photo 7 Comparison between SEM image and SIM image of cross section for solder joint Intermetalic compund layer (Au, Cu, Ni, Sn) Chip condenser Intermetallic conpound (Cu-Sn) Closeup P rich layer of Ni-P plating Void Ni-P plating 100 nm Initial state After 150 C 240 h Photo 8 TEM image of cross section for Ni-P/Au/ 4 3,11 5 3,12, Photo 9 Cu Sn-Pb Cu Cu Sn Cu land Photo 9 Cu land Void 275 µm 3 µm SEM image of cross section of solder joint for chip condenser Photo 10 Sn Sn-Pb 2 Sn-8%Zn-3%Bi Pb 40 C 125 C 30 min 700 Sn Sn-8%Zn-3%Bi Sn- Pb Sn-8%Zn-3%Bi Photo 11 EPMA electron probe microanalysis Sn Pb Bi Sn Pb Bi Sn plating /Sn-8Zn-3Bi Lead Crack Sn- Pb plating /Sn-8Zn-3Bi Void and crack 200 µm Photo 10 SEM image of cross section for solder joint after heat-cycle examination of 700 cycles 101

6 Sn Bi Pb 5 µm Photo 11 EPMA mapping of Sn,Pb and Bi for joint of Sn-Pb plating and Sn-Zn-Bi solder, in which voids are observed 100 C Sn Pb Bi C 3 4. X IC JFE p p TSOP mate p Ni/Au BGA mate2006 p Ni Al vol. 50 no p Sn-Ag Ni-P/Au CSP mate p TEM 3 mate2006 p p SMT 1994 p p p p p p